Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:
 "Random fixes across the MIPS tree.  The two hotspots are several bugs
  in the module loader and the ath79 SOC support; also noteworthy is the
  restructuring of the code to synchronize CPU timers across CPUs on
  startup; the old code recently ceased to work due to unrelated
  changes.

  All except one of these patches have sat for a significant time in
  linux-next for testing."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: pci-ar724x: avoid data bus error due to a missing PCIe module
  MIPS: Malta: Delete duplicate PCI fixup.
  MIPS: ath79: don't hardcode the unavailability of the DSP ASE
  MIPS: Synchronize MIPS count one CPU at a time
  MIPS: BCM63xx: Fix SPI message control register handling for BCM6338/6348.
  MIPS: Module: Deal with malformed HI16/LO16 relocation sequences.
  MIPS: Fix race condition in module relocation code.
  MIPS: Fix memory leak in error path of HI16/LO16 relocation handling.
  MIPS: MTX-1: Add udelay to mtx1_pci_idsel
  MIPS: ath79: select HAVE_CLK
  MIPS: ath79: Use correct IRQ number for the OHCI controller on AR7240
  MIPS: ath79: Fix number of GPIO lines for AR724[12]
  MIPS: Octeon: Fix broken interrupt controller code.

7 files changed, 20 insertions, 18 deletions

diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 1caa78ad06d5..dde504477fac 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -393,7 +393,8 @@
 #define AR71XX_GPIO_REG_FUNC            0x28
 
 #define AR71XX_GPIO_COUNT               16
-#define AR724X_GPIO_COUNT               18
+#define AR7240_GPIO_COUNT               18
+#define AR7241_GPIO_COUNT               20
 #define AR913X_GPIO_COUNT               22
 #define AR933X_GPIO_COUNT               30
 #define AR934X_GPIO_COUNT               23
diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
index 4476fa03bf36..6ddae926bf79 100644
--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -42,7 +42,6 @@
 #define cpu_has_mips64r1        0
 #define cpu_has_mips64r2        0
 
-#define cpu_has_dsp             0
 #define cpu_has_mipsmt          0
 
 #define cpu_has_64bits          0
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
index 7d98dbe5d4b5..c9bae1362606 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -9,6 +9,8 @@ int __init bcm63xx_spi_register(void);
 
 struct bcm63xx_spi_pdata {
         unsigned int    fifo_size;
+        unsigned int    msg_type_shift;
+        unsigned int    msg_ctl_width;
         int             bus_num;
         int             num_chipselect;
         u32             speed_hz;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 4ccc2a748aff..61f2a2a5099d 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -1054,7 +1054,8 @@
 #define SPI_6338_FILL_BYTE              0x07
 #define SPI_6338_MSG_TAIL               0x09
 #define SPI_6338_RX_TAIL                0x0b
-#define SPI_6338_MSG_CTL                0x40
+#define SPI_6338_MSG_CTL                0x40    /* 8-bits register */
+#define SPI_6338_MSG_CTL_WIDTH          8
 #define SPI_6338_MSG_DATA               0x41
 #define SPI_6338_MSG_DATA_SIZE          0x3f
 #define SPI_6338_RX_DATA                0x80
@@ -1070,7 +1071,8 @@
 #define SPI_6348_FILL_BYTE              0x07
 #define SPI_6348_MSG_TAIL               0x09
 #define SPI_6348_RX_TAIL                0x0b
-#define SPI_6348_MSG_CTL                0x40
+#define SPI_6348_MSG_CTL                0x40    /* 8-bits register */
+#define SPI_6348_MSG_CTL_WIDTH          8
 #define SPI_6348_MSG_DATA               0x41
 #define SPI_6348_MSG_DATA_SIZE          0x3f
 #define SPI_6348_RX_DATA                0x80
@@ -1078,6 +1080,7 @@
 
 /* BCM 6358 SPI core */
 #define SPI_6358_MSG_CTL                0x00    /* 16-bits register */
+#define SPI_6358_MSG_CTL_WIDTH          16
 #define SPI_6358_MSG_DATA               0x02
 #define SPI_6358_MSG_DATA_SIZE          0x21e
 #define SPI_6358_RX_DATA                0x400
@@ -1094,6 +1097,7 @@
 
 /* BCM 6358 SPI core */
 #define SPI_6368_MSG_CTL                0x00    /* 16-bits register */
+#define SPI_6368_MSG_CTL_WIDTH          16
 #define SPI_6368_MSG_DATA               0x02
 #define SPI_6368_MSG_DATA_SIZE          0x21e
 #define SPI_6368_RX_DATA                0x400
@@ -1115,7 +1119,10 @@
 #define SPI_HD_W                        0x01
 #define SPI_HD_R                        0x02
 #define SPI_BYTE_CNT_SHIFT              0
-#define SPI_MSG_TYPE_SHIFT              14
+#define SPI_6338_MSG_TYPE_SHIFT         6
+#define SPI_6348_MSG_TYPE_SHIFT         6
+#define SPI_6358_MSG_TYPE_SHIFT         14
+#define SPI_6368_MSG_TYPE_SHIFT         14
 
 /* Command */
 #define SPI_CMD_NOOP                    0x00
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 418992042f6f..c22a3078bf11 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -21,14 +21,10 @@ enum octeon_irq {
         OCTEON_IRQ_TIMER,
 /* sources in CIU_INTX_EN0 */
         OCTEON_IRQ_WORKQ0,
-        OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
-        OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
+        OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16,
         OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
         OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
         OCTEON_IRQ_MBOX1,
-        OCTEON_IRQ_UART0,
-        OCTEON_IRQ_UART1,
-        OCTEON_IRQ_UART2,
         OCTEON_IRQ_PCI_INT0,
         OCTEON_IRQ_PCI_INT1,
         OCTEON_IRQ_PCI_INT2,
@@ -38,8 +34,6 @@ enum octeon_irq {
         OCTEON_IRQ_PCI_MSI2,
         OCTEON_IRQ_PCI_MSI3,
 
-        OCTEON_IRQ_TWSI,
-        OCTEON_IRQ_TWSI2,
         OCTEON_IRQ_RML,
         OCTEON_IRQ_TIMER0,
         OCTEON_IRQ_TIMER1,
@@ -47,8 +41,6 @@ enum octeon_irq {
         OCTEON_IRQ_TIMER3,
         OCTEON_IRQ_USB0,
         OCTEON_IRQ_USB1,
-        OCTEON_IRQ_MII0,
-        OCTEON_IRQ_MII1,
         OCTEON_IRQ_BOOTDMA,
 #ifndef CONFIG_PCI_MSI
         OCTEON_IRQ_LAST = 127
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 7531ecd654d6..dca8bce8c7ab 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -10,6 +10,7 @@ struct mod_arch_specific {
         struct list_head dbe_list;
         const struct exception_table_entry *dbe_start;
         const struct exception_table_entry *dbe_end;
+        struct mips_hi16 *r_mips_hi16_list;
 };
 
 typedef uint8_t Elf64_Byte;             /* Type for a 8-bit quantity.  */
diff --git a/arch/mips/include/asm/r4k-timer.h b/arch/mips/include/asm/r4k-timer.h
index a37d12b3b61c..afe9e0e03fe9 100644
--- a/arch/mips/include/asm/r4k-timer.h
+++ b/arch/mips/include/asm/r4k-timer.h
@@ -12,16 +12,16 @@
 
 #ifdef CONFIG_SYNC_R4K
 
-extern void synchronise_count_master(void);
-extern void synchronise_count_slave(void);
+extern void synchronise_count_master(int cpu);
+extern void synchronise_count_slave(int cpu);
 
 #else
 
-static inline void synchronise_count_master(void)
+static inline void synchronise_count_master(int cpu)
 {
 }
 
-static inline void synchronise_count_slave(void)
+static inline void synchronise_count_slave(int cpu)
 {
 }