diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-08-25 18:28:57 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-08-25 18:28:57 -0400 |
commit | 497c01dda9a6abc969573ba999a86ed04a835e76 (patch) | |
tree | 6eeb184184f3190bb19f96544125fdf5576a3840 /arch/mips/include/asm/syscall.h | |
parent | 01e9982ab39a1279adcb5d8741fd912870dc3d4b (diff) | |
parent | 608308682addfdc7b8e2aee88f0e028331d88e4d (diff) |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"Pretty much all across the field so with this we should be in
reasonable shape for the upcoming -rc2"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: OCTEON: make get_system_type() thread-safe
MIPS: CPS: Initialize EVA before bringing up VPEs from secondary cores
MIPS: Malta: EVA: Rename 'eva_entry' to 'platform_eva_init'
MIPS: EVA: Add new EVA header
MIPS: scall64-o32: Fix indirect syscall detection
MIPS: syscall: Fix AUDIT value for O32 processes on MIPS64
MIPS: Loongson: Fix COP2 usage for preemptible kernel
MIPS: NL: Fix nlm_xlp_defconfig build error
MIPS: Remove race window in page fault handling
MIPS: Malta: Improve system memory detection for '{e, }memsize' >= 2G
MIPS: Alchemy: Fix db1200 PSC clock enablement
MIPS: BCM47XX: Fix reboot problem on BCM4705/BCM4785
MIPS: Remove duplicated include from numa.c
MIPS: Add common plat_irq_dispatch declaration
MIPS: MSP71xx: remove unused plat_irq_dispatch() argument
MIPS: GIC: Remove useless parens from GICBIS().
MIPS: perf: Mark pmu interupt IRQF_NO_THREAD
Diffstat (limited to 'arch/mips/include/asm/syscall.h')
-rw-r--r-- | arch/mips/include/asm/syscall.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h index 17960fe7a8ce..cdf68b33bd65 100644 --- a/arch/mips/include/asm/syscall.h +++ b/arch/mips/include/asm/syscall.h | |||
@@ -131,10 +131,12 @@ static inline int syscall_get_arch(void) | |||
131 | { | 131 | { |
132 | int arch = EM_MIPS; | 132 | int arch = EM_MIPS; |
133 | #ifdef CONFIG_64BIT | 133 | #ifdef CONFIG_64BIT |
134 | if (!test_thread_flag(TIF_32BIT_REGS)) | 134 | if (!test_thread_flag(TIF_32BIT_REGS)) { |
135 | arch |= __AUDIT_ARCH_64BIT; | 135 | arch |= __AUDIT_ARCH_64BIT; |
136 | if (test_thread_flag(TIF_32BIT_ADDR)) | 136 | /* N32 sets only TIF_32BIT_ADDR */ |
137 | arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32; | 137 | if (test_thread_flag(TIF_32BIT_ADDR)) |
138 | arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32; | ||
139 | } | ||
138 | #endif | 140 | #endif |
139 | #if defined(__LITTLE_ENDIAN) | 141 | #if defined(__LITTLE_ENDIAN) |
140 | arch |= __AUDIT_ARCH_LE; | 142 | arch |= __AUDIT_ARCH_LE; |