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authorDavid Daney <david.daney@cavium.com>2012-05-11 17:34:45 -0400
committerJohn Crispin <blogic@openwrt.org>2012-08-22 17:46:38 -0400
commit95d585fc289cae216b5abed65bb3dbc85b5d91d4 (patch)
treee2b54aa01e97a650e514cf4076d9f6abfd97548f /arch/mips/include/asm/octeon/cvmx-mpi-defs.h
parent1c5992427b8c7d61052a3eaac05e98791c6163b7 (diff)
MIPS: OCTEON: Add register definitions for SPI host hardware.
Needed by SPI driver. Signed-off-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/3796/ Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-mpi-defs.h')
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mpi-defs.h328
1 files changed, 328 insertions, 0 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-mpi-defs.h b/arch/mips/include/asm/octeon/cvmx-mpi-defs.h
new file mode 100644
index 000000000000..4615b102625b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mpi-defs.h
@@ -0,0 +1,328 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MPI_DEFS_H__
29#define __CVMX_MPI_DEFS_H__
30
31#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
32#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
33#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
34#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
35
36union cvmx_mpi_cfg {
37 uint64_t u64;
38 struct cvmx_mpi_cfg_s {
39#ifdef __BIG_ENDIAN_BITFIELD
40 uint64_t reserved_29_63:35;
41 uint64_t clkdiv:13;
42 uint64_t csena3:1;
43 uint64_t csena2:1;
44 uint64_t csena1:1;
45 uint64_t csena0:1;
46 uint64_t cslate:1;
47 uint64_t tritx:1;
48 uint64_t idleclks:2;
49 uint64_t cshi:1;
50 uint64_t csena:1;
51 uint64_t int_ena:1;
52 uint64_t lsbfirst:1;
53 uint64_t wireor:1;
54 uint64_t clk_cont:1;
55 uint64_t idlelo:1;
56 uint64_t enable:1;
57#else
58 uint64_t enable:1;
59 uint64_t idlelo:1;
60 uint64_t clk_cont:1;
61 uint64_t wireor:1;
62 uint64_t lsbfirst:1;
63 uint64_t int_ena:1;
64 uint64_t csena:1;
65 uint64_t cshi:1;
66 uint64_t idleclks:2;
67 uint64_t tritx:1;
68 uint64_t cslate:1;
69 uint64_t csena0:1;
70 uint64_t csena1:1;
71 uint64_t csena2:1;
72 uint64_t csena3:1;
73 uint64_t clkdiv:13;
74 uint64_t reserved_29_63:35;
75#endif
76 } s;
77 struct cvmx_mpi_cfg_cn30xx {
78#ifdef __BIG_ENDIAN_BITFIELD
79 uint64_t reserved_29_63:35;
80 uint64_t clkdiv:13;
81 uint64_t reserved_12_15:4;
82 uint64_t cslate:1;
83 uint64_t tritx:1;
84 uint64_t idleclks:2;
85 uint64_t cshi:1;
86 uint64_t csena:1;
87 uint64_t int_ena:1;
88 uint64_t lsbfirst:1;
89 uint64_t wireor:1;
90 uint64_t clk_cont:1;
91 uint64_t idlelo:1;
92 uint64_t enable:1;
93#else
94 uint64_t enable:1;
95 uint64_t idlelo:1;
96 uint64_t clk_cont:1;
97 uint64_t wireor:1;
98 uint64_t lsbfirst:1;
99 uint64_t int_ena:1;
100 uint64_t csena:1;
101 uint64_t cshi:1;
102 uint64_t idleclks:2;
103 uint64_t tritx:1;
104 uint64_t cslate:1;
105 uint64_t reserved_12_15:4;
106 uint64_t clkdiv:13;
107 uint64_t reserved_29_63:35;
108#endif
109 } cn30xx;
110 struct cvmx_mpi_cfg_cn31xx {
111#ifdef __BIG_ENDIAN_BITFIELD
112 uint64_t reserved_29_63:35;
113 uint64_t clkdiv:13;
114 uint64_t reserved_11_15:5;
115 uint64_t tritx:1;
116 uint64_t idleclks:2;
117 uint64_t cshi:1;
118 uint64_t csena:1;
119 uint64_t int_ena:1;
120 uint64_t lsbfirst:1;
121 uint64_t wireor:1;
122 uint64_t clk_cont:1;
123 uint64_t idlelo:1;
124 uint64_t enable:1;
125#else
126 uint64_t enable:1;
127 uint64_t idlelo:1;
128 uint64_t clk_cont:1;
129 uint64_t wireor:1;
130 uint64_t lsbfirst:1;
131 uint64_t int_ena:1;
132 uint64_t csena:1;
133 uint64_t cshi:1;
134 uint64_t idleclks:2;
135 uint64_t tritx:1;
136 uint64_t reserved_11_15:5;
137 uint64_t clkdiv:13;
138 uint64_t reserved_29_63:35;
139#endif
140 } cn31xx;
141 struct cvmx_mpi_cfg_cn30xx cn50xx;
142 struct cvmx_mpi_cfg_cn61xx {
143#ifdef __BIG_ENDIAN_BITFIELD
144 uint64_t reserved_29_63:35;
145 uint64_t clkdiv:13;
146 uint64_t reserved_14_15:2;
147 uint64_t csena1:1;
148 uint64_t csena0:1;
149 uint64_t cslate:1;
150 uint64_t tritx:1;
151 uint64_t idleclks:2;
152 uint64_t cshi:1;
153 uint64_t reserved_6_6:1;
154 uint64_t int_ena:1;
155 uint64_t lsbfirst:1;
156 uint64_t wireor:1;
157 uint64_t clk_cont:1;
158 uint64_t idlelo:1;
159 uint64_t enable:1;
160#else
161 uint64_t enable:1;
162 uint64_t idlelo:1;
163 uint64_t clk_cont:1;
164 uint64_t wireor:1;
165 uint64_t lsbfirst:1;
166 uint64_t int_ena:1;
167 uint64_t reserved_6_6:1;
168 uint64_t cshi:1;
169 uint64_t idleclks:2;
170 uint64_t tritx:1;
171 uint64_t cslate:1;
172 uint64_t csena0:1;
173 uint64_t csena1:1;
174 uint64_t reserved_14_15:2;
175 uint64_t clkdiv:13;
176 uint64_t reserved_29_63:35;
177#endif
178 } cn61xx;
179 struct cvmx_mpi_cfg_cn66xx {
180#ifdef __BIG_ENDIAN_BITFIELD
181 uint64_t reserved_29_63:35;
182 uint64_t clkdiv:13;
183 uint64_t csena3:1;
184 uint64_t csena2:1;
185 uint64_t reserved_12_13:2;
186 uint64_t cslate:1;
187 uint64_t tritx:1;
188 uint64_t idleclks:2;
189 uint64_t cshi:1;
190 uint64_t reserved_6_6:1;
191 uint64_t int_ena:1;
192 uint64_t lsbfirst:1;
193 uint64_t wireor:1;
194 uint64_t clk_cont:1;
195 uint64_t idlelo:1;
196 uint64_t enable:1;
197#else
198 uint64_t enable:1;
199 uint64_t idlelo:1;
200 uint64_t clk_cont:1;
201 uint64_t wireor:1;
202 uint64_t lsbfirst:1;
203 uint64_t int_ena:1;
204 uint64_t reserved_6_6:1;
205 uint64_t cshi:1;
206 uint64_t idleclks:2;
207 uint64_t tritx:1;
208 uint64_t cslate:1;
209 uint64_t reserved_12_13:2;
210 uint64_t csena2:1;
211 uint64_t csena3:1;
212 uint64_t clkdiv:13;
213 uint64_t reserved_29_63:35;
214#endif
215 } cn66xx;
216 struct cvmx_mpi_cfg_cn61xx cnf71xx;
217};
218
219union cvmx_mpi_datx {
220 uint64_t u64;
221 struct cvmx_mpi_datx_s {
222#ifdef __BIG_ENDIAN_BITFIELD
223 uint64_t reserved_8_63:56;
224 uint64_t data:8;
225#else
226 uint64_t data:8;
227 uint64_t reserved_8_63:56;
228#endif
229 } s;
230 struct cvmx_mpi_datx_s cn30xx;
231 struct cvmx_mpi_datx_s cn31xx;
232 struct cvmx_mpi_datx_s cn50xx;
233 struct cvmx_mpi_datx_s cn61xx;
234 struct cvmx_mpi_datx_s cn66xx;
235 struct cvmx_mpi_datx_s cnf71xx;
236};
237
238union cvmx_mpi_sts {
239 uint64_t u64;
240 struct cvmx_mpi_sts_s {
241#ifdef __BIG_ENDIAN_BITFIELD
242 uint64_t reserved_13_63:51;
243 uint64_t rxnum:5;
244 uint64_t reserved_1_7:7;
245 uint64_t busy:1;
246#else
247 uint64_t busy:1;
248 uint64_t reserved_1_7:7;
249 uint64_t rxnum:5;
250 uint64_t reserved_13_63:51;
251#endif
252 } s;
253 struct cvmx_mpi_sts_s cn30xx;
254 struct cvmx_mpi_sts_s cn31xx;
255 struct cvmx_mpi_sts_s cn50xx;
256 struct cvmx_mpi_sts_s cn61xx;
257 struct cvmx_mpi_sts_s cn66xx;
258 struct cvmx_mpi_sts_s cnf71xx;
259};
260
261union cvmx_mpi_tx {
262 uint64_t u64;
263 struct cvmx_mpi_tx_s {
264#ifdef __BIG_ENDIAN_BITFIELD
265 uint64_t reserved_22_63:42;
266 uint64_t csid:2;
267 uint64_t reserved_17_19:3;
268 uint64_t leavecs:1;
269 uint64_t reserved_13_15:3;
270 uint64_t txnum:5;
271 uint64_t reserved_5_7:3;
272 uint64_t totnum:5;
273#else
274 uint64_t totnum:5;
275 uint64_t reserved_5_7:3;
276 uint64_t txnum:5;
277 uint64_t reserved_13_15:3;
278 uint64_t leavecs:1;
279 uint64_t reserved_17_19:3;
280 uint64_t csid:2;
281 uint64_t reserved_22_63:42;
282#endif
283 } s;
284 struct cvmx_mpi_tx_cn30xx {
285#ifdef __BIG_ENDIAN_BITFIELD
286 uint64_t reserved_17_63:47;
287 uint64_t leavecs:1;
288 uint64_t reserved_13_15:3;
289 uint64_t txnum:5;
290 uint64_t reserved_5_7:3;
291 uint64_t totnum:5;
292#else
293 uint64_t totnum:5;
294 uint64_t reserved_5_7:3;
295 uint64_t txnum:5;
296 uint64_t reserved_13_15:3;
297 uint64_t leavecs:1;
298 uint64_t reserved_17_63:47;
299#endif
300 } cn30xx;
301 struct cvmx_mpi_tx_cn30xx cn31xx;
302 struct cvmx_mpi_tx_cn30xx cn50xx;
303 struct cvmx_mpi_tx_cn61xx {
304#ifdef __BIG_ENDIAN_BITFIELD
305 uint64_t reserved_21_63:43;
306 uint64_t csid:1;
307 uint64_t reserved_17_19:3;
308 uint64_t leavecs:1;
309 uint64_t reserved_13_15:3;
310 uint64_t txnum:5;
311 uint64_t reserved_5_7:3;
312 uint64_t totnum:5;
313#else
314 uint64_t totnum:5;
315 uint64_t reserved_5_7:3;
316 uint64_t txnum:5;
317 uint64_t reserved_13_15:3;
318 uint64_t leavecs:1;
319 uint64_t reserved_17_19:3;
320 uint64_t csid:1;
321 uint64_t reserved_21_63:43;
322#endif
323 } cn61xx;
324 struct cvmx_mpi_tx_s cn66xx;
325 struct cvmx_mpi_tx_cn61xx cnf71xx;
326};
327
328#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-15 18:24:22 -0400