MIPS: Get rid of hard-coded values for Malta PIIX4 fixups

Make the code more readable by using defines.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6031/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 23 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index a02596cf1abd..06d483131dc4 100644
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -1,6 +1,7 @@
 /*
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
@@ -20,6 +21,28 @@
 #ifndef __ASM_MIPS_BOARDS_PIIX4_H
 #define __ASM_MIPS_BOARDS_PIIX4_H
 
+/* PIRQX Route Control */
+#define PIIX4_FUNC0_PIRQRC                      0x60
+#define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE        (1 << 7)
+#define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK           0xf
+#define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX            16
+/* Top Of Memory */
+#define PIIX4_FUNC0_TOM                         0x69
+#define   PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK            0xf0
+/* Deterministic Latency Control */
+#define PIIX4_FUNC0_DLC                         0x82
+#define   PIIX4_FUNC0_DLC_USBPR_EN                      (1 << 2)
+#define   PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN            (1 << 1)
+#define   PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN        (1 << 0)
+
+/* IDE Timing */
+#define PIIX4_FUNC1_IDETIM_PRIMARY_LO           0x40
+#define PIIX4_FUNC1_IDETIM_PRIMARY_HI           0x41
+#define   PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN   (1 << 7)
+#define PIIX4_FUNC1_IDETIM_SECONDARY_LO         0x42
+#define PIIX4_FUNC1_IDETIM_SECONDARY_HI         0x43
+#define   PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
+
 /************************************************************************
  *  IO register offsets
  ************************************************************************/