diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2013-09-25 12:21:26 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-10-29 16:25:24 -0400 |
commit | 14bd8c082016cd1f67fdfd702e4cf6367869a712 (patch) | |
tree | b4d517e79c58fd3c665286b39ddb1801890f2cb0 /arch/mips/include/asm/cacheops.h | |
parent | 7b784c634b4147345b46251884be6be4bd45fd43 (diff) |
MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.
It was ugly.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cacheops.h')
-rw-r--r-- | arch/mips/include/asm/cacheops.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 0644c985d153..c75025f27c20 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h | |||
@@ -20,11 +20,7 @@ | |||
20 | #define Index_Load_Tag_D 0x05 | 20 | #define Index_Load_Tag_D 0x05 |
21 | #define Index_Store_Tag_I 0x08 | 21 | #define Index_Store_Tag_I 0x08 |
22 | #define Index_Store_Tag_D 0x09 | 22 | #define Index_Store_Tag_D 0x09 |
23 | #if defined(CONFIG_CPU_LOONGSON2) | ||
24 | #define Hit_Invalidate_I 0x00 | ||
25 | #else | ||
26 | #define Hit_Invalidate_I 0x10 | 23 | #define Hit_Invalidate_I 0x10 |
27 | #endif | ||
28 | #define Hit_Invalidate_D 0x11 | 24 | #define Hit_Invalidate_D 0x11 |
29 | #define Hit_Writeback_Inv_D 0x15 | 25 | #define Hit_Writeback_Inv_D 0x15 |
30 | 26 | ||
@@ -84,4 +80,9 @@ | |||
84 | #define Index_Store_Data_D 0x1d | 80 | #define Index_Store_Data_D 0x1d |
85 | #define Index_Store_Data_S 0x1f | 81 | #define Index_Store_Data_S 0x1f |
86 | 82 | ||
83 | /* | ||
84 | * Loongson2-specific cacheops | ||
85 | */ | ||
86 | #define Hit_Invalidate_I_Loongson23 0x00 | ||
87 | |||
87 | #endif /* __ASM_CACHEOPS_H */ | 88 | #endif /* __ASM_CACHEOPS_H */ |