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authorRalf Baechle <ralf@linux-mips.org>2014-03-30 07:20:10 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-03-31 12:17:12 -0400
commita809d46066d5171ed446d59a51cd1e57d99fcfc3 (patch)
treeede5e0f23d1577da4685034894f66f1de2529937 /arch/mips/alchemy
parent30ee615bb86ba640c9ec7f85fb95c1b0e31c41be (diff)
MIPS: Fix gigaton of warning building with microMIPS.
With binutils 2.24 the attempt to switch with microMIPS mode to MIPS III mode through .set mips3 results in *lots* of warnings like {standard input}: Assembler messages: {standard input}:397: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension during a kernel build. Fixed by using .set arch=r4000 instead. This breaks support for building the kernel with binutils 2.13 which was supported for 32 bit kernels only anyway and 2.14 which was a bad vintage for MIPS anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/common/sleeper.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 706d933e0085..c73d81270b42 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -95,7 +95,7 @@ LEAF(alchemy_sleep_au1000)
95 95
96 /* cache following instructions, as memory gets put to sleep */ 96 /* cache following instructions, as memory gets put to sleep */
97 la t0, 1f 97 la t0, 1f
98 .set mips3 98 .set arch=r4000
99 cache 0x14, 0(t0) 99 cache 0x14, 0(t0)
100 cache 0x14, 32(t0) 100 cache 0x14, 32(t0)
101 cache 0x14, 64(t0) 101 cache 0x14, 64(t0)
@@ -121,7 +121,7 @@ LEAF(alchemy_sleep_au1550)
121 121
122 /* cache following instructions, as memory gets put to sleep */ 122 /* cache following instructions, as memory gets put to sleep */
123 la t0, 1f 123 la t0, 1f
124 .set mips3 124 .set arch=r4000
125 cache 0x14, 0(t0) 125 cache 0x14, 0(t0)
126 cache 0x14, 32(t0) 126 cache 0x14, 32(t0)
127 cache 0x14, 64(t0) 127 cache 0x14, 64(t0)
@@ -163,7 +163,7 @@ LEAF(alchemy_sleep_au1300)
163 la t1, 4f 163 la t1, 4f
164 subu t2, t1, t0 164 subu t2, t1, t0
165 165
166 .set mips3 166 .set arch=r4000
167 167
1681: cache 0x14, 0(t0) 1681: cache 0x14, 0(t0)
169 subu t2, t2, 32 169 subu t2, t2, 32