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authorMichael Trimarchi <michael@amarulasolutions.com>2016-01-29 03:01:39 -0500
committerShawn Guo <shawnguo@kernel.org>2016-02-29 03:14:32 -0500
commitcc42603de3200277afca1664358b85d2360ccdd6 (patch)
treeb162d81e2760471566e7bf6c9cc6106f942c0586 /arch/arm
parentf8ea256e6fe9929e38cd0126847a1a98e34d6fbd (diff)
ARM: dts: imx6q-icore-rqs: Add Engicam IMX6 Q7 initial support
www.engicam.com/en/products/embedded/som/standard/i-core-rqs-m6s-dl-d-q Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/imx6q-icore-rqs.dts78
-rw-r--r--arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi411
3 files changed, 490 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a4a6d70e8b26..5d1f978cd3a8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -332,6 +332,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
332 imx6q-gw551x.dtb \ 332 imx6q-gw551x.dtb \
333 imx6q-gw552x.dtb \ 333 imx6q-gw552x.dtb \
334 imx6q-hummingboard.dtb \ 334 imx6q-hummingboard.dtb \
335 imx6q-icore-rqs.dtb \
335 imx6q-nitrogen6x.dtb \ 336 imx6q-nitrogen6x.dtb \
336 imx6q-nitrogen6_max.dtb \ 337 imx6q-nitrogen6_max.dtb \
337 imx6q-novena.dtb \ 338 imx6q-novena.dtb \
diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts
new file mode 100644
index 000000000000..005318865f66
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-icore-rqs.dts
@@ -0,0 +1,78 @@
1/*
2 * Copyright (C) 2015 Amarula Solutions B.V.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43
44#include "imx6q.dtsi"
45#include "imx6qdl-icore-rqs.dtsi"
46
47/ {
48 model = "Engicam i.CoreM6 Quad SOM";
49 compatible = "engicam,imx6-icore-rqs", "fsl,imx6q";
50
51 sound {
52 compatible = "fsl,imx-audio-sgtl5000";
53 model = "imx-audio-sgtl5000";
54 ssi-controller = <&ssi1>;
55 audio-codec = <&codec>;
56 audio-routing =
57 "MIC_IN", "Mic Jack",
58 "Mic Jack", "Mic Bias",
59 "Headphone Jack", "HP_OUT";
60 mux-int-port = <1>;
61 mux-ext-port = <4>;
62 };
63};
64
65&i2c3 {
66 codec: sgtl5000@0a {
67 compatible = "fsl,sgtl5000";
68 reg = <0x0a>;
69 clocks = <&clks IMX6QDL_CLK_CKO>;
70 VDDA-supply = <&reg_2p5v>;
71 VDDIO-supply = <&reg_3p3v>;
72 VDDD-supply = <&reg_1p8v>;
73 };
74};
75
76&sata {
77 status = "okay";
78};
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
new file mode 100644
index 000000000000..f8d945a56525
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -0,0 +1,411 @@
1/*
2 * Copyright (C) 2015 Amarula Solutions B.V.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/clock/imx6qdl-clock.h>
44
45/ {
46 memory {
47 reg = <0x10000000 0x80000000>;
48 };
49
50 reg_1p8v: regulator-1p8v {
51 compatible = "regulator-fixed";
52 regulator-name = "1P8V";
53 regulator-min-microvolt = <1800000>;
54 regulator-max-microvolt = <1800000>;
55 regulator-boot-on;
56 regulator-always-on;
57 };
58
59 reg_2p5v: regulator-2p5v {
60 compatible = "regulator-fixed";
61 regulator-name = "2P5V";
62 regulator-min-microvolt = <2500000>;
63 regulator-max-microvolt = <2500000>;
64 regulator-boot-on;
65 regulator-always-on;
66 };
67
68 reg_3p3v: regulator-3p3v {
69 compatible = "regulator-fixed";
70 regulator-name = "3P3V";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 regulator-boot-on;
74 regulator-always-on;
75 };
76
77 reg_sd3_vmmc: regulator-sd3-vmmc {
78 compatible = "regulator-fixed";
79 regulator-name = "P3V3_SD3_SWITCHED";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
83 enable-active-high;
84 };
85
86 reg_sd4_vmmc: regulator-sd4-vmmc {
87 compatible = "regulator-fixed";
88 regulator-name = "P3V3_SD4_SWITCHED";
89 regulator-min-microvolt = <3300000>;
90 regulator-max-microvolt = <3300000>;
91 regulator-boot-on;
92 regulator-always-on;
93 };
94
95 reg_usb_h1_vbus: regulator-usb-h1-vbus {
96 compatible = "regulator-fixed";
97 regulator-name = "usb_h1_vbus";
98 regulator-min-microvolt = <5000000>;
99 regulator-max-microvolt = <5000000>;
100 regulator-boot-on;
101 regulator-always-on;
102 };
103
104 reg_usb_otg_vbus: regulator-usb-otg-vbus {
105 compatible = "regulator-fixed";
106 regulator-name = "usb_otg_vbus";
107 regulator-min-microvolt = <5000000>;
108 regulator-max-microvolt = <5000000>;
109 regulator-boot-on;
110 regulator-always-on;
111 };
112
113 usb_hub: usb-hub {
114 compatible = "smsc,usb3503a";
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_usbhub>;
117 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
118 clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
119 clock-names = "refclk";
120 };
121};
122
123&clks {
124 assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
125 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
126};
127
128&audmux {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_audmux>;
131 status = "okay";
132};
133
134&fec {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_enet>;
137 phy-handle = <&eth_phy>;
138 phy-mode = "rgmii";
139 status = "okay";
140
141 mdio {
142 eth_phy: ethernet-phy {
143 rxc-skew-ps = <1140>;
144 txc-skew-ps = <1140>;
145 txen-skew-ps = <600>;
146 rxdv-skew-ps = <240>;
147 rxd0-skew-ps = <420>;
148 rxd1-skew-ps = <600>;
149 rxd2-skew-ps = <420>;
150 rxd3-skew-ps = <240>;
151 txd0-skew-ps = <60>;
152 txd1-skew-ps = <60>;
153 txd2-skew-ps = <60>;
154 txd3-skew-ps = <240>;
155 };
156 };
157};
158
159&i2c1 {
160 clock-frequency = <100000>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_i2c1>;
163 status = "okay";
164};
165
166&i2c2 {
167 clock-frequency = <100000>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c2>;
170 status = "okay";
171};
172
173&i2c3 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c3>;
176 status = "okay";
177};
178
179&pcie {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_pcie>;
182 reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
183 status = "okay";
184};
185
186&ssi1 {
187 fsl,mode = "i2s-slave";
188 status = "okay";
189};
190
191&uart4 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_uart4>;
194 status = "okay";
195};
196
197&usbh1 {
198 vbus-supply = <&reg_usb_h1_vbus>;
199 disable-over-current;
200 clocks = <&clks IMX6QDL_CLK_USBOH3>;
201 status = "okay";
202};
203
204&usbotg {
205 vbus-supply = <&reg_usb_otg_vbus>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_usbotg>;
208 disable-over-current;
209 status = "okay";
210};
211
212&usdhc1 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_usdhc1>;
215 no-1-8-v;
216 status = "okay";
217};
218
219&usdhc3 {
220 pinctrl-names = "default", "state_100mhz", "state_200mhz";
221 pinctrl-0 = <&pinctrl_usdhc3>;
222 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
223 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
224 vmcc-supply = <&reg_sd3_vmmc>;
225 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
226 bus-witdh=<4>;
227 no-1-8-v;
228 status = "okay";
229};
230
231&usdhc4 {
232 pinctrl-names = "default", "state_100mhz", "state_200mhz";
233 pinctrl-0 = <&pinctrl_usdhc4>;
234 pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
235 pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
236 vmcc-supply = <&reg_sd4_vmmc>;
237 bus-witdh=<8>;
238 no-1-8-v;
239 non-removable;
240 status = "okay";
241};
242
243&iomuxc {
244 pinctrl_audmux: audmux {
245 fsl,pins = <
246 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
247 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
248 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
249 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
250 >;
251 };
252
253 pinctrl_enet: enetgrp {
254 fsl,pins = <
255 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
256 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
257 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
258 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
259 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
260 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
261 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
262 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
263 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
264 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
265 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
266 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
267 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
268 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
269 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
270 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
271 >;
272 };
273
274 pinctrl_i2c1: i2c1grp {
275 fsl,pins = <
276 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
277 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
278 >;
279 };
280
281 pinctrl_i2c2: i2c2grp {
282 fsl,pins = <
283 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
284 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
285 >;
286 };
287
288 pinctrl_i2c3: i2c3grp {
289 fsl,pins = <
290 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
291 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
292 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
293 >;
294 };
295
296 pinctrl_pcie: pciegrp {
297 fsl,pins = <
298 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */
299 >;
300 };
301
302 pinctrl_uart4: uart4grp {
303 fsl,pins = <
304 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
305 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
306 >;
307 };
308
309 pinctrl_usbhub: usbhubgrp {
310 fsl,pins = <
311 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */
312 >;
313 };
314
315 pinctrl_usbotg: usbotggrp {
316 fsl,pins = <
317 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
318 >;
319 };
320
321 pinctrl_usdhc1: usdhc1grp {
322 fsl,pins = <
323 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
324 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
325 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
326 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
327 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
328 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
329 >;
330 };
331
332 pinctrl_usdhc3: usdhc3grp {
333 fsl,pins = <
334 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
335 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
336 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
337 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
338 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
339 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
340 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */
341 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */
342 >;
343 };
344
345 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
346 fsl,pins = <
347 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1
348 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1
349 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1
350 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1
351 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1
352 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1
353 >;
354 };
355
356 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
357 fsl,pins = <
358 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
359 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
360 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
361 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
362 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
363 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
364 >;
365 };
366
367 pinctrl_usdhc4: usdhc4grp {
368 fsl,pins = <
369 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070
370 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070
371 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
372 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
373 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
374 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
375 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
376 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
377 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
378 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
379 >;
380 };
381
382 pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
383 fsl,pins = <
384 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1
385 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1
386 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
387 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
388 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
389 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
390 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
391 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
392 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
393 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
394 >;
395 };
396
397 pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
398 fsl,pins = <
399 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9
400 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9
401 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
402 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
403 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
404 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
405 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
406 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
407 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
408 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
409 >;
410 };
411};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 18:35:33 -0500