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authorSrinivas Kandagatla <srinivas.kandagatla@st.com>2014-01-29 11:19:44 -0500
committerSrinivas Kandagatla <srinivas.kandagatla@st.com>2014-03-11 06:04:00 -0400
commitc80fe3357fc13a4b5ecbb89a07d53c60f9df4b0a (patch)
tree35c2c5486b81f642450d0534c99dc2a2b66ffd41 /arch/arm
parentbef40df89ff55b1d0cb6881bc0a974c0971432dd (diff)
ARM: STi: STiH415: Add ethernet support.
This patch adds support to STiH415 SOC, which has two ethernet snps,dwmac controllers version 3.610. With this patch B2000 and B2020 boards can boot with ethernet in MII and RGMII modes. Tested on both B2020 and B2000. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/stih415-clock.dtsi14
-rw-r--r--arch/arm/boot/dts/stih415-pinctrl.dtsi121
-rw-r--r--arch/arm/boot/dts/stih415.dtsi48
-rw-r--r--arch/arm/boot/dts/stih41x-b2000.dtsi22
-rw-r--r--arch/arm/boot/dts/stih41x-b2020.dtsi13
5 files changed, 218 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index 174c799df741..d047dbc28d61 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -34,5 +34,19 @@
34 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
35 clock-frequency = <100000000>; 35 clock-frequency = <100000000>;
36 }; 36 };
37
38 CLKS_GMAC0_PHY: clockgenA1@7 {
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <25000000>;
42 clock-output-names = "CLKS_GMAC0_PHY";
43 };
44
45 CLKS_ETH1_PHY: clockgenA0@7 {
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <25000000>;
49 clock-output-names = "CLKS_ETH1_PHY";
50 };
37 }; 51 };
38}; 52};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 887c5e59c73e..9ca20aafba24 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -119,6 +119,56 @@
119 }; 119 };
120 }; 120 };
121 }; 121 };
122
123 gmac1 {
124 pinctrl_mii1: mii1 {
125 st,pins {
126 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
127 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
128 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
129 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
130 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
131 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
132 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
133 col = <&PIO0 7 ALT1 IN BYPASS 1000>;
134 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
135 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
136 crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
137 mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
138 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
139 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
140 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
141 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
142 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
143 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
144 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
145 phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
146 };
147 };
148
149 pinctrl_rgmii1: rgmii1-0 {
150 st,pins {
151 txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
152 txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
153 txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
154 txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
155 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
156 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
157 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
158 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
159 rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
160 rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
161 rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
162 rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
163
164 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
165 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
166 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
167
168 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
169 };
170 };
171 };
122 }; 172 };
123 173
124 pin-controller-front { 174 pin-controller-front {
@@ -284,6 +334,77 @@
284 }; 334 };
285 }; 335 };
286 }; 336 };
337
338 gmac0{
339 pinctrl_mii0: mii0 {
340 st,pins {
341 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
342 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
343
344 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
345 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
346 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
347 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
348
349 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
350 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
351 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
352 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
353 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
354 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
355
356 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
357 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
358 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
359 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
360 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
361 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
362 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
363 phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
364
365 };
366 };
367
368 pinctrl_gmii0: gmii0 {
369 st,pins {
370 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
371 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
372 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
373 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
374
375 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
376 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
377 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
378 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
379 txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
380 txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
381 txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
382 txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
383
384 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
385 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
386 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
387 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
388 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
389 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
390
391 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
392 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
393 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
394 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
395 rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
396 rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
397 rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
398 rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
399
400 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
401 clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
402 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
403
404
405 };
406 };
407 };
287 }; 408 };
288 409
289 pin-controller-left { 410 pin-controller-left {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d52207c1168e..cc9b22bc7472 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -147,5 +147,53 @@
147 147
148 status = "disabled"; 148 status = "disabled";
149 }; 149 };
150
151 ethernet0: dwmac@fe810000 {
152 device_type = "network";
153 compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
154 status = "disabled";
155
156 reg = <0xfe810000 0x8000>, <0x148 0x4>;
157 reg-names = "stmmaceth", "sti-ethconf";
158
159 interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
160 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
161 resets = <&softreset STIH415_ETH0_SOFTRESET>;
162 reset-names = "stmmaceth";
163
164 snps,pbl = <32>;
165 snps,mixed-burst;
166 snps,force_sf_dma_mode;
167
168 st,syscon = <&syscfg_rear>;
169
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_mii0>;
172 clock-names = "stmmaceth";
173 clocks = <&CLKS_GMAC0_PHY>;
174 };
175
176 ethernet1: dwmac@fef08000 {
177 device_type = "network";
178 compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
179 status = "disabled";
180 reg = <0xfef08000 0x8000>, <0x74 0x4>;
181 reg-names = "stmmaceth", "sti-ethconf";
182 interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
183 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
184
185 snps,pbl = <32>;
186 snps,mixed-burst;
187 snps,force_sf_dma_mode;
188
189 st,syscon = <&syscfg_sbc>;
190
191 resets = <&softreset STIH415_ETH1_SOFTRESET>;
192 reset-names = "stmmaceth";
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_mii1>;
195 clock-names = "stmmaceth";
196 clocks = <&CLKS_ETH1_PHY>;
197 };
150 }; 198 };
151}; 199};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 1e6aa92772f5..bf65c49095af 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -20,6 +20,8 @@
20 20
21 aliases { 21 aliases {
22 ttyAS0 = &serial2; 22 ttyAS0 = &serial2;
23 ethernet0 = &ethernet0;
24 ethernet1 = &ethernet1;
23 }; 25 };
24 26
25 soc { 27 soc {
@@ -46,5 +48,25 @@
46 48
47 status = "okay"; 49 status = "okay";
48 }; 50 };
51
52 ethernet0: dwmac@fe810000 {
53 status = "okay";
54 phy-mode = "mii";
55 pinctrl-0 = <&pinctrl_mii0>;
56
57 snps,reset-gpio = <&PIO106 2>;
58 snps,reset-active-low;
59 snps,reset-delays-us = <0 10000 10000>;
60 };
61
62 ethernet1: dwmac@fef08000 {
63 status = "disabled";
64 phy-mode = "mii";
65 st,tx-retime-src = "txclk";
66
67 snps,reset-gpio = <&PIO4 7>;
68 snps,reset-active-low;
69 snps,reset-delays-us = <0 10000 10000>;
70 };
49 }; 71 };
50}; 72};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 0ef0a69df8ea..3dc74c25a57b 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -19,6 +19,7 @@
19 19
20 aliases { 20 aliases {
21 ttyAS0 = &sbc_serial1; 21 ttyAS0 = &sbc_serial1;
22 ethernet1 = &ethernet1;
22 }; 23 };
23 soc { 24 soc {
24 sbc_serial1: serial@fe531000 { 25 sbc_serial1: serial@fe531000 {
@@ -60,5 +61,17 @@
60 i2c@fe541000 { 61 i2c@fe541000 {
61 status = "okay"; 62 status = "okay";
62 }; 63 };
64
65 ethernet1: dwmac@fef08000 {
66 status = "okay";
67 phy-mode = "rgmii-id";
68 max-speed = <1000>;
69 st,tx-retime-src = "clk_125";
70 snps,reset-gpio = <&PIO3 0>;
71 snps,reset-active-low;
72 snps,reset-delays-us = <0 10000 10000>;
73
74 pinctrl-0 = <&pinctrl_rgmii1>;
75 };
63 }; 76 };
64}; 77};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 18:51:49 -0500