aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorTony Lindgren <tony@atomide.com>2010-12-21 19:53:00 -0500
committerTony Lindgren <tony@atomide.com>2010-12-21 19:53:00 -0500
commitbb3613aa34a81a5e2f1227ccdb801fde04a7da10 (patch)
treebb79c15d5da41113bd7b83d9e74fbfc4a1bf8569 /arch/arm
parent6971071cdda79cad5f53ba390e466d696e7e9006 (diff)
parentbb1c9034b3ce7f29d3d178a87b42b767611d6574 (diff)
Merge branch 'pm-next' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-linus
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-at91/Makefile2
-rw-r--r--arch/arm/mach-at91/board-pcontrol-g20.c98
-rw-r--r--arch/arm/mach-at91/board-stamp9g20.c82
-rw-r--r--arch/arm/mach-at91/clock.c2
-rw-r--r--arch/arm/mach-at91/include/mach/stamp9g20.h7
-rw-r--r--arch/arm/mach-omap2/control.c22
-rw-r--r--arch/arm/mach-omap2/control.h9
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c36
-rw-r--r--arch/arm/mach-omap2/pm.c2
-rw-r--r--arch/arm/mach-omap2/pm.h15
-rw-r--r--arch/arm/mach-omap2/pm24xx.c16
-rw-r--r--arch/arm/mach-omap2/pm34xx.c66
-rw-r--r--arch/arm/mach-omap2/pm44xx.c16
-rw-r--r--arch/arm/mach-omap2/sdrc.h1
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S832
-rw-r--r--arch/arm/mach-s3c2412/Kconfig7
-rw-r--r--arch/arm/mach-s3c2412/Makefile3
-rw-r--r--arch/arm/mach-s3c2416/Kconfig1
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c6
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c6
-rw-r--r--arch/arm/mach-shmobile/include/mach/entry-macro.S30
-rw-r--r--arch/arm/mach-shmobile/include/mach/vmalloc.h2
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h11
-rw-r--r--arch/arm/plat-omap/sram.c7
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig2
25 files changed, 702 insertions, 579 deletions
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 62d686f0b426..d13add71f72a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
65obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o 65obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
66obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o 66obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o 67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
68obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o 68obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
69 69
70# AT91SAM9260/AT91SAM9G20 board-specific support 70# AT91SAM9260/AT91SAM9G20 board-specific support
71obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o 71obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index bba5a560e02b..feb65787c30b 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -31,6 +31,7 @@
31 31
32#include <mach/board.h> 32#include <mach/board.h>
33#include <mach/at91sam9_smc.h> 33#include <mach/at91sam9_smc.h>
34#include <mach/stamp9g20.h>
34 35
35#include "sam9_smc.h" 36#include "sam9_smc.h"
36#include "generic.h" 37#include "generic.h"
@@ -38,11 +39,7 @@
38 39
39static void __init pcontrol_g20_map_io(void) 40static void __init pcontrol_g20_map_io(void)
40{ 41{
41 /* Initialize processor: 18.432 MHz crystal */ 42 stamp9g20_map_io();
42 at91sam9260_initialize(18432000);
43
44 /* DGBU on ttyS0. (Rx, Tx) only TTL -> JTAG connector X7 17,19 ) */
45 at91_register_uart(0, 0, 0);
46 43
47 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ 44 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */
48 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS 45 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
@@ -54,9 +51,6 @@ static void __init pcontrol_g20_map_io(void)
54 51
55 /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ 52 /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */
56 at91_register_uart(AT91SAM9260_ID_US4, 3, 0); 53 at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
57
58 /* set serial console to ttyS0 (ie, DBGU) */
59 at91_set_serial_console(0);
60} 54}
61 55
62 56
@@ -66,38 +60,6 @@ static void __init init_irq(void)
66} 60}
67 61
68 62
69/*
70 * NAND flash 512MiB 1,8V 8-bit, sector size 128 KiB
71 */
72static struct atmel_nand_data __initdata nand_data = {
73 .ale = 21,
74 .cle = 22,
75 .rdy_pin = AT91_PIN_PC13,
76 .enable_pin = AT91_PIN_PC14,
77};
78
79/*
80 * Bus timings; unit = 7.57ns
81 */
82static struct sam9_smc_config __initdata nand_smc_config = {
83 .ncs_read_setup = 0,
84 .nrd_setup = 2,
85 .ncs_write_setup = 0,
86 .nwe_setup = 2,
87
88 .ncs_read_pulse = 4,
89 .nrd_pulse = 4,
90 .ncs_write_pulse = 4,
91 .nwe_pulse = 4,
92
93 .read_cycle = 7,
94 .write_cycle = 7,
95
96 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
97 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
98 .tdf_cycles = 3,
99};
100
101static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { { 63static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
102 .ncs_read_setup = 16, 64 .ncs_read_setup = 16,
103 .nrd_setup = 18, 65 .nrd_setup = 18,
@@ -138,14 +100,6 @@ static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
138 .tdf_cycles = 1, 100 .tdf_cycles = 1,
139} }; 101} };
140 102
141static void __init add_device_nand(void)
142{
143 /* configure chip-select 3 (NAND) */
144 sam9_smc_configure(3, &nand_smc_config);
145 at91_add_device_nand(&nand_data);
146}
147
148
149static void __init add_device_pcontrol(void) 103static void __init add_device_pcontrol(void)
150{ 104{
151 /* configure chip-select 4 (IO compatible to 8051 X4 ) */ 105 /* configure chip-select 4 (IO compatible to 8051 X4 ) */
@@ -156,23 +110,6 @@ static void __init add_device_pcontrol(void)
156 110
157 111
158/* 112/*
159 * MCI (SD/MMC)
160 * det_pin, wp_pin and vcc_pin are not connected
161 */
162#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
163static struct mci_platform_data __initdata mmc_data = {
164 .slot[0] = {
165 .bus_width = 4,
166 },
167};
168#else
169static struct at91_mmc_data __initdata mmc_data = {
170 .wire4 = 1,
171};
172#endif
173
174
175/*
176 * USB Host port 113 * USB Host port
177 */ 114 */
178static struct at91_usbh_data __initdata usbh_data = { 115static struct at91_usbh_data __initdata usbh_data = {
@@ -265,42 +202,13 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = {
265}; 202};
266 203
267 204
268/*
269 * Dallas 1-Wire DS2431
270 */
271static struct w1_gpio_platform_data w1_gpio_pdata = {
272 .pin = AT91_PIN_PA29,
273 .is_open_drain = 1,
274};
275
276static struct platform_device w1_device = {
277 .name = "w1-gpio",
278 .id = -1,
279 .dev.platform_data = &w1_gpio_pdata,
280};
281
282static void add_wire1(void)
283{
284 at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
285 at91_set_multi_drive(w1_gpio_pdata.pin, 1);
286 platform_device_register(&w1_device);
287}
288
289
290static void __init pcontrol_g20_board_init(void) 205static void __init pcontrol_g20_board_init(void)
291{ 206{
292 at91_add_device_serial(); 207 stamp9g20_board_init();
293 add_device_nand();
294#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
295 at91_add_device_mci(0, &mmc_data);
296#else
297 at91_add_device_mmc(0, &mmc_data);
298#endif
299 at91_add_device_usbh(&usbh_data); 208 at91_add_device_usbh(&usbh_data);
300 at91_add_device_eth(&macb_data); 209 at91_add_device_eth(&macb_data);
301 at91_add_device_i2c(pcontrol_g20_i2c_devices, 210 at91_add_device_i2c(pcontrol_g20_i2c_devices,
302 ARRAY_SIZE(pcontrol_g20_i2c_devices)); 211 ARRAY_SIZE(pcontrol_g20_i2c_devices));
303 add_wire1();
304 add_device_pcontrol(); 212 add_device_pcontrol();
305 at91_add_device_spi(pcontrol_g20_spi_devices, 213 at91_add_device_spi(pcontrol_g20_spi_devices,
306 ARRAY_SIZE(pcontrol_g20_spi_devices)); 214 ARRAY_SIZE(pcontrol_g20_spi_devices));
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 5206eef4a67e..f8902b118960 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -32,7 +32,7 @@
32#include "generic.h" 32#include "generic.h"
33 33
34 34
35static void __init portuxg20_map_io(void) 35void __init stamp9g20_map_io(void)
36{ 36{
37 /* Initialize processor: 18.432 MHz crystal */ 37 /* Initialize processor: 18.432 MHz crystal */
38 at91sam9260_initialize(18432000); 38 at91sam9260_initialize(18432000);
@@ -40,6 +40,24 @@ static void __init portuxg20_map_io(void)
40 /* DGBU on ttyS0. (Rx & Tx only) */ 40 /* DGBU on ttyS0. (Rx & Tx only) */
41 at91_register_uart(0, 0, 0); 41 at91_register_uart(0, 0, 0);
42 42
43 /* set serial console to ttyS0 (ie, DBGU) */
44 at91_set_serial_console(0);
45}
46
47static void __init stamp9g20evb_map_io(void)
48{
49 stamp9g20_map_io();
50
51 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
52 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
53 | ATMEL_UART_DTR | ATMEL_UART_DSR
54 | ATMEL_UART_DCD | ATMEL_UART_RI);
55}
56
57static void __init portuxg20_map_io(void)
58{
59 stamp9g20_map_io();
60
43 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ 61 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
44 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS 62 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
45 | ATMEL_UART_DTR | ATMEL_UART_DSR 63 | ATMEL_UART_DTR | ATMEL_UART_DSR
@@ -56,26 +74,6 @@ static void __init portuxg20_map_io(void)
56 74
57 /* USART5 on ttyS6. (Rx, Tx only) */ 75 /* USART5 on ttyS6. (Rx, Tx only) */
58 at91_register_uart(AT91SAM9260_ID_US5, 6, 0); 76 at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
59
60 /* set serial console to ttyS0 (ie, DBGU) */
61 at91_set_serial_console(0);
62}
63
64static void __init stamp9g20_map_io(void)
65{
66 /* Initialize processor: 18.432 MHz crystal */
67 at91sam9260_initialize(18432000);
68
69 /* DGBU on ttyS0. (Rx & Tx only) */
70 at91_register_uart(0, 0, 0);
71
72 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
73 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
74 | ATMEL_UART_DTR | ATMEL_UART_DSR
75 | ATMEL_UART_DCD | ATMEL_UART_RI);
76
77 /* set serial console to ttyS0 (ie, DBGU) */
78 at91_set_serial_console(0);
79} 77}
80 78
81static void __init init_irq(void) 79static void __init init_irq(void)
@@ -156,7 +154,7 @@ static struct at91_udc_data __initdata portuxg20_udc_data = {
156 .pullup_pin = 0, /* pull-up driven by UDC */ 154 .pullup_pin = 0, /* pull-up driven by UDC */
157}; 155};
158 156
159static struct at91_udc_data __initdata stamp9g20_udc_data = { 157static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
160 .vbus_pin = AT91_PIN_PA22, 158 .vbus_pin = AT91_PIN_PA22,
161 .pullup_pin = 0, /* pull-up driven by UDC */ 159 .pullup_pin = 0, /* pull-up driven by UDC */
162}; 160};
@@ -190,7 +188,7 @@ static struct gpio_led portuxg20_leds[] = {
190 } 188 }
191}; 189};
192 190
193static struct gpio_led stamp9g20_leds[] = { 191static struct gpio_led stamp9g20evb_leds[] = {
194 { 192 {
195 .name = "D8", 193 .name = "D8",
196 .gpio = AT91_PIN_PB18, 194 .gpio = AT91_PIN_PB18,
@@ -250,7 +248,7 @@ void add_w1(void)
250} 248}
251 249
252 250
253static void __init generic_board_init(void) 251void __init stamp9g20_board_init(void)
254{ 252{
255 /* Serial */ 253 /* Serial */
256 at91_add_device_serial(); 254 at91_add_device_serial();
@@ -262,34 +260,40 @@ static void __init generic_board_init(void)
262#else 260#else
263 at91_add_device_mmc(0, &mmc_data); 261 at91_add_device_mmc(0, &mmc_data);
264#endif 262#endif
265 /* USB Host */
266 at91_add_device_usbh(&usbh_data);
267 /* Ethernet */
268 at91_add_device_eth(&macb_data);
269 /* I2C */
270 at91_add_device_i2c(NULL, 0);
271 /* W1 */ 263 /* W1 */
272 add_w1(); 264 add_w1();
273} 265}
274 266
275static void __init portuxg20_board_init(void) 267static void __init portuxg20_board_init(void)
276{ 268{
277 generic_board_init(); 269 stamp9g20_board_init();
278 /* SPI */ 270 /* USB Host */
279 at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices)); 271 at91_add_device_usbh(&usbh_data);
280 /* USB Device */ 272 /* USB Device */
281 at91_add_device_udc(&portuxg20_udc_data); 273 at91_add_device_udc(&portuxg20_udc_data);
274 /* Ethernet */
275 at91_add_device_eth(&macb_data);
276 /* I2C */
277 at91_add_device_i2c(NULL, 0);
278 /* SPI */
279 at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
282 /* LEDs */ 280 /* LEDs */
283 at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds)); 281 at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds));
284} 282}
285 283
286static void __init stamp9g20_board_init(void) 284static void __init stamp9g20evb_board_init(void)
287{ 285{
288 generic_board_init(); 286 stamp9g20_board_init();
287 /* USB Host */
288 at91_add_device_usbh(&usbh_data);
289 /* USB Device */ 289 /* USB Device */
290 at91_add_device_udc(&stamp9g20_udc_data); 290 at91_add_device_udc(&stamp9g20evb_udc_data);
291 /* Ethernet */
292 at91_add_device_eth(&macb_data);
293 /* I2C */
294 at91_add_device_i2c(NULL, 0);
291 /* LEDs */ 295 /* LEDs */
292 at91_gpio_leds(stamp9g20_leds, ARRAY_SIZE(stamp9g20_leds)); 296 at91_gpio_leds(stamp9g20evb_leds, ARRAY_SIZE(stamp9g20evb_leds));
293} 297}
294 298
295MACHINE_START(PORTUXG20, "taskit PortuxG20") 299MACHINE_START(PORTUXG20, "taskit PortuxG20")
@@ -305,7 +309,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
305 /* Maintainer: taskit GmbH */ 309 /* Maintainer: taskit GmbH */
306 .boot_params = AT91_SDRAM_BASE + 0x100, 310 .boot_params = AT91_SDRAM_BASE + 0x100,
307 .timer = &at91sam926x_timer, 311 .timer = &at91sam926x_timer,
308 .map_io = stamp9g20_map_io, 312 .map_io = stamp9g20evb_map_io,
309 .init_irq = init_irq, 313 .init_irq = init_irq,
310 .init_machine = stamp9g20_board_init, 314 .init_machine = stamp9g20evb_board_init,
311MACHINE_END 315MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 7525cee3983f..9113da6845f1 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -658,7 +658,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
658 /* Now set uhpck values */ 658 /* Now set uhpck values */
659 uhpck.parent = &utmi_clk; 659 uhpck.parent = &utmi_clk;
660 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 660 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
661 uhpck.rate_hz = utmi_clk.parent->rate_hz; 661 uhpck.rate_hz = utmi_clk.rate_hz;
662 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); 662 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
663} 663}
664 664
diff --git a/arch/arm/mach-at91/include/mach/stamp9g20.h b/arch/arm/mach-at91/include/mach/stamp9g20.h
new file mode 100644
index 000000000000..6120f9c46d59
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/stamp9g20.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_STAMP9G20_H
2#define __MACH_STAMP9G20_H
3
4void stamp9g20_map_io(void);
5void stamp9g20_board_init(void);
6
7#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1fa3294b6048..0269bb055b69 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -239,9 +239,19 @@ void omap3_save_scratchpad_contents(void)
239 struct omap3_scratchpad_prcm_block prcm_block_contents; 239 struct omap3_scratchpad_prcm_block prcm_block_contents;
240 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 240 struct omap3_scratchpad_sdrc_block sdrc_block_contents;
241 241
242 /* Populate the Scratchpad contents */ 242 /*
243 * Populate the Scratchpad contents
244 *
245 * The "get_*restore_pointer" functions are used to provide a
246 * physical restore address where the ROM code jumps while waking
247 * up from MPU OFF/OSWR state.
248 * The restore pointer is stored into the scratchpad.
249 */
243 scratchpad_contents.boot_config_ptr = 0x0; 250 scratchpad_contents.boot_config_ptr = 0x0;
244 if (omap_rev() != OMAP3430_REV_ES3_0 && 251 if (cpu_is_omap3630())
252 scratchpad_contents.public_restore_ptr =
253 virt_to_phys(get_omap3630_restore_pointer());
254 else if (omap_rev() != OMAP3430_REV_ES3_0 &&
245 omap_rev() != OMAP3430_REV_ES3_1) 255 omap_rev() != OMAP3430_REV_ES3_1)
246 scratchpad_contents.public_restore_ptr = 256 scratchpad_contents.public_restore_ptr =
247 virt_to_phys(get_restore_pointer()); 257 virt_to_phys(get_restore_pointer());
@@ -474,4 +484,12 @@ void omap3_control_restore_context(void)
474 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 484 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
475 return; 485 return;
476} 486}
487
488void omap3630_ctrl_disable_rta(void)
489{
490 if (!cpu_is_omap3630())
491 return;
492 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
493}
494
477#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 495#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b6c6b7c450b3..6e5f7e512ff7 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -204,6 +204,10 @@
204#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) 204#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
205#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) 205#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
206 206
207/* 36xx-only RTA - Retention till Accesss control registers and bits */
208#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
209#define OMAP36XX_RTA_DISABLE 0x0
210
207/* 34xx D2D idle-related pins, handled by PM core */ 211/* 34xx D2D idle-related pins, handled by PM core */
208#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 212#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
209#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 213#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
@@ -270,6 +274,8 @@
270#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) 274#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
271#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) 275#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
272#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C 276#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
277#define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\
278 OMAP343X_SCRATCHPAD + reg)
273 279
274/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ 280/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
275#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 281#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
@@ -347,10 +353,11 @@ extern void omap3_save_scratchpad_contents(void);
347extern void omap3_clear_scratchpad_contents(void); 353extern void omap3_clear_scratchpad_contents(void);
348extern u32 *get_restore_pointer(void); 354extern u32 *get_restore_pointer(void);
349extern u32 *get_es3_restore_pointer(void); 355extern u32 *get_es3_restore_pointer(void);
356extern u32 *get_omap3630_restore_pointer(void);
350extern u32 omap3_arm_context[128]; 357extern u32 omap3_arm_context[128];
351extern void omap3_control_save_context(void); 358extern void omap3_control_save_context(void);
352extern void omap3_control_restore_context(void); 359extern void omap3_control_restore_context(void);
353 360extern void omap3630_ctrl_disable_rta(void);
354#else 361#else
355#define omap_ctrl_base_get() 0 362#define omap_ctrl_base_get() 0
356#define omap_ctrl_readb(x) 0 363#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 0d50b45d041c..0fb619c52588 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -293,25 +293,26 @@ select_state:
293DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); 293DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
294 294
295/** 295/**
296 * omap3_cpuidle_update_states - Update the cpuidle states. 296 * omap3_cpuidle_update_states() - Update the cpuidle states
297 * @mpu_deepest_state: Enable states upto and including this for mpu domain
298 * @core_deepest_state: Enable states upto and including this for core domain
297 * 299 *
298 * Currently, this function toggles the validity of idle states based upon 300 * This goes through the list of states available and enables and disables the
299 * the flag 'enable_off_mode'. When the flag is set all states are valid. 301 * validity of C states based on deepest state that can be achieved for the
300 * Else, states leading to OFF state set to be invalid. 302 * variable domain
301 */ 303 */
302void omap3_cpuidle_update_states(void) 304void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
303{ 305{
304 int i; 306 int i;
305 307
306 for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { 308 for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
307 struct omap3_processor_cx *cx = &omap3_power_states[i]; 309 struct omap3_processor_cx *cx = &omap3_power_states[i];
308 310
309 if (enable_off_mode) { 311 if ((cx->mpu_state >= mpu_deepest_state) &&
312 (cx->core_state >= core_deepest_state)) {
310 cx->valid = 1; 313 cx->valid = 1;
311 } else { 314 } else {
312 if ((cx->mpu_state == PWRDM_POWER_OFF) || 315 cx->valid = 0;
313 (cx->core_state == PWRDM_POWER_OFF))
314 cx->valid = 0;
315 } 316 }
316 } 317 }
317} 318}
@@ -452,6 +453,18 @@ void omap_init_power_states(void)
452 omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; 453 omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
453 omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | 454 omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
454 CPUIDLE_FLAG_CHECK_BM; 455 CPUIDLE_FLAG_CHECK_BM;
456
457 /*
458 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
459 * enable OFF mode in a stable form for previous revisions.
460 * we disable C7 state as a result.
461 */
462 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
463 omap3_power_states[OMAP3_STATE_C7].valid = 0;
464 cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
465 WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n",
466 __func__);
467 }
455} 468}
456 469
457struct cpuidle_driver omap3_idle_driver = { 470struct cpuidle_driver omap3_idle_driver = {
@@ -504,7 +517,10 @@ int __init omap3_idle_init(void)
504 return -EINVAL; 517 return -EINVAL;
505 dev->state_count = count; 518 dev->state_count = count;
506 519
507 omap3_cpuidle_update_states(); 520 if (enable_off_mode)
521 omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
522 else
523 omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
508 524
509 if (cpuidle_register_device(dev)) { 525 if (cpuidle_register_device(dev)) {
510 printk(KERN_ERR "%s: CPUidle register device failed\n", 526 printk(KERN_ERR "%s: CPUidle register device failed\n",
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 59ca03b0e691..6ec2ee12272a 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -143,5 +143,5 @@ static int __init omap2_common_pm_init(void)
143 143
144 return 0; 144 return 0;
145} 145}
146device_initcall(omap2_common_pm_init); 146postcore_initcall(omap2_common_pm_init);
147 147
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0d75bfd1fdbe..c04f7b50e26f 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -58,7 +58,7 @@ extern u32 sleep_while_idle;
58#endif 58#endif
59 59
60#if defined(CONFIG_CPU_IDLE) 60#if defined(CONFIG_CPU_IDLE)
61extern void omap3_cpuidle_update_states(void); 61extern void omap3_cpuidle_update_states(u32, u32);
62#endif 62#endif
63 63
64#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) 64#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
@@ -80,9 +80,20 @@ extern void save_secure_ram_context(u32 *addr);
80extern void omap3_save_scratchpad_contents(void); 80extern void omap3_save_scratchpad_contents(void);
81 81
82extern unsigned int omap24xx_idle_loop_suspend_sz; 82extern unsigned int omap24xx_idle_loop_suspend_sz;
83extern unsigned int omap34xx_suspend_sz;
84extern unsigned int save_secure_ram_context_sz; 83extern unsigned int save_secure_ram_context_sz;
85extern unsigned int omap24xx_cpu_suspend_sz; 84extern unsigned int omap24xx_cpu_suspend_sz;
86extern unsigned int omap34xx_cpu_suspend_sz; 85extern unsigned int omap34xx_cpu_suspend_sz;
87 86
87#define PM_RTA_ERRATUM_i608 (1 << 0)
88#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
89
90#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
91extern u16 pm34xx_errata;
92#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
93extern void enable_omap3630_toggle_l2_on_restore(void);
94#else
95#define IS_PM34XX_ERRATUM(id) 0
96static inline void enable_omap3630_toggle_l2_on_restore(void) { }
97#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
98
88#endif 99#endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index aaeea49b9bdd..aea7ced9a2ff 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -301,14 +301,8 @@ out:
301 301
302static int omap2_pm_begin(suspend_state_t state) 302static int omap2_pm_begin(suspend_state_t state)
303{ 303{
304 suspend_state = state;
305 return 0;
306}
307
308static int omap2_pm_prepare(void)
309{
310 /* We cannot sleep in idle until we have resumed */
311 disable_hlt(); 304 disable_hlt();
305 suspend_state = state;
312 return 0; 306 return 0;
313} 307}
314 308
@@ -349,21 +343,15 @@ static int omap2_pm_enter(suspend_state_t state)
349 return ret; 343 return ret;
350} 344}
351 345
352static void omap2_pm_finish(void)
353{
354 enable_hlt();
355}
356
357static void omap2_pm_end(void) 346static void omap2_pm_end(void)
358{ 347{
359 suspend_state = PM_SUSPEND_ON; 348 suspend_state = PM_SUSPEND_ON;
349 enable_hlt();
360} 350}
361 351
362static struct platform_suspend_ops omap_pm_ops = { 352static struct platform_suspend_ops omap_pm_ops = {
363 .begin = omap2_pm_begin, 353 .begin = omap2_pm_begin,
364 .prepare = omap2_pm_prepare,
365 .enter = omap2_pm_enter, 354 .enter = omap2_pm_enter,
366 .finish = omap2_pm_finish,
367 .end = omap2_pm_end, 355 .end = omap2_pm_end,
368 .valid = suspend_valid_only_mem, 356 .valid = suspend_valid_only_mem,
369}; 357};
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 648b8c50d024..c45b4fa1deeb 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -68,6 +68,9 @@ static inline bool is_suspending(void)
68#define OMAP343X_TABLE_VALUE_OFFSET 0xc0 68#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
69#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 69#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
70 70
71/* pm34xx errata defined in pm.h */
72u16 pm34xx_errata;
73
71struct power_state { 74struct power_state {
72 struct powerdomain *pwrdm; 75 struct powerdomain *pwrdm;
73 u32 next_state; 76 u32 next_state;
@@ -143,7 +146,7 @@ static void omap3_core_save_context(void)
143 146
144 /* 147 /*
145 * Force write last pad into memory, as this can fail in some 148 * Force write last pad into memory, as this can fail in some
146 * cases according to erratas 1.157, 1.185 149 * cases according to errata 1.157, 1.185
147 */ 150 */
148 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 151 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
149 OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 152 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
@@ -430,7 +433,7 @@ void omap_sram_idle(void)
430 /* 433 /*
431 * On EMU/HS devices ROM code restores a SRDC value 434 * On EMU/HS devices ROM code restores a SRDC value
432 * from scratchpad which has automatic self refresh on timeout 435 * from scratchpad which has automatic self refresh on timeout
433 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. 436 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
434 * Hence store/restore the SDRC_POWER register here. 437 * Hence store/restore the SDRC_POWER register here.
435 */ 438 */
436 if (omap_rev() >= OMAP3430_REV_ES3_0 && 439 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
@@ -529,12 +532,6 @@ out:
529} 532}
530 533
531#ifdef CONFIG_SUSPEND 534#ifdef CONFIG_SUSPEND
532static int omap3_pm_prepare(void)
533{
534 disable_hlt();
535 return 0;
536}
537
538static int omap3_pm_suspend(void) 535static int omap3_pm_suspend(void)
539{ 536{
540 struct power_state *pwrst; 537 struct power_state *pwrst;
@@ -597,14 +594,10 @@ static int omap3_pm_enter(suspend_state_t unused)
597 return ret; 594 return ret;
598} 595}
599 596
600static void omap3_pm_finish(void)
601{
602 enable_hlt();
603}
604
605/* Hooks to enable / disable UART interrupts during suspend */ 597/* Hooks to enable / disable UART interrupts during suspend */
606static int omap3_pm_begin(suspend_state_t state) 598static int omap3_pm_begin(suspend_state_t state)
607{ 599{
600 disable_hlt();
608 suspend_state = state; 601 suspend_state = state;
609 omap_uart_enable_irqs(0); 602 omap_uart_enable_irqs(0);
610 return 0; 603 return 0;
@@ -614,15 +607,14 @@ static void omap3_pm_end(void)
614{ 607{
615 suspend_state = PM_SUSPEND_ON; 608 suspend_state = PM_SUSPEND_ON;
616 omap_uart_enable_irqs(1); 609 omap_uart_enable_irqs(1);
610 enable_hlt();
617 return; 611 return;
618} 612}
619 613
620static struct platform_suspend_ops omap_pm_ops = { 614static struct platform_suspend_ops omap_pm_ops = {
621 .begin = omap3_pm_begin, 615 .begin = omap3_pm_begin,
622 .end = omap3_pm_end, 616 .end = omap3_pm_end,
623 .prepare = omap3_pm_prepare,
624 .enter = omap3_pm_enter, 617 .enter = omap3_pm_enter,
625 .finish = omap3_pm_finish,
626 .valid = suspend_valid_only_mem, 618 .valid = suspend_valid_only_mem,
627}; 619};
628#endif /* CONFIG_SUSPEND */ 620#endif /* CONFIG_SUSPEND */
@@ -925,12 +917,29 @@ void omap3_pm_off_mode_enable(int enable)
925 state = PWRDM_POWER_RET; 917 state = PWRDM_POWER_RET;
926 918
927#ifdef CONFIG_CPU_IDLE 919#ifdef CONFIG_CPU_IDLE
928 omap3_cpuidle_update_states(); 920 /*
921 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
922 * enable OFF mode in a stable form for previous revisions, restrict
923 * instead to RET
924 */
925 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
926 omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
927 else
928 omap3_cpuidle_update_states(state, state);
929#endif 929#endif
930 930
931 list_for_each_entry(pwrst, &pwrst_list, node) { 931 list_for_each_entry(pwrst, &pwrst_list, node) {
932 pwrst->next_state = state; 932 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
933 omap_set_pwrdm_state(pwrst->pwrdm, state); 933 pwrst->pwrdm == core_pwrdm &&
934 state == PWRDM_POWER_OFF) {
935 pwrst->next_state = PWRDM_POWER_RET;
936 WARN_ONCE(1,
937 "%s: Core OFF disabled due to errata i583\n",
938 __func__);
939 } else {
940 pwrst->next_state = state;
941 }
942 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
934 } 943 }
935} 944}
936 945
@@ -1002,6 +1011,17 @@ void omap_push_sram_idle(void)
1002 save_secure_ram_context_sz); 1011 save_secure_ram_context_sz);
1003} 1012}
1004 1013
1014static void __init pm_errata_configure(void)
1015{
1016 if (cpu_is_omap3630()) {
1017 pm34xx_errata |= PM_RTA_ERRATUM_i608;
1018 /* Enable the l2 cache toggling in sleep logic */
1019 enable_omap3630_toggle_l2_on_restore();
1020 if (omap_rev() < OMAP3630_REV_ES1_2)
1021 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
1022 }
1023}
1024
1005static int __init omap3_pm_init(void) 1025static int __init omap3_pm_init(void)
1006{ 1026{
1007 struct power_state *pwrst, *tmp; 1027 struct power_state *pwrst, *tmp;
@@ -1011,6 +1031,8 @@ static int __init omap3_pm_init(void)
1011 if (!cpu_is_omap34xx()) 1031 if (!cpu_is_omap34xx())
1012 return -ENODEV; 1032 return -ENODEV;
1013 1033
1034 pm_errata_configure();
1035
1014 printk(KERN_ERR "Power Management for TI OMAP3.\n"); 1036 printk(KERN_ERR "Power Management for TI OMAP3.\n");
1015 1037
1016 /* XXX prcm_setup_regs needs to be before enabling hw 1038 /* XXX prcm_setup_regs needs to be before enabling hw
@@ -1058,6 +1080,14 @@ static int __init omap3_pm_init(void)
1058 pm_idle = omap3_pm_idle; 1080 pm_idle = omap3_pm_idle;
1059 omap3_idle_init(); 1081 omap3_idle_init();
1060 1082
1083 /*
1084 * RTA is disabled during initialization as per erratum i608
1085 * it is safer to disable RTA by the bootloader, but we would like
1086 * to be doubly sure here and prevent any mishaps.
1087 */
1088 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
1089 omap3630_ctrl_disable_rta();
1090
1061 clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 1091 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1062 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 1092 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1063 omap3_secure_ram_storage = 1093 omap3_secure_ram_storage =
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 54544b4fc76b..6aff9961e35d 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -31,12 +31,6 @@ struct power_state {
31static LIST_HEAD(pwrst_list); 31static LIST_HEAD(pwrst_list);
32 32
33#ifdef CONFIG_SUSPEND 33#ifdef CONFIG_SUSPEND
34static int omap4_pm_prepare(void)
35{
36 disable_hlt();
37 return 0;
38}
39
40static int omap4_pm_suspend(void) 34static int omap4_pm_suspend(void)
41{ 35{
42 do_wfi(); 36 do_wfi();
@@ -59,28 +53,22 @@ static int omap4_pm_enter(suspend_state_t suspend_state)
59 return ret; 53 return ret;
60} 54}
61 55
62static void omap4_pm_finish(void)
63{
64 enable_hlt();
65 return;
66}
67
68static int omap4_pm_begin(suspend_state_t state) 56static int omap4_pm_begin(suspend_state_t state)
69{ 57{
58 disable_hlt();
70 return 0; 59 return 0;
71} 60}
72 61
73static void omap4_pm_end(void) 62static void omap4_pm_end(void)
74{ 63{
64 enable_hlt();
75 return; 65 return;
76} 66}
77 67
78static struct platform_suspend_ops omap_pm_ops = { 68static struct platform_suspend_ops omap_pm_ops = {
79 .begin = omap4_pm_begin, 69 .begin = omap4_pm_begin,
80 .end = omap4_pm_end, 70 .end = omap4_pm_end,
81 .prepare = omap4_pm_prepare,
82 .enter = omap4_pm_enter, 71 .enter = omap4_pm_enter,
83 .finish = omap4_pm_finish,
84 .valid = suspend_valid_only_mem, 72 .valid = suspend_valid_only_mem,
85}; 73};
86#endif /* CONFIG_SUSPEND */ 74#endif /* CONFIG_SUSPEND */
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 68f57bb67fc5..b3f83799e6cf 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -74,5 +74,4 @@ static inline u32 sms_read_reg(u16 reg)
74 */ 74 */
75#define SDRC_MPURATE_LOOPS 96 75#define SDRC_MPURATE_LOOPS 96
76 76
77
78#endif 77#endif
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 2fb205a7f285..e3b5cd76c54c 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -1,6 +1,4 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/sleep.S
3 *
4 * (C) Copyright 2007 2 * (C) Copyright 2007
5 * Texas Instruments 3 * Texas Instruments
6 * Karthik Dasu <karthik-dp@ti.com> 4 * Karthik Dasu <karthik-dp@ti.com>
@@ -26,6 +24,7 @@
26 */ 24 */
27#include <linux/linkage.h> 25#include <linux/linkage.h>
28#include <asm/assembler.h> 26#include <asm/assembler.h>
27#include <plat/sram.h>
29#include <mach/io.h> 28#include <mach/io.h>
30 29
31#include "cm.h" 30#include "cm.h"
@@ -33,21 +32,27 @@
33#include "sdrc.h" 32#include "sdrc.h"
34#include "control.h" 33#include "control.h"
35 34
36#define SDRC_SCRATCHPAD_SEM_V 0xfa00291c 35/*
37 36 * Registers access definitions
38#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ 37 */
39 OMAP3430_PM_PREPWSTST) 38#define SDRC_SCRATCHPAD_SEM_OFFS 0xc
40#define PM_PREPWSTST_CORE_P 0x48306AE8 39#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\
41#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ 40 (SDRC_SCRATCHPAD_SEM_OFFS)
42 OMAP3430_PM_PREPWSTST) 41#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
42 OMAP3430_PM_PREPWSTST
43#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 43#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
44#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 44#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
45#define SRAM_BASE_P 0x40200000 45#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
46#define CONTROL_STAT 0x480022F0 46#define SRAM_BASE_P OMAP3_SRAM_PA
47#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is 47#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
48 * available */ 48#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
49#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\ 49 OMAP36XX_CONTROL_MEM_RTA_CTRL)
50 + SCRATCHPAD_MEM_OFFS) 50
51/* Move this as correct place is available */
52#define SCRATCHPAD_MEM_OFFS 0x310
53#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
54 OMAP343X_CONTROL_MEM_WKUP +\
55 SCRATCHPAD_MEM_OFFS)
51#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 56#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
52#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 57#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
53#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 58#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
@@ -59,48 +64,38 @@
59#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 64#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
60#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 65#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
61 66
62 .text 67
63/* Function to acquire the semaphore in scratchpad */ 68/*
64ENTRY(lock_scratchpad_sem) 69 * API functions
65 stmfd sp!, {lr} @ save registers on stack 70 */
66wait_sem: 71
67 mov r0,#1 72/*
68 ldr r1, sdrc_scratchpad_sem 73 * The "get_*restore_pointer" functions are used to provide a
69wait_loop: 74 * physical restore address where the ROM code jumps while waking
70 ldr r2, [r1] @ load the lock value 75 * up from MPU OFF/OSWR state.
71 cmp r2, r0 @ is the lock free ? 76 * The restore pointer is stored into the scratchpad.
72 beq wait_loop @ not free... 77 */
73 swp r2, r0, [r1] @ semaphore free so lock it and proceed
74 cmp r2, r0 @ did we succeed ?
75 beq wait_sem @ no - try again
76 ldmfd sp!, {pc} @ restore regs and return
77sdrc_scratchpad_sem:
78 .word SDRC_SCRATCHPAD_SEM_V
79ENTRY(lock_scratchpad_sem_sz)
80 .word . - lock_scratchpad_sem
81
82 .text
83/* Function to release the scratchpad semaphore */
84ENTRY(unlock_scratchpad_sem)
85 stmfd sp!, {lr} @ save registers on stack
86 ldr r3, sdrc_scratchpad_sem
87 mov r2,#0
88 str r2,[r3]
89 ldmfd sp!, {pc} @ restore regs and return
90ENTRY(unlock_scratchpad_sem_sz)
91 .word . - unlock_scratchpad_sem
92 78
93 .text 79 .text
94/* Function call to get the restore pointer for resume from OFF */ 80/* Function call to get the restore pointer for resume from OFF */
95ENTRY(get_restore_pointer) 81ENTRY(get_restore_pointer)
96 stmfd sp!, {lr} @ save registers on stack 82 stmfd sp!, {lr} @ save registers on stack
97 adr r0, restore 83 adr r0, restore
98 ldmfd sp!, {pc} @ restore regs and return 84 ldmfd sp!, {pc} @ restore regs and return
99ENTRY(get_restore_pointer_sz) 85ENTRY(get_restore_pointer_sz)
100 .word . - get_restore_pointer 86 .word . - get_restore_pointer
101 87
102 .text 88 .text
103/* Function call to get the restore pointer for for ES3 to resume from OFF */ 89/* Function call to get the restore pointer for 3630 resume from OFF */
90ENTRY(get_omap3630_restore_pointer)
91 stmfd sp!, {lr} @ save registers on stack
92 adr r0, restore_3630
93 ldmfd sp!, {pc} @ restore regs and return
94ENTRY(get_omap3630_restore_pointer_sz)
95 .word . - get_omap3630_restore_pointer
96
97 .text
98/* Function call to get the restore pointer for ES3 to resume from OFF */
104ENTRY(get_es3_restore_pointer) 99ENTRY(get_es3_restore_pointer)
105 stmfd sp!, {lr} @ save registers on stack 100 stmfd sp!, {lr} @ save registers on stack
106 adr r0, restore_es3 101 adr r0, restore_es3
@@ -108,54 +103,23 @@ ENTRY(get_es3_restore_pointer)
108ENTRY(get_es3_restore_pointer_sz) 103ENTRY(get_es3_restore_pointer_sz)
109 .word . - get_es3_restore_pointer 104 .word . - get_es3_restore_pointer
110 105
111ENTRY(es3_sdrc_fix) 106 .text
112 ldr r4, sdrc_syscfg @ get config addr 107/*
113 ldr r5, [r4] @ get value 108 * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
114 tst r5, #0x100 @ is part access blocked 109 * This function sets up a flag that will allow for this toggling to take
115 it eq 110 * place on 3630. Hopefully some version in the future may not need this.
116 biceq r5, r5, #0x100 @ clear bit if set 111 */
117 str r5, [r4] @ write back change 112ENTRY(enable_omap3630_toggle_l2_on_restore)
118 ldr r4, sdrc_mr_0 @ get config addr 113 stmfd sp!, {lr} @ save registers on stack
119 ldr r5, [r4] @ get value 114 /* Setup so that we will disable and enable l2 */
120 str r5, [r4] @ write back change 115 mov r1, #0x1
121 ldr r4, sdrc_emr2_0 @ get config addr 116 str r1, l2dis_3630
122 ldr r5, [r4] @ get value 117 ldmfd sp!, {pc} @ restore regs and return
123 str r5, [r4] @ write back change
124 ldr r4, sdrc_manual_0 @ get config addr
125 mov r5, #0x2 @ autorefresh command
126 str r5, [r4] @ kick off refreshes
127 ldr r4, sdrc_mr_1 @ get config addr
128 ldr r5, [r4] @ get value
129 str r5, [r4] @ write back change
130 ldr r4, sdrc_emr2_1 @ get config addr
131 ldr r5, [r4] @ get value
132 str r5, [r4] @ write back change
133 ldr r4, sdrc_manual_1 @ get config addr
134 mov r5, #0x2 @ autorefresh command
135 str r5, [r4] @ kick off refreshes
136 bx lr
137sdrc_syscfg:
138 .word SDRC_SYSCONFIG_P
139sdrc_mr_0:
140 .word SDRC_MR_0_P
141sdrc_emr2_0:
142 .word SDRC_EMR2_0_P
143sdrc_manual_0:
144 .word SDRC_MANUAL_0_P
145sdrc_mr_1:
146 .word SDRC_MR_1_P
147sdrc_emr2_1:
148 .word SDRC_EMR2_1_P
149sdrc_manual_1:
150 .word SDRC_MANUAL_1_P
151ENTRY(es3_sdrc_fix_sz)
152 .word . - es3_sdrc_fix
153 118
119 .text
154/* Function to call rom code to save secure ram context */ 120/* Function to call rom code to save secure ram context */
155ENTRY(save_secure_ram_context) 121ENTRY(save_secure_ram_context)
156 stmfd sp!, {r1-r12, lr} @ save registers on stack 122 stmfd sp!, {r1-r12, lr} @ save registers on stack
157save_secure_ram_debug:
158 /* b save_secure_ram_debug */ @ enable to debug save code
159 adr r3, api_params @ r3 points to parameters 123 adr r3, api_params @ r3 points to parameters
160 str r0, [r3,#0x4] @ r0 has sdram address 124 str r0, [r3,#0x4] @ r0 has sdram address
161 ldr r12, high_mask 125 ldr r12, high_mask
@@ -185,35 +149,162 @@ ENTRY(save_secure_ram_context_sz)
185 .word . - save_secure_ram_context 149 .word . - save_secure_ram_context
186 150
187/* 151/*
152 * ======================
153 * == Idle entry point ==
154 * ======================
155 */
156
157/*
188 * Forces OMAP into idle state 158 * Forces OMAP into idle state
189 * 159 *
190 * omap34xx_suspend() - This bit of code just executes the WFI 160 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
191 * for normal idles. 161 * and executes the WFI instruction. Calling WFI effectively changes the
162 * power domains states to the desired target power states.
163 *
192 * 164 *
193 * Note: This code get's copied to internal SRAM at boot. When the OMAP 165 * Notes:
194 * wakes up it continues execution at the point it went to sleep. 166 * - this code gets copied to internal SRAM at boot and after wake-up
167 * from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
168 * - when the OMAP wakes up it continues at different execution points
169 * depending on the low power mode (non-OFF vs OFF modes),
170 * cf. 'Resume path for xxx mode' comments.
195 */ 171 */
196ENTRY(omap34xx_cpu_suspend) 172ENTRY(omap34xx_cpu_suspend)
197 stmfd sp!, {r0-r12, lr} @ save registers on stack 173 stmfd sp!, {r0-r12, lr} @ save registers on stack
198loop:
199 /*b loop*/ @Enable to debug by stepping through code
200 /* r0 contains restore pointer in sdram */
201 /* r1 contains information about saving context */
202 ldr r4, sdrc_power @ read the SDRC_POWER register
203 ldr r5, [r4] @ read the contents of SDRC_POWER
204 orr r5, r5, #0x40 @ enable self refresh on idle req
205 str r5, [r4] @ write back to SDRC_POWER register
206 174
175 /*
176 * r0 contains restore pointer in sdram
177 * r1 contains information about saving context:
178 * 0 - No context lost
179 * 1 - Only L1 and logic lost
180 * 2 - Only L2 lost
181 * 3 - Both L1 and L2 lost
182 */
183
184 /* Directly jump to WFI is the context save is not required */
207 cmp r1, #0x0 185 cmp r1, #0x0
208 /* If context save is required, do that and execute wfi */ 186 beq omap3_do_wfi
209 bne save_context_wfi 187
188 /* Otherwise fall through to the save context code */
189save_context_wfi:
190 mov r8, r0 @ Store SDRAM address in r8
191 mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
192 mov r4, #0x1 @ Number of parameters for restore call
193 stmia r8!, {r4-r5} @ Push parameters for restore call
194 mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
195 stmia r8!, {r4-r5} @ Push parameters for restore call
196
197 /* Check what that target sleep state is from r1 */
198 cmp r1, #0x2 @ Only L2 lost, no need to save context
199 beq clean_caches
200
201l1_logic_lost:
202 /* Store sp and spsr to SDRAM */
203 mov r4, sp
204 mrs r5, spsr
205 mov r6, lr
206 stmia r8!, {r4-r6}
207 /* Save all ARM registers */
208 /* Coprocessor access control register */
209 mrc p15, 0, r6, c1, c0, 2
210 stmia r8!, {r6}
211 /* TTBR0, TTBR1 and Translation table base control */
212 mrc p15, 0, r4, c2, c0, 0
213 mrc p15, 0, r5, c2, c0, 1
214 mrc p15, 0, r6, c2, c0, 2
215 stmia r8!, {r4-r6}
216 /*
217 * Domain access control register, data fault status register,
218 * and instruction fault status register
219 */
220 mrc p15, 0, r4, c3, c0, 0
221 mrc p15, 0, r5, c5, c0, 0
222 mrc p15, 0, r6, c5, c0, 1
223 stmia r8!, {r4-r6}
224 /*
225 * Data aux fault status register, instruction aux fault status,
226 * data fault address register and instruction fault address register
227 */
228 mrc p15, 0, r4, c5, c1, 0
229 mrc p15, 0, r5, c5, c1, 1
230 mrc p15, 0, r6, c6, c0, 0
231 mrc p15, 0, r7, c6, c0, 2
232 stmia r8!, {r4-r7}
233 /*
234 * user r/w thread and process ID, user r/o thread and process ID,
235 * priv only thread and process ID, cache size selection
236 */
237 mrc p15, 0, r4, c13, c0, 2
238 mrc p15, 0, r5, c13, c0, 3
239 mrc p15, 0, r6, c13, c0, 4
240 mrc p15, 2, r7, c0, c0, 0
241 stmia r8!, {r4-r7}
242 /* Data TLB lockdown, instruction TLB lockdown registers */
243 mrc p15, 0, r5, c10, c0, 0
244 mrc p15, 0, r6, c10, c0, 1
245 stmia r8!, {r5-r6}
246 /* Secure or non secure vector base address, FCSE PID, Context PID*/
247 mrc p15, 0, r4, c12, c0, 0
248 mrc p15, 0, r5, c13, c0, 0
249 mrc p15, 0, r6, c13, c0, 1
250 stmia r8!, {r4-r6}
251 /* Primary remap, normal remap registers */
252 mrc p15, 0, r4, c10, c2, 0
253 mrc p15, 0, r5, c10, c2, 1
254 stmia r8!,{r4-r5}
255
256 /* Store current cpsr*/
257 mrs r2, cpsr
258 stmia r8!, {r2}
259
260 mrc p15, 0, r4, c1, c0, 0
261 /* save control register */
262 stmia r8!, {r4}
263
264clean_caches:
265 /*
266 * Clean Data or unified cache to POU
267 * How to invalidate only L1 cache???? - #FIX_ME#
268 * mcr p15, 0, r11, c7, c11, 1
269 */
270 cmp r1, #0x1 @ Check whether L2 inval is required
271 beq omap3_do_wfi
272
273clean_l2:
274 /*
275 * jump out to kernel flush routine
276 * - reuse that code is better
277 * - it executes in a cached space so is faster than refetch per-block
278 * - should be faster and will change with kernel
279 * - 'might' have to copy address, load and jump to it
280 */
281 ldr r1, kernel_flush
282 mov lr, pc
283 bx r1
284
285omap3_do_wfi:
286 ldr r4, sdrc_power @ read the SDRC_POWER register
287 ldr r5, [r4] @ read the contents of SDRC_POWER
288 orr r5, r5, #0x40 @ enable self refresh on idle req
289 str r5, [r4] @ write back to SDRC_POWER register
290
210 /* Data memory barrier and Data sync barrier */ 291 /* Data memory barrier and Data sync barrier */
211 mov r1, #0 292 mov r1, #0
212 mcr p15, 0, r1, c7, c10, 4 293 mcr p15, 0, r1, c7, c10, 4
213 mcr p15, 0, r1, c7, c10, 5 294 mcr p15, 0, r1, c7, c10, 5
214 295
296/*
297 * ===================================
298 * == WFI instruction => Enter idle ==
299 * ===================================
300 */
215 wfi @ wait for interrupt 301 wfi @ wait for interrupt
216 302
303/*
304 * ===================================
305 * == Resume path for non-OFF modes ==
306 * ===================================
307 */
217 nop 308 nop
218 nop 309 nop
219 nop 310 nop
@@ -226,9 +317,30 @@ loop:
226 nop 317 nop
227 bl wait_sdrc_ok 318 bl wait_sdrc_ok
228 319
229 ldmfd sp!, {r0-r12, pc} @ restore regs and return 320/*
321 * ===================================
322 * == Exit point from non-OFF modes ==
323 * ===================================
324 */
325 ldmfd sp!, {r0-r12, pc} @ restore regs and return
326
327
328/*
329 * ==============================
330 * == Resume path for OFF mode ==
331 * ==============================
332 */
333
334/*
335 * The restore_* functions are called by the ROM code
336 * when back from WFI in OFF mode.
337 * Cf. the get_*restore_pointer functions.
338 *
339 * restore_es3: applies to 34xx >= ES3.0
340 * restore_3630: applies to 36xx
341 * restore: common code for 3xxx
342 */
230restore_es3: 343restore_es3:
231 /*b restore_es3*/ @ Enable to debug restore code
232 ldr r5, pm_prepwstst_core_p 344 ldr r5, pm_prepwstst_core_p
233 ldr r4, [r5] 345 ldr r4, [r5]
234 and r4, r4, #0x3 346 and r4, r4, #0x3
@@ -245,82 +357,117 @@ copy_to_sram:
245 bne copy_to_sram 357 bne copy_to_sram
246 ldr r1, sram_base 358 ldr r1, sram_base
247 blx r1 359 blx r1
360 b restore
361
362restore_3630:
363 ldr r1, pm_prepwstst_core_p
364 ldr r2, [r1]
365 and r2, r2, #0x3
366 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
367 bne restore
368 /* Disable RTA before giving control */
369 ldr r1, control_mem_rta
370 mov r2, #OMAP36XX_RTA_DISABLE
371 str r2, [r1]
372
373 /* Fall through to common code for the remaining logic */
374
248restore: 375restore:
249 /* b restore*/ @ Enable to debug restore code 376 /*
250 /* Check what was the reason for mpu reset and store the reason in r9*/ 377 * Check what was the reason for mpu reset and store the reason in r9:
251 /* 1 - Only L1 and logic lost */ 378 * 0 - No context lost
252 /* 2 - Only L2 lost - In this case, we wont be here */ 379 * 1 - Only L1 and logic lost
253 /* 3 - Both L1 and L2 lost */ 380 * 2 - Only L2 lost - In this case, we wont be here
254 ldr r1, pm_pwstctrl_mpu 381 * 3 - Both L1 and L2 lost
382 */
383 ldr r1, pm_pwstctrl_mpu
255 ldr r2, [r1] 384 ldr r2, [r1]
256 and r2, r2, #0x3 385 and r2, r2, #0x3
257 cmp r2, #0x0 @ Check if target power state was OFF or RET 386 cmp r2, #0x0 @ Check if target power state was OFF or RET
258 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost 387 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
259 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation 388 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
260 bne logic_l1_restore 389 bne logic_l1_restore
390
391 ldr r0, l2dis_3630
392 cmp r0, #0x1 @ should we disable L2 on 3630?
393 bne skipl2dis
394 mrc p15, 0, r0, c1, c0, 1
395 bic r0, r0, #2 @ disable L2 cache
396 mcr p15, 0, r0, c1, c0, 1
397skipl2dis:
261 ldr r0, control_stat 398 ldr r0, control_stat
262 ldr r1, [r0] 399 ldr r1, [r0]
263 and r1, #0x700 400 and r1, #0x700
264 cmp r1, #0x300 401 cmp r1, #0x300
265 beq l2_inv_gp 402 beq l2_inv_gp
266 mov r0, #40 @ set service ID for PPA 403 mov r0, #40 @ set service ID for PPA
267 mov r12, r0 @ copy secure Service ID in r12 404 mov r12, r0 @ copy secure Service ID in r12
268 mov r1, #0 @ set task id for ROM code in r1 405 mov r1, #0 @ set task id for ROM code in r1
269 mov r2, #4 @ set some flags in r2, r6 406 mov r2, #4 @ set some flags in r2, r6
270 mov r6, #0xff 407 mov r6, #0xff
271 adr r3, l2_inv_api_params @ r3 points to dummy parameters 408 adr r3, l2_inv_api_params @ r3 points to dummy parameters
272 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 409 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
273 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 410 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
274 .word 0xE1600071 @ call SMI monitor (smi #1) 411 .word 0xE1600071 @ call SMI monitor (smi #1)
275 /* Write to Aux control register to set some bits */ 412 /* Write to Aux control register to set some bits */
276 mov r0, #42 @ set service ID for PPA 413 mov r0, #42 @ set service ID for PPA
277 mov r12, r0 @ copy secure Service ID in r12 414 mov r12, r0 @ copy secure Service ID in r12
278 mov r1, #0 @ set task id for ROM code in r1 415 mov r1, #0 @ set task id for ROM code in r1
279 mov r2, #4 @ set some flags in r2, r6 416 mov r2, #4 @ set some flags in r2, r6
280 mov r6, #0xff 417 mov r6, #0xff
281 ldr r4, scratchpad_base 418 ldr r4, scratchpad_base
282 ldr r3, [r4, #0xBC] @ r3 points to parameters 419 ldr r3, [r4, #0xBC] @ r3 points to parameters
283 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 420 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
284 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 421 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
285 .word 0xE1600071 @ call SMI monitor (smi #1) 422 .word 0xE1600071 @ call SMI monitor (smi #1)
286 423
287#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 424#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
288 /* Restore L2 aux control register */ 425 /* Restore L2 aux control register */
289 @ set service ID for PPA 426 @ set service ID for PPA
290 mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 427 mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
291 mov r12, r0 @ copy service ID in r12 428 mov r12, r0 @ copy service ID in r12
292 mov r1, #0 @ set task ID for ROM code in r1 429 mov r1, #0 @ set task ID for ROM code in r1
293 mov r2, #4 @ set some flags in r2, r6 430 mov r2, #4 @ set some flags in r2, r6
294 mov r6, #0xff 431 mov r6, #0xff
295 ldr r4, scratchpad_base 432 ldr r4, scratchpad_base
296 ldr r3, [r4, #0xBC] 433 ldr r3, [r4, #0xBC]
297 adds r3, r3, #8 @ r3 points to parameters 434 adds r3, r3, #8 @ r3 points to parameters
298 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 435 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
299 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 436 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
300 .word 0xE1600071 @ call SMI monitor (smi #1) 437 .word 0xE1600071 @ call SMI monitor (smi #1)
301#endif 438#endif
302 b logic_l1_restore 439 b logic_l1_restore
440
303l2_inv_api_params: 441l2_inv_api_params:
304 .word 0x1, 0x00 442 .word 0x1, 0x00
305l2_inv_gp: 443l2_inv_gp:
306 /* Execute smi to invalidate L2 cache */ 444 /* Execute smi to invalidate L2 cache */
307 mov r12, #0x1 @ set up to invalide L2 445 mov r12, #0x1 @ set up to invalidate L2
308smi: .word 0xE1600070 @ Call SMI monitor (smieq) 446 .word 0xE1600070 @ Call SMI monitor (smieq)
309 /* Write to Aux control register to set some bits */ 447 /* Write to Aux control register to set some bits */
310 ldr r4, scratchpad_base 448 ldr r4, scratchpad_base
311 ldr r3, [r4,#0xBC] 449 ldr r3, [r4,#0xBC]
312 ldr r0, [r3,#4] 450 ldr r0, [r3,#4]
313 mov r12, #0x3 451 mov r12, #0x3
314 .word 0xE1600070 @ Call SMI monitor (smieq) 452 .word 0xE1600070 @ Call SMI monitor (smieq)
315 ldr r4, scratchpad_base 453 ldr r4, scratchpad_base
316 ldr r3, [r4,#0xBC] 454 ldr r3, [r4,#0xBC]
317 ldr r0, [r3,#12] 455 ldr r0, [r3,#12]
318 mov r12, #0x2 456 mov r12, #0x2
319 .word 0xE1600070 @ Call SMI monitor (smieq) 457 .word 0xE1600070 @ Call SMI monitor (smieq)
320logic_l1_restore: 458logic_l1_restore:
459 ldr r1, l2dis_3630
460 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
461 bne skipl2reen
462 mrc p15, 0, r1, c1, c0, 1
463 orr r1, r1, #2 @ re-enable L2 cache
464 mcr p15, 0, r1, c1, c0, 1
465skipl2reen:
321 mov r1, #0 466 mov r1, #0
322 /* Invalidate all instruction caches to PoU 467 /*
323 * and flush branch target cache */ 468 * Invalidate all instruction caches to PoU
469 * and flush branch target cache
470 */
324 mcr p15, 0, r1, c7, c5, 0 471 mcr p15, 0, r1, c7, c5, 0
325 472
326 ldr r4, scratchpad_base 473 ldr r4, scratchpad_base
@@ -341,33 +488,33 @@ logic_l1_restore:
341 MCR p15, 0, r6, c2, c0, 1 488 MCR p15, 0, r6, c2, c0, 1
342 /* Translation table base control register */ 489 /* Translation table base control register */
343 MCR p15, 0, r7, c2, c0, 2 490 MCR p15, 0, r7, c2, c0, 2
344 /*domain access Control Register */ 491 /* Domain access Control Register */
345 MCR p15, 0, r8, c3, c0, 0 492 MCR p15, 0, r8, c3, c0, 0
346 /* data fault status Register */ 493 /* Data fault status Register */
347 MCR p15, 0, r9, c5, c0, 0 494 MCR p15, 0, r9, c5, c0, 0
348 495
349 ldmia r3!,{r4-r8} 496 ldmia r3!,{r4-r8}
350 /* instruction fault status Register */ 497 /* Instruction fault status Register */
351 MCR p15, 0, r4, c5, c0, 1 498 MCR p15, 0, r4, c5, c0, 1
352 /*Data Auxiliary Fault Status Register */ 499 /* Data Auxiliary Fault Status Register */
353 MCR p15, 0, r5, c5, c1, 0 500 MCR p15, 0, r5, c5, c1, 0
354 /*Instruction Auxiliary Fault Status Register*/ 501 /* Instruction Auxiliary Fault Status Register*/
355 MCR p15, 0, r6, c5, c1, 1 502 MCR p15, 0, r6, c5, c1, 1
356 /*Data Fault Address Register */ 503 /* Data Fault Address Register */
357 MCR p15, 0, r7, c6, c0, 0 504 MCR p15, 0, r7, c6, c0, 0
358 /*Instruction Fault Address Register*/ 505 /* Instruction Fault Address Register*/
359 MCR p15, 0, r8, c6, c0, 2 506 MCR p15, 0, r8, c6, c0, 2
360 ldmia r3!,{r4-r7} 507 ldmia r3!,{r4-r7}
361 508
362 /* user r/w thread and process ID */ 509 /* User r/w thread and process ID */
363 MCR p15, 0, r4, c13, c0, 2 510 MCR p15, 0, r4, c13, c0, 2
364 /* user ro thread and process ID */ 511 /* User ro thread and process ID */
365 MCR p15, 0, r5, c13, c0, 3 512 MCR p15, 0, r5, c13, c0, 3
366 /*Privileged only thread and process ID */ 513 /* Privileged only thread and process ID */
367 MCR p15, 0, r6, c13, c0, 4 514 MCR p15, 0, r6, c13, c0, 4
368 /* cache size selection */ 515 /* Cache size selection */
369 MCR p15, 2, r7, c0, c0, 0 516 MCR p15, 2, r7, c0, c0, 0
370 ldmia r3!,{r4-r8} 517 ldmia r3!,{r4-r8}
371 /* Data TLB lockdown registers */ 518 /* Data TLB lockdown registers */
372 MCR p15, 0, r4, c10, c0, 0 519 MCR p15, 0, r4, c10, c0, 0
373 /* Instruction TLB lockdown registers */ 520 /* Instruction TLB lockdown registers */
@@ -379,26 +526,27 @@ logic_l1_restore:
379 /* Context PID */ 526 /* Context PID */
380 MCR p15, 0, r8, c13, c0, 1 527 MCR p15, 0, r8, c13, c0, 1
381 528
382 ldmia r3!,{r4-r5} 529 ldmia r3!,{r4-r5}
383 /* primary memory remap register */ 530 /* Primary memory remap register */
384 MCR p15, 0, r4, c10, c2, 0 531 MCR p15, 0, r4, c10, c2, 0
385 /*normal memory remap register */ 532 /* Normal memory remap register */
386 MCR p15, 0, r5, c10, c2, 1 533 MCR p15, 0, r5, c10, c2, 1
387 534
388 /* Restore cpsr */ 535 /* Restore cpsr */
389 ldmia r3!,{r4} /*load CPSR from SDRAM*/ 536 ldmia r3!,{r4} @ load CPSR from SDRAM
390 msr cpsr, r4 /*store cpsr */ 537 msr cpsr, r4 @ store cpsr
391 538
392 /* Enabling MMU here */ 539 /* Enabling MMU here */
393 mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ 540 mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
394 /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ 541 /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
395 and r7, #0x7 542 and r7, #0x7
396 cmp r7, #0x0 543 cmp r7, #0x0
397 beq usettbr0 544 beq usettbr0
398ttbr_error: 545ttbr_error:
399 /* More work needs to be done to support N[0:2] value other than 0 546 /*
400 * So looping here so that the error can be detected 547 * More work needs to be done to support N[0:2] value other than 0
401 */ 548 * So looping here so that the error can be detected
549 */
402 b ttbr_error 550 b ttbr_error
403usettbr0: 551usettbr0:
404 mrc p15, 0, r2, c2, c0, 0 552 mrc p15, 0, r2, c2, c0, 0
@@ -406,21 +554,25 @@ usettbr0:
406 and r2, r5 554 and r2, r5
407 mov r4, pc 555 mov r4, pc
408 ldr r5, table_index_mask 556 ldr r5, table_index_mask
409 and r4, r5 /* r4 = 31 to 20 bits of pc */ 557 and r4, r5 @ r4 = 31 to 20 bits of pc
410 /* Extract the value to be written to table entry */ 558 /* Extract the value to be written to table entry */
411 ldr r1, table_entry 559 ldr r1, table_entry
412 add r1, r1, r4 /* r1 has value to be written to table entry*/ 560 /* r1 has the value to be written to table entry*/
561 add r1, r1, r4
413 /* Getting the address of table entry to modify */ 562 /* Getting the address of table entry to modify */
414 lsr r4, #18 563 lsr r4, #18
415 add r2, r4 /* r2 has the location which needs to be modified */ 564 /* r2 has the location which needs to be modified */
565 add r2, r4
416 /* Storing previous entry of location being modified */ 566 /* Storing previous entry of location being modified */
417 ldr r5, scratchpad_base 567 ldr r5, scratchpad_base
418 ldr r4, [r2] 568 ldr r4, [r2]
419 str r4, [r5, #0xC0] 569 str r4, [r5, #0xC0]
420 /* Modify the table entry */ 570 /* Modify the table entry */
421 str r1, [r2] 571 str r1, [r2]
422 /* Storing address of entry being modified 572 /*
423 * - will be restored after enabling MMU */ 573 * Storing address of entry being modified
574 * - will be restored after enabling MMU
575 */
424 ldr r5, scratchpad_base 576 ldr r5, scratchpad_base
425 str r2, [r5, #0xC4] 577 str r2, [r5, #0xC4]
426 578
@@ -429,8 +581,11 @@ usettbr0:
429 mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array 581 mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
430 mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB 582 mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
431 mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB 583 mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
432 /* Restore control register but dont enable caches here*/ 584 /*
433 /* Caches will be enabled after restoring MMU table entry */ 585 * Restore control register. This enables the MMU.
586 * The caches and prediction are not enabled here, they
587 * will be enabled after restoring the MMU table entry.
588 */
434 ldmia r3!, {r4} 589 ldmia r3!, {r4}
435 /* Store previous value of control register in scratchpad */ 590 /* Store previous value of control register in scratchpad */
436 str r4, [r5, #0xC8] 591 str r4, [r5, #0xC8]
@@ -438,212 +593,144 @@ usettbr0:
438 and r4, r2 593 and r4, r2
439 mcr p15, 0, r4, c1, c0, 0 594 mcr p15, 0, r4, c1, c0, 0
440 595
441 ldmfd sp!, {r0-r12, pc} @ restore regs and return 596/*
442save_context_wfi: 597 * ==============================
443 /*b save_context_wfi*/ @ enable to debug save code 598 * == Exit point from OFF mode ==
444 mov r8, r0 /* Store SDRAM address in r8 */ 599 * ==============================
445 mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 600 */
446 mov r4, #0x1 @ Number of parameters for restore call 601 ldmfd sp!, {r0-r12, pc} @ restore regs and return
447 stmia r8!, {r4-r5} @ Push parameters for restore call
448 mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
449 stmia r8!, {r4-r5} @ Push parameters for restore call
450 /* Check what that target sleep state is:stored in r1*/
451 /* 1 - Only L1 and logic lost */
452 /* 2 - Only L2 lost */
453 /* 3 - Both L1 and L2 lost */
454 cmp r1, #0x2 /* Only L2 lost */
455 beq clean_l2
456 cmp r1, #0x1 /* L2 retained */
457 /* r9 stores whether to clean L2 or not*/
458 moveq r9, #0x0 /* Dont Clean L2 */
459 movne r9, #0x1 /* Clean L2 */
460l1_logic_lost:
461 /* Store sp and spsr to SDRAM */
462 mov r4, sp
463 mrs r5, spsr
464 mov r6, lr
465 stmia r8!, {r4-r6}
466 /* Save all ARM registers */
467 /* Coprocessor access control register */
468 mrc p15, 0, r6, c1, c0, 2
469 stmia r8!, {r6}
470 /* TTBR0, TTBR1 and Translation table base control */
471 mrc p15, 0, r4, c2, c0, 0
472 mrc p15, 0, r5, c2, c0, 1
473 mrc p15, 0, r6, c2, c0, 2
474 stmia r8!, {r4-r6}
475 /* Domain access control register, data fault status register,
476 and instruction fault status register */
477 mrc p15, 0, r4, c3, c0, 0
478 mrc p15, 0, r5, c5, c0, 0
479 mrc p15, 0, r6, c5, c0, 1
480 stmia r8!, {r4-r6}
481 /* Data aux fault status register, instruction aux fault status,
482 datat fault address register and instruction fault address register*/
483 mrc p15, 0, r4, c5, c1, 0
484 mrc p15, 0, r5, c5, c1, 1
485 mrc p15, 0, r6, c6, c0, 0
486 mrc p15, 0, r7, c6, c0, 2
487 stmia r8!, {r4-r7}
488 /* user r/w thread and process ID, user r/o thread and process ID,
489 priv only thread and process ID, cache size selection */
490 mrc p15, 0, r4, c13, c0, 2
491 mrc p15, 0, r5, c13, c0, 3
492 mrc p15, 0, r6, c13, c0, 4
493 mrc p15, 2, r7, c0, c0, 0
494 stmia r8!, {r4-r7}
495 /* Data TLB lockdown, instruction TLB lockdown registers */
496 mrc p15, 0, r5, c10, c0, 0
497 mrc p15, 0, r6, c10, c0, 1
498 stmia r8!, {r5-r6}
499 /* Secure or non secure vector base address, FCSE PID, Context PID*/
500 mrc p15, 0, r4, c12, c0, 0
501 mrc p15, 0, r5, c13, c0, 0
502 mrc p15, 0, r6, c13, c0, 1
503 stmia r8!, {r4-r6}
504 /* Primary remap, normal remap registers */
505 mrc p15, 0, r4, c10, c2, 0
506 mrc p15, 0, r5, c10, c2, 1
507 stmia r8!,{r4-r5}
508 602
509 /* Store current cpsr*/
510 mrs r2, cpsr
511 stmia r8!, {r2}
512 603
513 mrc p15, 0, r4, c1, c0, 0 604/*
514 /* save control register */ 605 * Internal functions
515 stmia r8!, {r4} 606 */
516clean_caches:
517 /* Clean Data or unified cache to POU*/
518 /* How to invalidate only L1 cache???? - #FIX_ME# */
519 /* mcr p15, 0, r11, c7, c11, 1 */
520 cmp r9, #1 /* Check whether L2 inval is required or not*/
521 bne skip_l2_inval
522clean_l2:
523 /* read clidr */
524 mrc p15, 1, r0, c0, c0, 1
525 /* extract loc from clidr */
526 ands r3, r0, #0x7000000
527 /* left align loc bit field */
528 mov r3, r3, lsr #23
529 /* if loc is 0, then no need to clean */
530 beq finished
531 /* start clean at cache level 0 */
532 mov r10, #0
533loop1:
534 /* work out 3x current cache level */
535 add r2, r10, r10, lsr #1
536 /* extract cache type bits from clidr*/
537 mov r1, r0, lsr r2
538 /* mask of the bits for current cache only */
539 and r1, r1, #7
540 /* see what cache we have at this level */
541 cmp r1, #2
542 /* skip if no cache, or just i-cache */
543 blt skip
544 /* select current cache level in cssr */
545 mcr p15, 2, r10, c0, c0, 0
546 /* isb to sych the new cssr&csidr */
547 isb
548 /* read the new csidr */
549 mrc p15, 1, r1, c0, c0, 0
550 /* extract the length of the cache lines */
551 and r2, r1, #7
552 /* add 4 (line length offset) */
553 add r2, r2, #4
554 ldr r4, assoc_mask
555 /* find maximum number on the way size */
556 ands r4, r4, r1, lsr #3
557 /* find bit position of way size increment */
558 clz r5, r4
559 ldr r7, numset_mask
560 /* extract max number of the index size*/
561 ands r7, r7, r1, lsr #13
562loop2:
563 mov r9, r4
564 /* create working copy of max way size*/
565loop3:
566 /* factor way and cache number into r11 */
567 orr r11, r10, r9, lsl r5
568 /* factor index number into r11 */
569 orr r11, r11, r7, lsl r2
570 /*clean & invalidate by set/way */
571 mcr p15, 0, r11, c7, c10, 2
572 /* decrement the way*/
573 subs r9, r9, #1
574 bge loop3
575 /*decrement the index */
576 subs r7, r7, #1
577 bge loop2
578skip:
579 add r10, r10, #2
580 /* increment cache number */
581 cmp r3, r10
582 bgt loop1
583finished:
584 /*swith back to cache level 0 */
585 mov r10, #0
586 /* select current cache level in cssr */
587 mcr p15, 2, r10, c0, c0, 0
588 isb
589skip_l2_inval:
590 /* Data memory barrier and Data sync barrier */
591 mov r1, #0
592 mcr p15, 0, r1, c7, c10, 4
593 mcr p15, 0, r1, c7, c10, 5
594 607
595 wfi @ wait for interrupt 608/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
596 nop 609 .text
597 nop 610ENTRY(es3_sdrc_fix)
598 nop 611 ldr r4, sdrc_syscfg @ get config addr
599 nop 612 ldr r5, [r4] @ get value
600 nop 613 tst r5, #0x100 @ is part access blocked
601 nop 614 it eq
602 nop 615 biceq r5, r5, #0x100 @ clear bit if set
603 nop 616 str r5, [r4] @ write back change
604 nop 617 ldr r4, sdrc_mr_0 @ get config addr
605 nop 618 ldr r5, [r4] @ get value
606 bl wait_sdrc_ok 619 str r5, [r4] @ write back change
607 /* restore regs and return */ 620 ldr r4, sdrc_emr2_0 @ get config addr
608 ldmfd sp!, {r0-r12, pc} 621 ldr r5, [r4] @ get value
622 str r5, [r4] @ write back change
623 ldr r4, sdrc_manual_0 @ get config addr
624 mov r5, #0x2 @ autorefresh command
625 str r5, [r4] @ kick off refreshes
626 ldr r4, sdrc_mr_1 @ get config addr
627 ldr r5, [r4] @ get value
628 str r5, [r4] @ write back change
629 ldr r4, sdrc_emr2_1 @ get config addr
630 ldr r5, [r4] @ get value
631 str r5, [r4] @ write back change
632 ldr r4, sdrc_manual_1 @ get config addr
633 mov r5, #0x2 @ autorefresh command
634 str r5, [r4] @ kick off refreshes
635 bx lr
636
637sdrc_syscfg:
638 .word SDRC_SYSCONFIG_P
639sdrc_mr_0:
640 .word SDRC_MR_0_P
641sdrc_emr2_0:
642 .word SDRC_EMR2_0_P
643sdrc_manual_0:
644 .word SDRC_MANUAL_0_P
645sdrc_mr_1:
646 .word SDRC_MR_1_P
647sdrc_emr2_1:
648 .word SDRC_EMR2_1_P
649sdrc_manual_1:
650 .word SDRC_MANUAL_1_P
651ENTRY(es3_sdrc_fix_sz)
652 .word . - es3_sdrc_fix
653
654/*
655 * This function implements the erratum ID i581 WA:
656 * SDRC state restore before accessing the SDRAM
657 *
658 * Only used at return from non-OFF mode. For OFF
659 * mode the ROM code configures the SDRC and
660 * the DPLL before calling the restore code directly
661 * from DDR.
662 */
609 663
610/* Make sure SDRC accesses are ok */ 664/* Make sure SDRC accesses are ok */
611wait_sdrc_ok: 665wait_sdrc_ok:
612 ldr r4, cm_idlest1_core 666
613 ldr r5, [r4] 667/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
614 and r5, r5, #0x2 668 ldr r4, cm_idlest_ckgen
615 cmp r5, #0 669wait_dpll3_lock:
616 bne wait_sdrc_ok 670 ldr r5, [r4]
617 ldr r4, sdrc_power 671 tst r5, #1
618 ldr r5, [r4] 672 beq wait_dpll3_lock
619 bic r5, r5, #0x40 673
620 str r5, [r4] 674 ldr r4, cm_idlest1_core
675wait_sdrc_ready:
676 ldr r5, [r4]
677 tst r5, #0x2
678 bne wait_sdrc_ready
679 /* allow DLL powerdown upon hw idle req */
680 ldr r4, sdrc_power
681 ldr r5, [r4]
682 bic r5, r5, #0x40
683 str r5, [r4]
684
685is_dll_in_lock_mode:
686 /* Is dll in lock mode? */
687 ldr r4, sdrc_dlla_ctrl
688 ldr r5, [r4]
689 tst r5, #0x4
690 bxne lr @ Return if locked
691 /* wait till dll locks */
692wait_dll_lock_timed:
693 ldr r4, wait_dll_lock_counter
694 add r4, r4, #1
695 str r4, wait_dll_lock_counter
696 ldr r4, sdrc_dlla_status
697 /* Wait 20uS for lock */
698 mov r6, #8
621wait_dll_lock: 699wait_dll_lock:
622 /* Is dll in lock mode? */ 700 subs r6, r6, #0x1
623 ldr r4, sdrc_dlla_ctrl 701 beq kick_dll
624 ldr r5, [r4] 702 ldr r5, [r4]
625 tst r5, #0x4 703 and r5, r5, #0x4
626 bxne lr 704 cmp r5, #0x4
627 /* wait till dll locks */ 705 bne wait_dll_lock
628 ldr r4, sdrc_dlla_status 706 bx lr @ Return when locked
629 ldr r5, [r4] 707
630 and r5, r5, #0x4 708 /* disable/reenable DLL if not locked */
631 cmp r5, #0x4 709kick_dll:
632 bne wait_dll_lock 710 ldr r4, sdrc_dlla_ctrl
633 bx lr 711 ldr r5, [r4]
712 mov r6, r5
713 bic r6, #(1<<3) @ disable dll
714 str r6, [r4]
715 dsb
716 orr r6, r6, #(1<<3) @ enable dll
717 str r6, [r4]
718 dsb
719 ldr r4, kick_counter
720 add r4, r4, #1
721 str r4, kick_counter
722 b wait_dll_lock_timed
634 723
635cm_idlest1_core: 724cm_idlest1_core:
636 .word CM_IDLEST1_CORE_V 725 .word CM_IDLEST1_CORE_V
726cm_idlest_ckgen:
727 .word CM_IDLEST_CKGEN_V
637sdrc_dlla_status: 728sdrc_dlla_status:
638 .word SDRC_DLLA_STATUS_V 729 .word SDRC_DLLA_STATUS_V
639sdrc_dlla_ctrl: 730sdrc_dlla_ctrl:
640 .word SDRC_DLLA_CTRL_V 731 .word SDRC_DLLA_CTRL_V
641pm_prepwstst_core:
642 .word PM_PREPWSTST_CORE_V
643pm_prepwstst_core_p: 732pm_prepwstst_core_p:
644 .word PM_PREPWSTST_CORE_P 733 .word PM_PREPWSTST_CORE_P
645pm_prepwstst_mpu:
646 .word PM_PREPWSTST_MPU_V
647pm_pwstctrl_mpu: 734pm_pwstctrl_mpu:
648 .word PM_PWSTCTRL_MPU_P 735 .word PM_PWSTCTRL_MPU_P
649scratchpad_base: 736scratchpad_base:
@@ -651,13 +738,7 @@ scratchpad_base:
651sram_base: 738sram_base:
652 .word SRAM_BASE_P + 0x8000 739 .word SRAM_BASE_P + 0x8000
653sdrc_power: 740sdrc_power:
654 .word SDRC_POWER_V 741 .word SDRC_POWER_V
655clk_stabilize_delay:
656 .word 0x000001FF
657assoc_mask:
658 .word 0x3ff
659numset_mask:
660 .word 0x7fff
661ttbrbit_mask: 742ttbrbit_mask:
662 .word 0xFFFFC000 743 .word 0xFFFFC000
663table_index_mask: 744table_index_mask:
@@ -668,5 +749,20 @@ cache_pred_disable_mask:
668 .word 0xFFFFE7FB 749 .word 0xFFFFE7FB
669control_stat: 750control_stat:
670 .word CONTROL_STAT 751 .word CONTROL_STAT
752control_mem_rta:
753 .word CONTROL_MEM_RTA_CTRL
754kernel_flush:
755 .word v7_flush_dcache_all
756l2dis_3630:
757 .word 0
758 /*
759 * When exporting to userspace while the counters are in SRAM,
760 * these 2 words need to be at the end to facilitate retrival!
761 */
762kick_counter:
763 .word 0
764wait_dll_lock_counter:
765 .word 0
766
671ENTRY(omap34xx_cpu_suspend_sz) 767ENTRY(omap34xx_cpu_suspend_sz)
672 .word . - omap34xx_cpu_suspend 768 .word . - omap34xx_cpu_suspend
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index fa2e5bffbb8e..6983cb4d4cae 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -28,9 +28,16 @@ config S3C2412_DMA
28 28
29config S3C2412_PM 29config S3C2412_PM
30 bool 30 bool
31 select S3C2412_PM_SLEEP
31 help 32 help
32 Internal config node to apply S3C2412 power management 33 Internal config node to apply S3C2412 power management
33 34
35config S3C2412_PM_SLEEP
36 bool
37 help
38 Internal config node to apply sleep for S3C2412 power management.
39 Can be selected by another SoCs with similar sleep procedure.
40
34# Note, the S3C2412 IOtiming support is in plat-s3c24xx 41# Note, the S3C2412 IOtiming support is in plat-s3c24xx
35 42
36config S3C2412_CPUFREQ 43config S3C2412_CPUFREQ
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 530ec46cbaea..6c48a91ea39e 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -14,7 +14,8 @@ obj-$(CONFIG_CPU_S3C2412) += irq.o
14obj-$(CONFIG_CPU_S3C2412) += clock.o 14obj-$(CONFIG_CPU_S3C2412) += clock.o
15obj-$(CONFIG_CPU_S3C2412) += gpio.o 15obj-$(CONFIG_CPU_S3C2412) += gpio.o
16obj-$(CONFIG_S3C2412_DMA) += dma.o 16obj-$(CONFIG_S3C2412_DMA) += dma.o
17obj-$(CONFIG_S3C2412_PM) += pm.o sleep.o 17obj-$(CONFIG_S3C2412_PM) += pm.o
18obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep.o
18obj-$(CONFIG_S3C2412_CPUFREQ) += cpu-freq.o 19obj-$(CONFIG_S3C2412_CPUFREQ) += cpu-freq.o
19 20
20# Machine support 21# Machine support
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index 27b3e7c9d613..df8d14974c90 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -27,6 +27,7 @@ config S3C2416_DMA
27 27
28config S3C2416_PM 28config S3C2416_PM
29 bool 29 bool
30 select S3C2412_PM_SLEEP
30 help 31 help
31 Internal config node to apply S3C2416 power management 32 Internal config node to apply S3C2416 power management
32 33
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 28677caf3613..461aa035afc0 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -378,6 +378,12 @@ static struct max8998_regulator_data aquila_regulators[] = {
378static struct max8998_platform_data aquila_max8998_pdata = { 378static struct max8998_platform_data aquila_max8998_pdata = {
379 .num_regulators = ARRAY_SIZE(aquila_regulators), 379 .num_regulators = ARRAY_SIZE(aquila_regulators),
380 .regulators = aquila_regulators, 380 .regulators = aquila_regulators,
381 .buck1_set1 = S5PV210_GPH0(3),
382 .buck1_set2 = S5PV210_GPH0(4),
383 .buck2_set3 = S5PV210_GPH0(5),
384 .buck1_max_voltage1 = 1200000,
385 .buck1_max_voltage2 = 1200000,
386 .buck2_max_voltage = 1200000,
381}; 387};
382#endif 388#endif
383 389
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index b1dcf964a768..e22d5112fd44 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -518,6 +518,12 @@ static struct max8998_regulator_data goni_regulators[] = {
518static struct max8998_platform_data goni_max8998_pdata = { 518static struct max8998_platform_data goni_max8998_pdata = {
519 .num_regulators = ARRAY_SIZE(goni_regulators), 519 .num_regulators = ARRAY_SIZE(goni_regulators),
520 .regulators = goni_regulators, 520 .regulators = goni_regulators,
521 .buck1_set1 = S5PV210_GPH0(3),
522 .buck1_set2 = S5PV210_GPH0(4),
523 .buck2_set3 = S5PV210_GPH0(5),
524 .buck1_max_voltage1 = 1200000,
525 .buck1_max_voltage2 = 1200000,
526 .buck2_max_voltage = 1200000,
521}; 527};
522#endif 528#endif
523 529
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index a285d13c7416..f428c4db2b60 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -1,4 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Magnus Damm
2 * Copyright (C) 2008 Renesas Solutions Corp. 3 * Copyright (C) 2008 Renesas Solutions Corp.
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
@@ -14,24 +15,45 @@
14 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
16 */ 17 */
17#include <mach/hardware.h>
18#include <mach/irqs.h> 18#include <mach/irqs.h>
19 19
20#define INTCA_BASE 0xe6980000
21#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */
22#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */
23#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */
24#define INTLVLB_OFFS 0x00000034 /* previous priority level */
25
20 .macro disable_fiq 26 .macro disable_fiq
21 .endm 27 .endm
22 28
23 .macro get_irqnr_preamble, base, tmp 29 .macro get_irqnr_preamble, base, tmp
24 ldr \base, =INTFLGA 30 ldr \base, =INTCA_BASE
25 .endm 31 .endm
26 32
27 .macro arch_ret_to_user, tmp1, tmp2 33 .macro arch_ret_to_user, tmp1, tmp2
28 .endm 34 .endm
29 35
30 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 36 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
31 ldr \irqnr, [\base] 37 /* The single INTFLGA read access below results in the following:
38 *
39 * 1. INTLVLB is updated with old priority value from INTLVLA
40 * 2. Highest priority interrupt is accepted
41 * 3. INTLVLA is updated to contain priority of accepted interrupt
42 * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
43 */
44 ldr \irqnr, [\base, #INTFLGA_OFFS]
45
46 /* Restore INTLVLA with the value saved in INTLVLB.
47 * This is required to support interrupt priorities properly.
48 */
49 ldrb \tmp, [\base, #INTLVLB_OFFS]
50 strb \tmp, [\base, #INTLVLA_OFFS]
51
52 /* Handle invalid vector number case */
32 cmp \irqnr, #0 53 cmp \irqnr, #0
33 beq 1000f 54 beq 1000f
34 /* intevt to irq number */ 55
56 /* Convert vector to irq number, same as the evt2irq() macro */
35 lsr \irqnr, \irqnr, #0x5 57 lsr \irqnr, \irqnr, #0x5
36 subs \irqnr, \irqnr, #16 58 subs \irqnr, \irqnr, #16
37 59
diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
index 4aecf6e3a859..2b8fd8b942fe 100644
--- a/arch/arm/mach-shmobile/include/mach/vmalloc.h
+++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h
@@ -2,6 +2,6 @@
2#define __ASM_MACH_VMALLOC_H 2#define __ASM_MACH_VMALLOC_H
3 3
4/* Vmalloc at ... - 0xe5ffffff */ 4/* Vmalloc at ... - 0xe5ffffff */
5#define VMALLOC_END 0xe6000000 5#define VMALLOC_END 0xe6000000UL
6 6
7#endif /* __ASM_MACH_VMALLOC_H */ 7#endif /* __ASM_MACH_VMALLOC_H */
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 5905100b29a1..9967d5e855c7 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -11,6 +11,7 @@
11#ifndef __ARCH_ARM_OMAP_SRAM_H 11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H 12#define __ARCH_ARM_OMAP_SRAM_H
13 13
14#ifndef __ASSEMBLY__
14extern void * omap_sram_push(void * start, unsigned long size); 15extern void * omap_sram_push(void * start, unsigned long size);
15extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); 16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
16 17
@@ -74,4 +75,14 @@ extern void omap_push_sram_idle(void);
74static inline void omap_push_sram_idle(void) {} 75static inline void omap_push_sram_idle(void) {}
75#endif /* CONFIG_PM */ 76#endif /* CONFIG_PM */
76 77
78#endif /* __ASSEMBLY__ */
79
80/*
81 * OMAP2+: define the SRAM PA addresses.
82 * Used by the SRAM management code and the idle sleep code.
83 */
84#define OMAP2_SRAM_PA 0x40200000
85#define OMAP3_SRAM_PA 0x40200000
86#define OMAP4_SRAM_PA 0x40300000
87
77#endif 88#endif
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 819ea0cfb81a..1a686c89d8dd 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -41,15 +41,12 @@
41 41
42#define OMAP1_SRAM_PA 0x20000000 42#define OMAP1_SRAM_PA 0x20000000
43#define OMAP1_SRAM_VA VMALLOC_END 43#define OMAP1_SRAM_VA VMALLOC_END
44#define OMAP2_SRAM_PA 0x40200000 44#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
45#define OMAP2_SRAM_PUB_PA 0x4020f800
46#define OMAP2_SRAM_VA 0xfe400000 45#define OMAP2_SRAM_VA 0xfe400000
47#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) 46#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
48#define OMAP3_SRAM_PA 0x40200000
49#define OMAP3_SRAM_VA 0xfe400000 47#define OMAP3_SRAM_VA 0xfe400000
50#define OMAP3_SRAM_PUB_PA 0x40208000 48#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
51#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) 49#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
52#define OMAP4_SRAM_PA 0x40300000
53#define OMAP4_SRAM_VA 0xfe400000 50#define OMAP4_SRAM_VA 0xfe400000
54#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) 51#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
55#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) 52#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000)
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 5a27b1b538f2..eb105e61c746 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -8,7 +8,7 @@ config PLAT_S3C24XX
8 default y 8 default y
9 select NO_IOPORT 9 select NO_IOPORT
10 select ARCH_REQUIRE_GPIOLIB 10 select ARCH_REQUIRE_GPIOLIB
11 select S3C_DEVICE_NAND 11 select S3C_DEV_NAND
12 select S3C_GPIO_CFG_S3C24XX 12 select S3C_GPIO_CFG_S3C24XX
13 help 13 help
14 Base platform code for any Samsung S3C24XX device 14 Base platform code for any Samsung S3C24XX device
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 14:33:50 -0500