Merge tag 'tags/soc_for_v3.10' into mvebu/dt

Pulling in mvebu branches which contain changes to armada*.dts? files for LPAE conversion. mvebu soc changes for v3.10 - use the mvebu-mbus driver - prep for LPAE support Depends: - mvebu/cleanup (tags/cleanup_for_v3.10) - mvebu/drivers (tags/drivers_for_v3.10)
author: Jason Cooper <jason@lakedaemon.net> 2013-04-15 10:55:23 -0400
committer: Jason Cooper <jason@lakedaemon.net> 2013-04-15 10:55:23 -0400
commit: b757f17e9184b65428c48a281d82f9acb3e96f0e (patch)
tree: 7dc22c9f82f78c20caeff00fdd68a2e92e40504a /arch/arm
parent: 3c76a8a95daeecd881718f88324041f6a5faab86 (diff)
parent: da497f6fbaa190d34907ecc9dd85cfc62ba9f5a2 (diff)
109 files changed, 513 insertions, 1029 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0c990b75082f..9462dd931b33 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -49,7 +49,6 @@ config ARM
        select HAVE_REGS_AND_STACK_ACCESS_API
        select HAVE_SYSCALL_TRACEPOINTS
        select HAVE_UID16
-        select HAVE_VIRT_TO_BUS
        select KTIME_SCALAR
        select PERF_USE_VMALLOC
        select RTC_LIB
@@ -563,6 +562,7 @@ config ARCH_DOVE
        select PINCTRL_DOVE
        select PLAT_ORION_LEGACY
        select USB_ARCH_HAS_EHCI
+        select MVEBU_MBUS
        help
          Support for the Marvell Dove SoC 88AP510
@@ -576,6 +576,7 @@ config ARCH_KIRKWOOD
        select PINCTRL
        select PINCTRL_KIRKWOOD
        select PLAT_ORION_LEGACY
+        select MVEBU_MBUS
        help
          Support for the following Marvell Kirkwood series SoCs:
          88F6180, 88F6192 and 88F6281.
@@ -587,6 +588,7 @@ config ARCH_MV78XX0
        select GENERIC_CLOCKEVENTS
        select PCI
        select PLAT_ORION_LEGACY
+        select MVEBU_MBUS
        help
          Support for the following Marvell MV78xx0 series SoCs:
          MV781x0, MV782x0.
@@ -599,6 +601,7 @@ config ARCH_ORION5X
        select GENERIC_CLOCKEVENTS
        select PCI
        select PLAT_ORION_LEGACY
+        select MVEBU_MBUS
        help
          Support for the following Marvell Orion 5x series SoCs:
          Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@ -743,6 +746,7 @@ config ARCH_RPC
        select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        select NO_IOPORT
+        select VIRT_TO_BUS
        help
          On the Acorn Risc-PC, Linux can support the internal IDE disk and
          CD-ROM interface, serial and parallel port, and the floppy drive.
@@ -878,6 +882,7 @@ config ARCH_SHARK
        select ISA_DMA
        select NEED_MACH_MEMORY_H
        select PCI
+        select VIRT_TO_BUS
        select ZONE_DMA
        help
          Support for the StrongARM based Digital DNARD machine, also known
@@ -1005,12 +1010,12 @@ config ARCH_MULTI_V4_V5
        bool
 config ARCH_MULTI_V6
-        bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
+        bool "ARMv6 based platforms (ARM11)"
        select ARCH_MULTI_V6_V7
        select CPU_V6
 config ARCH_MULTI_V7
-        bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
+        bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
        default y
        select ARCH_MULTI_V6_V7
        select ARCH_VEXPRESS
@@ -1461,10 +1466,6 @@ config ISA_DMA
        bool
        select ISA_DMA_API
-config ARCH_NO_VIRT_TO_BUS
-        def_bool y
-        depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
 # Select ISA DMA interface
 config ISA_DMA_API
        bool
@@ -1656,13 +1657,16 @@ config LOCAL_TIMERS
          accounting to be spread across the timer interval, preventing a
          "thundering herd" at every timer tick.
+# The GPIO number here must be sorted by descending number. In case of
+# a multiplatform kernel, we just want the highest value required by the
+# selected platforms.
 config ARCH_NR_GPIO
        int
        default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
-        default 355 if ARCH_U8500
-        default 264 if MACH_H4700
        default 512 if SOC_OMAP5
+        default 355 if ARCH_U8500
        default 288 if ARCH_VT8500 || ARCH_SUNXI
+        default 264 if MACH_H4700
        default 0
        help
          Maximum number of GPIOs in the system.
@@ -1886,8 +1890,9 @@ config XEN_DOM0
 config XEN
        bool "Xen guest support on ARM (EXPERIMENTAL)"
-        depends on ARM && OF
+        depends on ARM && AEABI && OF
        depends on CPU_V7 && !CPU_V6
+        depends on !GENERIC_ATOMIC64
        help
          Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index acddddac7ee4..ecfcdba2d17c 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -492,7 +492,7 @@ config DEBUG_IMX_UART_PORT
                                                DEBUG_IMX31_UART || \
                                                DEBUG_IMX35_UART || \
                                                DEBUG_IMX51_UART || \
-                                                DEBUG_IMX50_IMX53_UART || \
+                                                DEBUG_IMX53_UART || \
                                                DEBUG_IMX6Q_UART
        default 1
        help
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 71768b8a1ab9..84aa2caf07ed 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -115,4 +115,4 @@ i:
        $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
        $(obj)/Image System.map "$(INSTALL_PATH)"
-subdir-     := bootp compressed
+subdir-     := bootp compressed dts
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 758c4ea90344..9693f796bcfe 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -73,11 +73,6 @@
                               clocks = <&coreclk 2>;
                };
-                addr-decoding@d0020000 {
-                        compatible = "marvell,armada-addr-decoding-controller";
-                        reg = <0xd0020000 0x258>;
-                };
                sata@d00a0000 {
                        compatible = "marvell,orion-sata";
                        reg = <0xd00a0000 0x2400>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index aa98e641931f..a98c0d50fbbe 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -238,8 +238,32 @@
                                nand {
                                        pinctrl_nand: nand-0 {
                                                atmel,pins =
-                                                        <3 4 0x0 0x1    /* PD5 gpio RDY pin pull_up */
+                                                        <3 0 0x1 0x0    /* PD0 periph A Read Enable */
-                                                         3 5 0x0 0x1>;  /* PD4 gpio enable pin pull_up */
+                                                         3 1 0x1 0x0    /* PD1 periph A Write Enable */
+                                                         3 2 0x1 0x0    /* PD2 periph A Address Latch Enable */
+                                                         3 3 0x1 0x0    /* PD3 periph A Command Latch Enable */
+                                                         3 4 0x0 0x1    /* PD4 gpio Chip Enable pin pull_up */
+                                                         3 5 0x0 0x1    /* PD5 gpio RDY/BUSY pin pull_up */
+                                                         3 6 0x1 0x0    /* PD6 periph A Data bit 0 */
+                                                         3 7 0x1 0x0    /* PD7 periph A Data bit 1 */
+                                                         3 8 0x1 0x0    /* PD8 periph A Data bit 2 */
+                                                         3 9 0x1 0x0    /* PD9 periph A Data bit 3 */
+                                                         3 10 0x1 0x0   /* PD10 periph A Data bit 4 */
+                                                         3 11 0x1 0x0   /* PD11 periph A Data bit 5 */
+                                                         3 12 0x1 0x0   /* PD12 periph A Data bit 6 */
+                                                         3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */
+                                        };
+                                        pinctrl_nand_16bits: nand_16bits-0 {
+                                                atmel,pins =
+                                                        <3 14 0x1 0x0   /* PD14 periph A Data bit 8 */
+                                                         3 15 0x1 0x0   /* PD15 periph A Data bit 9 */
+                                                         3 16 0x1 0x0   /* PD16 periph A Data bit 10 */
+                                                         3 17 0x1 0x0   /* PD17 periph A Data bit 11 */
+                                                         3 18 0x1 0x0   /* PD18 periph A Data bit 12 */
+                                                         3 19 0x1 0x0   /* PD19 periph A Data bit 13 */
+                                                         3 20 0x1 0x0   /* PD20 periph A Data bit 14 */
+                                                         3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */
                                        };
                                };
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 4bf2a8774aa7..7e0481e2441a 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -105,7 +105,7 @@
                        compatible = "fixed-clock";
                        reg = <1>;
                        #clock-cells = <0>;
-                        clock-frequency = <150000000>;
+                        clock-frequency = <250000000>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 69140ba99f46..9de93096601a 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -319,9 +319,8 @@
                                };
                        };
-                        ab8500@5 {
+                        ab8500 {
                                compatible = "stericsson,ab8500";
-                                reg = <5>; /* mailbox 5 is i2c */
                                interrupt-parent = <&intc>;
                                interrupts = <0 40 0x4>;
                                interrupt-controller;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index e1347fceb5bc..1a62bcf18aa3 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -275,18 +275,27 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x12680000 0x1000>;
                        interrupts = <0 35 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
                };
                pdma1: pdma@12690000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x12690000 0x1000>;
                        interrupts = <0 36 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
                };
                mdma1: mdma@12850000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x12850000 0x1000>;
                        interrupts = <0 34 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <1>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 5f3562ad6746..9a99755920c0 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -142,12 +142,18 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x120000 0x1000>;
                        interrupts = <0 34 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
                };
                pdma1: pdma@121B0000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x121000 0x1000>;
                        interrupts = <0 35 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
                };
        };
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
index 592fb9dc35bd..379128eb9d98 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/href.dtsi
@@ -221,7 +221,7 @@
                                };
                        };
-                        ab8500@5 {
+                        ab8500 {
                                ab8500-regulators {
                                        ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
                                                regulator-name = "V-DISPLAY";
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
index 55f4191a626e..2b587a74b813 100644
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -158,7 +158,7 @@
                                };
                        };
-                        ab8500@5 {
+                        ab8500 {
                                ab8500-regulators {
                                        ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
                                                regulator-name = "V-DISPLAY";
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index e54fffd48369..468c0a1d48d9 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -42,10 +42,9 @@
                        fsl,pins = <689 0x10000         /* DISP1_DRDY   */
                                    482 0x10000         /* DISP1_HSYNC  */
                                    489 0x10000         /* DISP1_VSYNC  */
-                                    684 0x10000         /* DISP1_DAT_0  */
                                    515 0x10000         /* DISP1_DAT_22 */
                                    523 0x10000         /* DISP1_DAT_23 */
-                                    543 0x10000         /* DISP1_DAT_21 */
+                                    545 0x10000         /* DISP1_DAT_21 */
                                    553 0x10000         /* DISP1_DAT_20 */
                                    558 0x10000         /* DISP1_DAT_19 */
                                    564 0x10000         /* DISP1_DAT_18 */
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 27f31a5fa494..d3ec32f6b790 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -298,7 +298,7 @@
                                };
                        };
-                        ab8500@5 {
+                        ab8500 {
                                ab8500-regulators {
                                        ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
                                                regulator-name = "V-DISPLAY";
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 936d2306e7e1..7e8769bd5977 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -75,6 +75,9 @@
                                compatible = "arm,pl330", "arm,primecell";
                                reg = <0xffe01000 0x1000>;
                                interrupts = <0 180 4>;
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
                        };
                };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9a428931d042..48d00a099ce3 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -118,6 +118,7 @@
                compatible = "arm,cortex-a9-twd-timer";
                reg = <0x50040600 0x20>;
                interrupts = <1 13 0x304>;
+                clocks = <&tegra_car 132>;
        };
        intc: interrupt-controller {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 767803e1fd55..9d87a3ffe998 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -119,6 +119,7 @@
                compatible = "arm,cortex-a9-twd-timer";
                reg = <0x50040600 0x20>;
                interrupts = <1 13 0xf04>;
+                clocks = <&tegra_car 214>;
        };
        intc: interrupt-controller {
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index fbbc5bb022d5..6a99e30f81d2 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -116,6 +116,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_MXS_SOC=y
 CONFIG_SND_SOC_MXS_SGTL5000=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
 CONFIG_USB_STORAGE=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index b16bae2c9a60..bd07864f14a0 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -126,6 +126,8 @@ CONFIG_INPUT_MISC=y
 CONFIG_INPUT_TWL4030_PWRBUTTON=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=32
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
index 5c27696de14f..8b1f37bfeeec 100644
--- a/arch/arm/include/asm/xen/events.h
+++ b/arch/arm/include/asm/xen/events.h
@@ -2,6 +2,7 @@
 #define _ASM_ARM_XEN_EVENTS_H
 #include <asm/ptrace.h>
+#include <asm/atomic.h>
 enum ipi_vector {
        XEN_PLACEHOLDER_VECTOR,
@@ -15,26 +16,8 @@ static inline int xen_irqs_disabled(struct pt_regs *regs)
        return raw_irqs_disabled_flags(regs->ARM_cpsr);
 }
-/*
+#define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr),      \
- * We cannot use xchg because it does not support 8-byte
+                                                            atomic64_t, \
- * values. However it is safe to use {ldr,dtd}exd directly because all
+                                                            counter), (val))
- * platforms which Xen can run on support those instructions.
- */
-static inline xen_ulong_t xchg_xen_ulong(xen_ulong_t *ptr, xen_ulong_t val)
-{
-        xen_ulong_t oldval;
-        unsigned int tmp;
-        wmb();
-        asm volatile("@ xchg_xen_ulong\n"
-                "1:     ldrexd  %0, %H0, [%3]\n"
-                "       strexd  %1, %2, %H2, [%3]\n"
-                "       teq     %1, #0\n"
-                "       bne     1b"
-                : "=&r" (oldval), "=&r" (tmp)
-                : "r" (val), "r" (ptr)
-                : "memory", "cc");
-        return oldval;
-}
 #endif /* _ASM_ARM_XEN_EVENTS_H */
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index 865c6d02b332..df191afa3be1 100644
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -12,7 +12,7 @@
 */
 #define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE    0xfeb00000
+#define ARMADA_370_XP_REGS_VIRT_BASE    0xfec00000
        .macro  addruart, rp, rv, tmp
        ldr     \rp, =ARMADA_370_XP_REGS_PHYS_BASE
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 31644f1978d5..79078edbb9bc 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -480,7 +480,7 @@ static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
        evt->features   = CLOCK_EVT_FEAT_ONESHOT |
                          CLOCK_EVT_FEAT_PERIODIC |
                          CLOCK_EVT_FEAT_DUMMY;
-        evt->rating     = 400;
+        evt->rating     = 100;
        evt->mult       = 1;
        evt->set_mode   = broadcast_timer_set_mode;
diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index d912e7397ecc..94b0650ea98f 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -14,31 +14,15 @@
        .text
        .align  5
-        .word   0
-1:      subs    r2, r2, #4              @ 1 do we have enough
-        blt     5f                      @ 1 bytes to align with?
-        cmp     r3, #2                  @ 1
-        strltb  r1, [ip], #1            @ 1
-        strleb  r1, [ip], #1            @ 1
-        strb    r1, [ip], #1            @ 1
-        add     r2, r2, r3              @ 1 (r2 = r2 - (4 - r3))
-/*
- * The pointer is now aligned and the length is adjusted.  Try doing the
- * memset again.
- */
 ENTRY(memset)
-/*
+        ands    r3, r0, #3              @ 1 unaligned?
- * Preserve the contents of r0 for the return value.
+        mov     ip, r0                  @ preserve r0 as return value
- */
+        bne     6f                      @ 1
-        mov     ip, r0
-        ands    r3, ip, #3              @ 1 unaligned?
-        bne     1b                      @ 1
 /*
 * we know that the pointer in ip is aligned to a word boundary.
 */
-        orr     r1, r1, r1, lsl #8
+1:      orr     r1, r1, r1, lsl #8
        orr     r1, r1, r1, lsl #16
        mov     r3, r1
        cmp     r2, #16
@@ -127,4 +111,13 @@ ENTRY(memset)
        tst     r2, #1
        strneb  r1, [ip], #1
        mov     pc, lr
+6:      subs    r2, r2, #4              @ 1 do we have enough
+        blt     5b                      @ 1 bytes to align with?
+        cmp     r3, #2                  @ 1
+        strltb  r1, [ip], #1            @ 1
+        strleb  r1, [ip], #1            @ 1
+        strb    r1, [ip], #1            @ 1
+        add     r2, r2, r3              @ 1 (r2 = r2 - (4 - r3))
+        b       1b
 ENDPROC(memset)
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 2ea7059b840b..c20a870ea9c9 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -176,6 +176,7 @@ static struct w1_gpio_platform_data w1_gpio_pdata = {
        /* If you choose to use a pin other than PB16 it needs to be 3.3V */
        .pin            = AT91_PIN_PB16,
        .is_open_drain  = 1,
+        .ext_pullup_enable_pin  = -EINVAL,
 };
 static struct platform_device w1_device = {
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index a033b8df9fb2..869cbecf00b7 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -188,6 +188,7 @@ static struct spi_board_info portuxg20_spi_devices[] = {
 static struct w1_gpio_platform_data w1_gpio_pdata = {
        .pin            = AT91_PIN_PA29,
        .is_open_drain  = 1,
+        .ext_pullup_enable_pin  = -EINVAL,
 };
 static struct platform_device w1_device = {
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index eed465ab0dd7..5fc23771c154 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -209,6 +209,14 @@ extern int at91_get_gpio_value(unsigned pin);
 extern void at91_gpio_suspend(void);
 extern void at91_gpio_resume(void);
+#ifdef CONFIG_PINCTRL_AT91
+extern void at91_pinctrl_gpio_suspend(void);
+extern void at91_pinctrl_gpio_resume(void);
+#else
+static inline void at91_pinctrl_gpio_suspend(void) {}
+static inline void at91_pinctrl_gpio_resume(void) {}
+#endif
 #endif  /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 8e210262aeee..e0ca59171022 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -92,23 +92,21 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 void at91_irq_suspend(void)
 {
-        int i = 0, bit;
+        int bit = -1;
        if (has_aic5()) {
                /* disable enabled irqs */
-                while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
+                while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
                        at91_aic_write(AT91_AIC5_SSR,
                                       bit & AT91_AIC5_INTSEL_MSK);
                        at91_aic_write(AT91_AIC5_IDCR, 1);
-                        i = bit;
                }
                /* enable wakeup irqs */
-                i = 0;
+                bit = -1;
-                while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
+                while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
                        at91_aic_write(AT91_AIC5_SSR,
                                       bit & AT91_AIC5_INTSEL_MSK);
                        at91_aic_write(AT91_AIC5_IECR, 1);
-                        i = bit;
                }
        } else {
                at91_aic_write(AT91_AIC_IDCR, *backups);
@@ -118,23 +116,21 @@ void at91_irq_suspend(void)
 void at91_irq_resume(void)
 {
-        int i = 0, bit;
+        int bit = -1;
        if (has_aic5()) {
                /* disable wakeup irqs */
-                while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
+                while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
                        at91_aic_write(AT91_AIC5_SSR,
                                       bit & AT91_AIC5_INTSEL_MSK);
                        at91_aic_write(AT91_AIC5_IDCR, 1);
-                        i = bit;
                }
                /* enable irqs disabled for suspend */
-                i = 0;
+                bit = -1;
-                while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
+                while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
                        at91_aic_write(AT91_AIC5_SSR,
                                       bit & AT91_AIC5_INTSEL_MSK);
                        at91_aic_write(AT91_AIC5_IECR, 1);
-                        i = bit;
                }
        } else {
                at91_aic_write(AT91_AIC_IDCR, *wakeups);
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index adb6db888a1f..73f1f250403a 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -201,7 +201,10 @@ extern u32 at91_slow_clock_sz;
 static int at91_pm_enter(suspend_state_t state)
 {
-        at91_gpio_suspend();
+        if (of_have_populated_dt())
+                at91_pinctrl_gpio_suspend();
+        else
+                at91_gpio_suspend();
        at91_irq_suspend();
        pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
@@ -286,7 +289,10 @@ static int at91_pm_enter(suspend_state_t state)
 error:
        target_state = PM_SUSPEND_ON;
        at91_irq_resume();
-        at91_gpio_resume();
+        if (of_have_populated_dt())
+                at91_pinctrl_gpio_resume();
+        else
+                at91_gpio_resume();
        return 0;
 }
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index a685e9706b7b..45b7c71d9cc1 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -743,6 +743,9 @@ EXPORT_SYMBOL(edma_free_channel);
 */
 int edma_alloc_slot(unsigned ctlr, int slot)
 {
+        if (!edma_cc[ctlr])
+                return -EINVAL;
        if (slot >= 0)
                slot = EDMA_CHAN_SLOT(slot);
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 3f0a858fb597..4d9d2ffc4535 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,4 +1,4 @@
-obj-y                           += common.o addr-map.o irq.o
+obj-y                           += common.o irq.o
 obj-$(CONFIG_DOVE_LEGACY)       += mpp.o
 obj-$(CONFIG_PCI)               += pcie.o
 obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
deleted file mode 100644
index 2a06c0163418..000000000000
--- a/arch/arm/mach-dove/addr-map.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * arch/arm/mach-dove/addr-map.c
- *
- * Address map functions for Marvell Dove 88AP510 SoC
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mbus.h>
-#include <linux/io.h>
-#include <asm/mach/arch.h>
-#include <asm/setup.h>
-#include <mach/dove.h>
-#include <plat/addr-map.h>
-#include "common.h"
-/*
- * Generic Address Decode Windows bit settings
- */
-#define TARGET_DDR              0x0
-#define TARGET_BOOTROM          0x1
-#define TARGET_CESA             0x3
-#define TARGET_PCIE0            0x4
-#define TARGET_PCIE1            0x8
-#define TARGET_SCRATCHPAD       0xd
-#define ATTR_CESA               0x01
-#define ATTR_BOOTROM            0xfd
-#define ATTR_DEV_SPI0_ROM       0xfe
-#define ATTR_DEV_SPI1_ROM       0xfb
-#define ATTR_PCIE_IO            0xe0
-#define ATTR_PCIE_MEM           0xe8
-#define ATTR_SCRATCHPAD         0x0
-static inline void __iomem *ddr_map_sc(int i)
-{
-        return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
-}
-/*
- * Description of the windows needed by the platform code
- */
-static struct __initdata orion_addr_map_cfg addr_map_cfg = {
-        .num_wins = 8,
-        .remappable_wins = 4,
-        .bridge_virt_base = BRIDGE_VIRT_BASE,
-};
-static const struct __initdata orion_addr_map_info addr_map_info[] = {
-        /*
-         * Windows for PCIe IO+MEM space.
-         */
-        { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
-          TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE
-        },
-        { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
-          TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE
-        },
-        { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
-          TARGET_PCIE0, ATTR_PCIE_MEM, -1
-        },
-        { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
-          TARGET_PCIE1, ATTR_PCIE_MEM, -1
-        },
-        /*
-         * Window for CESA engine.
-         */
-        { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
-          TARGET_CESA, ATTR_CESA, -1
-        },
-        /*
-         * Window to the BootROM for Standby and Sleep Resume
-         */
-        { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
-          TARGET_BOOTROM, ATTR_BOOTROM, -1
-        },
-        /*
-         * Window to the PMU Scratch Pad space
-         */
-        { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
-          TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1
-        },
-        /* End marker */
-        { -1, 0, 0, 0, 0, 0 }
-};
-void __init dove_setup_cpu_mbus(void)
-{
-        int i;
-        int cs;
-        /*
-         * Disable, clear and configure windows.
-         */
-        orion_config_wins(&addr_map_cfg, addr_map_info);
-        /*
-         * Setup MBUS dram target info.
-         */
-        orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-        for (i = 0, cs = 0; i < 2; i++) {
-                u32 map = readl(ddr_map_sc(i));
-                /*
-                 * Chip select enabled?
-                 */
-                if (map & 1) {
-                        struct mbus_dram_window *w;
-                        w = &orion_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0; /* CS address decoding done inside */
-                                          /* the DDR controller, no need to  */
-                                          /* provide attributes */
-                        w->base = map & 0xff800000;
-                        w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
-                }
-        }
-        orion_mbus_dram_info.num_cs = cs;
-}
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index fbde1dd67113..0b142803b2e1 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -64,7 +64,7 @@ static void __init dove_dt_init(void)
 #ifdef CONFIG_CACHE_TAUROS2
        tauros2_init(0);
 #endif
-        dove_setup_cpu_mbus();
+        dove_setup_cpu_wins();
        /* Setup root of clk tree */
        dove_of_clk_init();
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index c6b3b2bb50e7..e2b5da031f96 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -224,6 +224,9 @@ void __init dove_i2c_init(void)
 void __init dove_init_early(void)
 {
        orion_time_set_base(TIMER_VIRT_BASE);
+        mvebu_mbus_init("marvell,dove-mbus",
+                        BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
+                        DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
 }
 static int __init dove_find_tclk(void)
@@ -326,6 +329,40 @@ void __init dove_sdio1_init(void)
        platform_device_register(&dove_sdio1);
 }
+void __init dove_setup_cpu_wins(void)
+{
+        /*
+         * The PCIe windows will no longer be statically allocated
+         * here once Dove is migrated to the pci-mvebu driver.
+         */
+        mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                          DOVE_PCIE0_IO_PHYS_BASE,
+                                          DOVE_PCIE0_IO_SIZE,
+                                          DOVE_PCIE0_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          DOVE_PCIE1_IO_PHYS_BASE,
+                                          DOVE_PCIE1_IO_SIZE,
+                                          DOVE_PCIE1_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                          DOVE_PCIE0_MEM_PHYS_BASE,
+                                          DOVE_PCIE0_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          DOVE_PCIE1_MEM_PHYS_BASE,
+                                          DOVE_PCIE1_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+        mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE,
+                              DOVE_CESA_SIZE);
+        mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE,
+                              DOVE_BOOTROM_SIZE);
+        mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE,
+                              DOVE_SCRATCHPAD_SIZE);
+}
 void __init dove_init(void)
 {
        pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
@@ -334,7 +371,7 @@ void __init dove_init(void)
 #ifdef CONFIG_CACHE_TAUROS2
        tauros2_init(0);
 #endif
-        dove_setup_cpu_mbus();
+        dove_setup_cpu_wins();
        /* Setup root of clk tree */
        dove_clk_init();
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index ee59fba4c6d1..e86347928b67 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -23,7 +23,7 @@ void dove_map_io(void);
 void dove_init(void);
 void dove_init_early(void);
 void dove_init_irq(void);
-void dove_setup_cpu_mbus(void);
+void dove_setup_cpu_wins(void);
 void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void dove_sata_init(struct mv_sata_platform_data *sata_data);
 #ifdef CONFIG_PCI
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index 661725e3115a..0c4b35f4ee5b 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -77,6 +77,8 @@
 /* North-South Bridge */
 #define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x20000)
 #define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x20000)
+#define  BRIDGE_WINS_BASE       (BRIDGE_PHYS_BASE)
+#define  BRIDGE_WINS_SZ         (0x80)
 /* Cryptographic Engine */
 #define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x30000)
@@ -168,6 +170,9 @@
 #define  DOVE_SSP_CLOCK_ENABLE          (1 << 1)
 #define  DOVE_SSP_BPB_CLOCK_SRC_SSP     (1 << 11)
 /* Memory Controller */
+#define DOVE_MC_PHYS_BASE       (DOVE_NB_REGS_PHYS_BASE + 0x00000)
+#define  DOVE_MC_WINS_BASE      (DOVE_MC_PHYS_BASE + 0x100)
+#define  DOVE_MC_WINS_SZ        (0x8)
 #define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE + 0x00000)
 /* LCD Controller */
diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
index abda5a18a664..0f2111a11315 100644
--- a/arch/arm/mach-footbridge/Kconfig
+++ b/arch/arm/mach-footbridge/Kconfig
@@ -67,6 +67,7 @@ config ARCH_NETWINDER
        select ISA
        select ISA_DMA
        select PCI
+        select VIRT_TO_BUS
        help
          Say Y here if you intend to run this kernel on the Rebel.COM
          NetWinder.  Information about this machine can be found at:
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 74e3a34d78b8..e13a8fa5e62c 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -264,6 +264,7 @@ int __init mx35_clocks_init(void)
        clk_prepare_enable(clk[gpio3_gate]);
        clk_prepare_enable(clk[iim_gate]);
        clk_prepare_enable(clk[emi_gate]);
+        clk_prepare_enable(clk[max_gate]);
        /*
         * SCC is needed to boot via mmc after a watchdog reset. The clock code
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 7b025ee528a5..2f9ff93a4e61 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -172,7 +172,7 @@ static struct clk *clk[clk_max];
 static struct clk_onecell_data clk_data;
 static enum mx6q_clks const clks_init_on[] __initconst = {
-        mmdc_ch0_axi, rom,
+        mmdc_ch0_axi, rom, pll1_sys,
 };
 static struct clk_div_table clk_enet_ref_table[] = {
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 921fc1555854..a58c8b0527cc 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -26,16 +26,16 @@ ENDPROC(v7_secondary_startup)
 #ifdef CONFIG_PM
 /*
- * The following code is located into the .data section.  This is to
+ * The following code must assume it is running from physical address
- * allow phys_l2x0_saved_regs to be accessed with a relative load
+ * where absolute virtual addresses to the data section have to be
- * as we are running on physical address here.
+ * turned into relative ones.
 */
-        .data
-        .align
 #ifdef CONFIG_CACHE_L2X0
        .macro  pl310_resume
-        ldr     r2, phys_l2x0_saved_regs
+        adr     r0, l2x0_saved_regs_offset
+        ldr     r2, [r0]
+        add     r2, r2, r0
        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
        ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value
        str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl
@@ -43,9 +43,9 @@ ENDPROC(v7_secondary_startup)
        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
        .endm
-        .globl  phys_l2x0_saved_regs
+l2x0_saved_regs_offset:
-phys_l2x0_saved_regs:
+        .word   l2x0_saved_regs - .
-        .long   0
 #else
        .macro  pl310_resume
        .endm
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 03b65e5ea541..82348391582a 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -27,6 +27,11 @@ static const char * const imx25_dt_board_compat[] __initconst = {
        NULL
 };
+static void __init imx25_timer_init(void)
+{
+        mx25_clocks_init_dt();
+}
 DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
        .map_io         = mx25_map_io,
        .init_early     = imx25_init_early,
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index ee42d20cba19..5faba7a3c95f 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -22,8 +22,6 @@
 #include "common.h"
 #include "hardware.h"
-extern unsigned long phys_l2x0_saved_regs;
 static int imx6q_suspend_finish(unsigned long val)
 {
        cpu_do_idle();
@@ -57,18 +55,5 @@ static const struct platform_suspend_ops imx6q_pm_ops = {
 void __init imx6q_pm_init(void)
 {
-        /*
-         * The l2x0 core code provides an infrastucture to save and restore
-         * l2x0 registers across suspend/resume cycle.  But because imx6q
-         * retains L2 content during suspend and needs to resume L2 before
-         * MMU is enabled, it can only utilize register saving support and
-         * have to take care of restoring on its own.  So we save physical
-         * address of the data structure used by l2x0 core to save registers,
-         * and later restore the necessary ones in imx6q resume entry.
-         */
-#ifdef CONFIG_CACHE_L2X0
-        phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
-#endif
        suspend_set_ops(&imx6q_pm_ops);
 }
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index d42730a1d4ab..d599e354ca57 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -163,6 +163,7 @@ static struct platform_device vulcan_max6369 = {
 static struct w1_gpio_platform_data vulcan_w1_gpio_pdata = {
        .pin                    = 14,
+        .ext_pullup_enable_pin  = -EINVAL,
 };
 static struct platform_device vulcan_w1_gpio = {
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 4cc4bee4d0cf..d805f8078fa3 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,4 +1,4 @@
-obj-y                           += common.o addr-map.o irq.o pcie.o mpp.o
+obj-y                           += common.o irq.o pcie.o mpp.o
 obj-$(CONFIG_MACH_DB88F6281_BP)         += db88f6281-bp-setup.o
 obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6192-nas-setup.o
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
deleted file mode 100644
index 8f0d162a1e1d..000000000000
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/addr-map.c
- *
- * Address map functions for Marvell Kirkwood SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mbus.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <plat/addr-map.h>
-#include "common.h"
-/*
- * Generic Address Decode Windows bit settings
- */
-#define TARGET_DEV_BUS          1
-#define TARGET_SRAM             3
-#define TARGET_PCIE             4
-#define ATTR_DEV_SPI_ROM        0x1e
-#define ATTR_DEV_BOOT           0x1d
-#define ATTR_DEV_NAND           0x2f
-#define ATTR_DEV_CS3            0x37
-#define ATTR_DEV_CS2            0x3b
-#define ATTR_DEV_CS1            0x3d
-#define ATTR_DEV_CS0            0x3e
-#define ATTR_PCIE_IO            0xe0
-#define ATTR_PCIE_MEM           0xe8
-#define ATTR_PCIE1_IO           0xd0
-#define ATTR_PCIE1_MEM          0xd8
-#define ATTR_SRAM               0x01
-/*
- * Description of the windows needed by the platform code
- */
-static struct __initdata orion_addr_map_cfg addr_map_cfg = {
-        .num_wins = 8,
-        .remappable_wins = 4,
-        .bridge_virt_base = BRIDGE_VIRT_BASE,
-};
-static const struct __initdata orion_addr_map_info addr_map_info[] = {
-        /*
-         * Windows for PCIe IO+MEM space.
-         */
-        { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
-          TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
-        },
-        { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
-          TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
-        },
-        { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
-          TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
-        },
-        { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
-          TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
-        },
-        /*
-         * Window for NAND controller.
-         */
-        { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
-          TARGET_DEV_BUS, ATTR_DEV_NAND, -1
-        },
-        /*
-         * Window for SRAM.
-         */
-        { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
-          TARGET_SRAM, ATTR_SRAM, -1
-        },
-        /* End marker */
-        { -1, 0, 0, 0, 0, 0 }
-};
-void __init kirkwood_setup_cpu_mbus(void)
-{
-        /*
-         * Disable, clear and configure windows.
-         */
-        orion_config_wins(&addr_map_cfg, addr_map_info);
-        /*
-         * Setup MBUS dram target info.
-         */
-        orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                    (void __iomem *) DDR_WINDOW_CPU_BASE);
-}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index d367aa6b47bb..f5437c27dc2a 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -93,7 +93,7 @@ static void __init kirkwood_dt_init(void)
         */
        writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
-        kirkwood_setup_cpu_mbus();
+        kirkwood_setup_wins();
        kirkwood_l2_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 49792a0cd2d3..c2cae69e6d2b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -33,7 +33,6 @@
 #include <linux/platform_data/usb-ehci-orion.h>
 #include <plat/common.h>
 #include <plat/time.h>
-#include <plat/addr-map.h>
 #include <linux/platform_data/dma-mv_xor.h>
 #include "common.h"
@@ -535,6 +534,9 @@ void __init kirkwood_init_early(void)
         * the allocations won't fail.
         */
        init_dma_coherent_pool_size(SZ_1M);
+        mvebu_mbus_init("marvell,kirkwood-mbus",
+                        BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
+                        DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
 }
 int kirkwood_tclk;
@@ -650,6 +652,38 @@ char * __init kirkwood_id(void)
        }
 }
+void __init kirkwood_setup_wins(void)
+{
+        /*
+         * The PCIe windows will no longer be statically allocated
+         * here once Kirkwood is migrated to the pci-mvebu driver.
+         */
+        mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                          KIRKWOOD_PCIE_IO_PHYS_BASE,
+                                          KIRKWOOD_PCIE_IO_SIZE,
+                                          KIRKWOOD_PCIE_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                          KIRKWOOD_PCIE_MEM_PHYS_BASE,
+                                          KIRKWOOD_PCIE_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          KIRKWOOD_PCIE1_IO_PHYS_BASE,
+                                          KIRKWOOD_PCIE1_IO_SIZE,
+                                          KIRKWOOD_PCIE1_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+                                          KIRKWOOD_PCIE1_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+        mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
+                              KIRKWOOD_NAND_MEM_SIZE);
+        mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
+                              KIRKWOOD_SRAM_SIZE);
+}
 void __init kirkwood_l2_init(void)
 {
 #ifdef CONFIG_CACHE_FEROCEON_L2
@@ -675,7 +709,7 @@ void __init kirkwood_init(void)
         */
        writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
-        kirkwood_setup_cpu_mbus();
+        kirkwood_setup_wins();
        kirkwood_l2_init();
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 5ed70565c843..e24f74305b34 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -30,7 +30,7 @@ void kirkwood_init(void);
 void kirkwood_init_early(void);
 void kirkwood_init_irq(void);
-void kirkwood_setup_cpu_mbus(void);
+void kirkwood_setup_wins(void);
 void kirkwood_enable_pcie(void);
 void kirkwood_pcie_id(u32 *dev, u32 *rev);
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a05563a31c95..92976cef3910 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -60,8 +60,9 @@
 * Register Map
 */
 #define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
-#define DDR_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
+#define DDR_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
-#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE + 0x1500)
+#define  DDR_WINDOW_CPU_BASE    (DDR_PHYS_BASE + 0x1500)
+#define  DDR_WINDOW_CPU_SZ      (0x20)
 #define DDR_OPERATION_BASE      (DDR_PHYS_BASE + 0x1418)
 #define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
@@ -80,6 +81,8 @@
 #define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
 #define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
+#define  BRIDGE_WINS_BASE       (BRIDGE_PHYS_BASE)
+#define  BRIDGE_WINS_SZ         (0x80)
 #define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index d96ad4c09972..7f43e6c2f8c0 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -17,7 +17,6 @@
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
 #include <mach/bridge-regs.h>
-#include <plat/addr-map.h>
 #include "common.h"
 static void kirkwood_enable_pcie_clk(const char *port)
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index d1e2d595e79c..f62b68d926f4 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -9,6 +9,7 @@
 */
 #include <linux/init.h>
+#include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
index 67a13f9bfe64..7cd04634d302 100644
--- a/arch/arm/mach-mv78xx0/Makefile
+++ b/arch/arm/mach-mv78xx0/Makefile
@@ -1,4 +1,4 @@
-obj-y                           += common.o addr-map.o mpp.o irq.o pcie.o
+obj-y                           += common.o mpp.o irq.o pcie.o
 obj-$(CONFIG_MACH_DB78X00_BP)   += db78x00-bp-setup.o
 obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o
 obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
deleted file mode 100644
index 26e9876b50e9..000000000000
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/addr-map.c
- *
- * Address map functions for Marvell MV78xx0 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mbus.h>
-#include <linux/io.h>
-#include <plat/addr-map.h>
-#include <mach/mv78xx0.h>
-#include "common.h"
-/*
- * Generic Address Decode Windows bit settings
- */
-#define TARGET_DEV_BUS          1
-#define TARGET_PCIE0            4
-#define TARGET_PCIE1            8
-#define TARGET_PCIE(i)          ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
-#define ATTR_DEV_SPI_ROM        0x1f
-#define ATTR_DEV_BOOT           0x2f
-#define ATTR_DEV_CS3            0x37
-#define ATTR_DEV_CS2            0x3b
-#define ATTR_DEV_CS1            0x3d
-#define ATTR_DEV_CS0            0x3e
-#define ATTR_PCIE_IO(l)         (0xf0 & ~(0x10 << (l)))
-#define ATTR_PCIE_MEM(l)        (0xf8 & ~(0x10 << (l)))
-/*
- * CPU Address Decode Windows registers
- */
-#define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
-#define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
-static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
-{
-        /*
-         * Find the control register base address for this window.
-         *
-         * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
-         * MBUS bridge depending on which CPU core we're running on,
-         * so we don't need to take that into account here.
-         */
-        return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
-}
-/*
- * Description of the windows needed by the platform code
- */
-static struct orion_addr_map_cfg addr_map_cfg __initdata = {
-        .num_wins = 14,
-        .remappable_wins = 8,
-        .win_cfg_base = win_cfg_base,
-};
-void __init mv78xx0_setup_cpu_mbus(void)
-{
-        /*
-         * Disable, clear and configure windows.
-         */
-        orion_config_wins(&addr_map_cfg, NULL);
-        /*
-         * Setup MBUS dram target info.
-         */
-        if (mv78xx0_core_index() == 0)
-                orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                            (void __iomem *) DDR_WINDOW_CPU0_BASE);
-        else
-                orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                            (void __iomem *) DDR_WINDOW_CPU1_BASE);
-}
-void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
-                                      int maj, int min)
-{
-        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
-                            TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
-}
-void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
-                                       int maj, int min)
-{
-        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
-                            TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
-}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 0efa14498ebc..749a7f8c4992 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -334,6 +334,14 @@ void __init mv78xx0_uart3_init(void)
 void __init mv78xx0_init_early(void)
 {
        orion_time_set_base(TIMER_VIRT_BASE);
+        if (mv78xx0_core_index() == 0)
+                mvebu_mbus_init("marvell,mv78xx0-mbus",
+                                BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
+                                DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
+        else
+                mvebu_mbus_init("marvell,mv78xx0-mbus",
+                                BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
+                                DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
 }
 void __init_refok mv78xx0_timer_init(void)
@@ -397,8 +405,6 @@ void __init mv78xx0_init(void)
        printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
        printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
-        mv78xx0_setup_cpu_mbus();
 #ifdef CONFIG_CACHE_FEROCEON_L2
        feroceon_l2_init(is_l2_writethrough());
 #endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 46200a183cf2..723748d8ba7d 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -60,13 +60,18 @@
 */
 #define BRIDGE_VIRT_BASE        (MV78XX0_CORE_REGS_VIRT_BASE)
 #define BRIDGE_PHYS_BASE        (MV78XX0_CORE_REGS_PHYS_BASE)
+#define  BRIDGE_WINS_CPU0_BASE  (MV78XX0_CORE0_REGS_PHYS_BASE)
+#define  BRIDGE_WINS_CPU1_BASE  (MV78XX0_CORE1_REGS_PHYS_BASE)
+#define  BRIDGE_WINS_SZ         (0xA000)
 /*
 * Register Map
 */
 #define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE + 0x00000)
-#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE + 0x1500)
+#define DDR_PHYS_BASE           (MV78XX0_REGS_PHYS_BASE + 0x00000)
-#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE + 0x1570)
+#define  DDR_WINDOW_CPU0_BASE   (DDR_PHYS_BASE + 0x1500)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_PHYS_BASE + 0x1570)
+#define  DDR_WINDOW_CPU_SZ      (0x20)
 #define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE + 0x10000)
 #define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x10000)
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index ee8c0b51df2c..dc26a654c496 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -10,11 +10,11 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
-#include <plat/addr-map.h>
 #include <mach/mv78xx0.h>
 #include "common.h"
@@ -54,7 +54,6 @@ static void __init mv78xx0_pcie_preinit(void)
        int i;
        u32 size_each;
        u32 start;
-        int win = 0;
        pcie_io_space.name = "PCIe I/O Space";
        pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
@@ -72,6 +71,7 @@ static void __init mv78xx0_pcie_preinit(void)
        start = MV78XX0_PCIE_MEM_PHYS_BASE;
        for (i = 0; i < num_pcie_ports; i++) {
                struct pcie_port *pp = pcie_port + i;
+                char winname[MVEBU_MBUS_MAX_WINNAME_SZ];
                snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                        "PCIe %d.%d MEM", pp->maj, pp->min);
@@ -85,12 +85,17 @@ static void __init mv78xx0_pcie_preinit(void)
                if (request_resource(&iomem_resource, &pp->res))
                        panic("can't allocate PCIe MEM sub-space");
-                mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start,
+                snprintf(winname, sizeof(winname), "pcie%d.%d",
-                                           resource_size(&pp->res),
+                         pp->maj, pp->min);
-                                           pp->maj, pp->min);
+                mvebu_mbus_add_window_remap_flags(winname,
-                mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K,
+                                                  pp->res.start,
-                                          pp->maj, pp->min);
+                                                  resource_size(&pp->res),
+                                                  MVEBU_MBUS_NO_REMAP,
+                                                  MVEBU_MBUS_PCI_MEM);
+                mvebu_mbus_add_window_remap_flags(winname,
+                                                  i * SZ_64K, SZ_64K,
+                                                  0, MVEBU_MBUS_PCI_IO);
        }
 }
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 440b13ef1fed..e11acbb0a46d 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -13,6 +13,8 @@ config ARCH_MVEBU
        select MVEBU_CLK_CORE
        select MVEBU_CLK_CPU
        select MVEBU_CLK_GATING
+        select MVEBU_MBUS
+        select ZONE_DMA if ARM_LPAE
 if ARCH_MVEBU
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index da93bcbc74c1..ba769e082ad4 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -5,6 +5,6 @@ AFLAGS_coherency_ll.o		:= -Wa,-march=armv7-a
 obj-y                            += system-controller.o
 obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
-obj-$(CONFIG_ARCH_MVEBU)         += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o 
+obj-$(CONFIG_ARCH_MVEBU)         += coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
deleted file mode 100644
index ab9b3bd4fef5..000000000000
--- a/arch/arm/mach-mvebu/addr-map.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Address map functions for Marvell 370 / XP SoCs
- *
- * Copyright (C) 2012 Marvell
- *
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mbus.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <plat/addr-map.h>
-/*
- * Generic Address Decode Windows bit settings
- */
-#define ARMADA_XP_TARGET_DEV_BUS        1
-#define   ARMADA_XP_ATTR_DEV_BOOTROM    0x1D
-#define ARMADA_XP_TARGET_ETH1           3
-#define ARMADA_XP_TARGET_PCIE_0_2       4
-#define ARMADA_XP_TARGET_ETH0           7
-#define ARMADA_XP_TARGET_PCIE_1_3       8
-#define ARMADA_370_TARGET_DEV_BUS       1
-#define   ARMADA_370_ATTR_DEV_BOOTROM   0x1D
-#define ARMADA_370_TARGET_PCIE_0        4
-#define ARMADA_370_TARGET_PCIE_1        8
-#define ARMADA_WINDOW_8_PLUS_OFFSET       0x90
-#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
-static const struct __initdata orion_addr_map_info
-armada_xp_addr_map_info[] = {
-        /*
-         * Window for the BootROM, needed for SMP on Armada XP
-         */
-        { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
-          ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
-        /* End marker */
-        { -1, 0, 0, 0, 0, 0 },
-};
-static const struct __initdata orion_addr_map_info
-armada_370_addr_map_info[] = {
-        /* End marker */
-        { -1, 0, 0, 0, 0, 0 },
-};
-static struct of_device_id of_addr_decoding_controller_table[] = {
-        { .compatible = "marvell,armada-addr-decoding-controller" },
-        { /* end of list */ },
-};
-static void __iomem *
-armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
-{
-        unsigned int offset;
-        /* The register layout is a bit annoying and the below code
-         * tries to cope with it.
-         * - At offset 0x0, there are the registers for the first 8
-         *   windows, with 4 registers of 32 bits per window (ctrl,
-         *   base, remap low, remap high)
-         * - Then at offset 0x80, there is a hole of 0x10 bytes for
-         *   the internal registers base address and internal units
-         *   sync barrier register.
-         * - Then at offset 0x90, there the registers for 12
-         *   windows, with only 2 registers of 32 bits per window
-         *   (ctrl, base).
-         */
-        if (win < 8)
-                offset = (win << 4);
-        else
-                offset = ARMADA_WINDOW_8_PLUS_OFFSET + ((win - 8) << 3);
-        return cfg->bridge_virt_base + offset;
-}
-static struct __initdata orion_addr_map_cfg addr_map_cfg = {
-        .num_wins = 20,
-        .remappable_wins = 8,
-        .win_cfg_base = armada_cfg_base,
-};
-static int __init armada_setup_cpu_mbus(void)
-{
-        struct device_node *np;
-        void __iomem *mbus_unit_addr_decoding_base;
-        void __iomem *sdram_addr_decoding_base;
-        np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
-        if (!np)
-                return -ENODEV;
-        mbus_unit_addr_decoding_base = of_iomap(np, 0);
-        BUG_ON(!mbus_unit_addr_decoding_base);
-        sdram_addr_decoding_base =
-                mbus_unit_addr_decoding_base +
-                ARMADA_SDRAM_ADDR_DECODING_OFFSET;
-        addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
-        if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
-                addr_map_cfg.hw_io_coherency = 1;
-        /*
-         * Disable, clear and configure windows.
-         */
-        if (of_machine_is_compatible("marvell,armadaxp"))
-                orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
-        else if (of_machine_is_compatible("marvell,armada370"))
-                orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
-        else {
-                pr_err("Unsupported SoC\n");
-                return -EINVAL;
-        }
-        /*
-         * Setup MBUS dram target info.
-         */
-        orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                    sdram_addr_decoding_base);
-        return 0;
-}
-/* Using a early_initcall is needed so that this initialization gets
- * done before the SMP initialization, which requires the BootROM to
- * be remapped. */
-early_initcall(armada_setup_cpu_mbus);
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index a5ea616d6d12..12d3655830d1 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -19,6 +19,7 @@
 #include <linux/time-armada-370-xp.h>
 #include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
+#include <linux/mbus.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -48,12 +49,29 @@ void __init armada_370_xp_timer_and_clk_init(void)
 void __init armada_370_xp_init_early(void)
 {
+        char *mbus_soc_name;
        /*
         * Some Armada 370/XP devices allocate their coherent buffers
         * from atomic context. Increase size of atomic coherent pool
         * to make sure such the allocations won't fail.
         */
        init_dma_coherent_pool_size(SZ_1M);
+        /*
+         * This initialization will be replaced by a DT-based
+         * initialization once the mvebu-mbus driver gains DT support.
+         */
+        if (of_machine_is_compatible("marvell,armada370"))
+                mbus_soc_name = "marvell,armada370-mbus";
+        else
+                mbus_soc_name = "marvell,armadaxp-mbus";
+        mvebu_mbus_init(mbus_soc_name,
+                        ARMADA_370_XP_MBUS_WINS_BASE,
+                        ARMADA_370_XP_MBUS_WINS_SIZE,
+                        ARMADA_370_XP_SDRAM_WINS_BASE,
+                        ARMADA_370_XP_SDRAM_WINS_SIZE);
 }
 static void __init armada_370_xp_dt_init(void)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index c6a7d74fddfe..2070e1b4f342 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,9 +16,15 @@
 #define __MACH_ARMADA_370_XP_H
 #define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE    IOMEM(0xfeb00000)
+#define ARMADA_370_XP_REGS_VIRT_BASE    IOMEM(0xfec00000)
 #define ARMADA_370_XP_REGS_SIZE         SZ_1M
+/* These defines can go away once mvebu-mbus has a DT binding */
+#define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
+#define ARMADA_370_XP_MBUS_WINS_SIZE    0x100
+#define ARMADA_370_XP_SDRAM_WINS_BASE   (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180)
+#define ARMADA_370_XP_SDRAM_WINS_SIZE   0x20
 #ifdef CONFIG_SMP
 #include <linux/cpumask.h>
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index fe16aaf7c19c..875ea748391c 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -21,6 +21,7 @@
 #include <linux/smp.h>
 #include <linux/clk.h>
 #include <linux/of.h>
+#include <linux/mbus.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include "common.h"
@@ -109,6 +110,7 @@ void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
        set_secondary_cpus_clock();
        flush_cache_all();
        set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
+        mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
 }
 struct smp_operations armada_xp_smp_ops __initdata = {
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
index 8fb23af154b3..e26eeba46598 100644
--- a/arch/arm/mach-mxs/icoll.c
+++ b/arch/arm/mach-mxs/icoll.c
@@ -100,7 +100,7 @@ static struct irq_domain_ops icoll_irq_domain_ops = {
        .xlate = irq_domain_xlate_onecell,
 };
-void __init icoll_of_init(struct device_node *np,
+static void __init icoll_of_init(struct device_node *np,
                          struct device_node *interrupt_parent)
 {
        /*
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 052186713347..3218f1f2c0e0 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -402,17 +402,17 @@ static void __init cfa10049_init(void)
 {
        enable_clk_enet_out();
        update_fec_mac_prop(OUI_CRYSTALFONTZ);
+        mxsfb_pdata.mode_list = cfa10049_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes);
+        mxsfb_pdata.default_bpp = 32;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
 }
 static void __init cfa10037_init(void)
 {
        enable_clk_enet_out();
        update_fec_mac_prop(OUI_CRYSTALFONTZ);
-        mxsfb_pdata.mode_list = cfa10049_video_modes;
-        mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes);
-        mxsfb_pdata.default_bpp = 32;
-        mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
 }
 static void __init apf28_init(void)
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index a4294aa9f301..e63b7d87acbd 100644
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -18,6 +18,7 @@
 #include <mach/mx23.h>
 #include <mach/mx28.h>
+#include <mach/common.h>
 /*
 * Define the MX23 memory map.
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
index 54add60f94c9..1dff46703753 100644
--- a/arch/arm/mach-mxs/ocotp.c
+++ b/arch/arm/mach-mxs/ocotp.c
@@ -19,6 +19,7 @@
 #include <asm/processor.h>      /* for cpu_relax() */
 #include <mach/mxs.h>
+#include <mach/common.h>
 #define OCOTP_WORD_OFFSET               0x20
 #define OCOTP_WORD_COUNT                0x20
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index fb18831e88aa..14f7e9920479 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -31,6 +31,8 @@
 #include <plat/i2c.h>
+#include <mach/irqs.h>
 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 void omap7xx_map_io(void);
 #else
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 49ac3dfebef9..8111cd9ff3e5 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -311,9 +311,6 @@ config MACH_OMAP_ZOOM2
        default y
        select OMAP_PACKAGE_CBB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select SERIAL_8250
-        select SERIAL_8250_CONSOLE
-        select SERIAL_CORE_CONSOLE
 config MACH_OMAP_ZOOM3
        bool "OMAP3630 Zoom3 board"
@@ -321,9 +318,6 @@ config MACH_OMAP_ZOOM3
        default y
        select OMAP_PACKAGE_CBP
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select SERIAL_8250
-        select SERIAL_8250_CONSOLE
-        select SERIAL_CORE_CONSOLE
 config MACH_CM_T35
        bool "CompuLab CM-T35/CM-T3730 modules"
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 0274ff7a2a2b..e54a48060198 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -102,6 +102,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
        .init_irq       = omap_intc_of_init,
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_generic_init,
+        .init_late      = omap3_init_late,
        .init_time      = omap3_sync32k_timer_init,
        .dt_compat      = omap3_boards_compat,
        .restart        = omap3xxx_restart,
@@ -119,6 +120,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
        .init_irq       = omap_intc_of_init,
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_generic_init,
+        .init_late      = omap3_init_late,
        .init_time      = omap3_secure_sync32k_timer_init,
        .dt_compat      = omap3_gp_boards_compat,
        .restart        = omap3xxx_restart,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index f7c4616cbb60..d2ea68ea678a 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/usb/phy.h>
 #include <linux/usb/musb.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
@@ -98,6 +99,7 @@ static void __init rx51_init(void)
        sdrc_params = nokia_get_sdram_timings();
        omap_sdrc_init(sdrc_params, sdrc_params);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(&musb_board_data);
        rx51_peripherals_init();
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 0a6b9c7a63da..40f4a03d728f 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -108,7 +108,6 @@ void omap35xx_init_late(void);
 void omap3630_init_late(void);
 void am35xx_init_late(void);
 void ti81xx_init_late(void);
-void omap4430_init_late(void);
 int omap2_common_pm_late_init(void);
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index e4b16c8efe8b..410e1bac7815 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1122,9 +1122,6 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
        /* TODO: remove, see function definition */
        gpmc_convert_ps_to_ns(gpmc_t);
-        /* Now the GPMC is initialised, unreserve the chip-selects */
-        gpmc_cs_map = 0;
        return 0;
 }
@@ -1383,6 +1380,9 @@ static int gpmc_probe(struct platform_device *pdev)
        if (IS_ERR_VALUE(gpmc_setup_irq()))
                dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
+        /* Now the GPMC is initialised, unreserve the chip-selects */
+        gpmc_cs_map = 0;
        rc = gpmc_probe_dt(pdev);
        if (rc < 0) {
                clk_disable_unprepare(gpmc_l3_clk);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 6a217c98db54..f82cf878d6af 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -211,8 +211,6 @@ static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
                return -EINVAL;
        }
-        pr_err("%s: Could not find signal %s\n", __func__, muxname);
        return -ENODEV;
 }
@@ -234,6 +232,8 @@ int __init omap_mux_get_by_name(const char *muxname,
                return mux_mode;
        }
+        pr_err("%s: Could not find signal %s\n", __func__, muxname);
        return -ENODEV;
 }
@@ -739,8 +739,9 @@ static void __init omap_mux_dbg_create_entry(
        list_for_each_entry(e, &partition->muxmodes, node) {
                struct omap_mux *m = &e->mux;
-                (void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir,
+                (void)debugfs_create_file(m->muxnames[0], S_IWUSR | S_IRUGO,
-                                          m, &omap_mux_dbg_signal_fops);
+                                          mux_dbg_dir, m,
+                                          &omap_mux_dbg_signal_fops);
        }
 }
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 9e809a7c05c0..45da805fb236 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -1,4 +1,4 @@
-obj-y                           += common.o addr-map.o pci.o irq.o mpp.o
+obj-y                           += common.o pci.o irq.o mpp.o
 obj-$(CONFIG_MACH_DB88F5281)    += db88f5281-setup.o
 obj-$(CONFIG_MACH_RD88F5182)    += rd88f5182-setup.o
 obj-$(CONFIG_MACH_KUROBOX_PRO)  += kurobox_pro-setup.o
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
deleted file mode 100644
index b5efc0fd31cb..000000000000
--- a/arch/arm/mach-orion5x/addr-map.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * arch/arm/mach-orion5x/addr-map.c
- *
- * Address map functions for Marvell Orion 5x SoCs
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mbus.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <plat/addr-map.h>
-#include "common.h"
-/*
- * The Orion has fully programmable address map. There's a separate address
- * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB,
- * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
- * address decode windows that allow it to access any of the Orion resources.
- *
- * CPU address decoding --
- * Linux assumes that it is the boot loader that already setup the access to
- * DDR and internal registers.
- * Setup access to PCI and PCIe IO/MEM space is issued by this file.
- * Setup access to various devices located on the device bus interface (e.g.
- * flashes, RTC, etc) should be issued by machine-setup.c according to
- * specific board population (by using orion5x_setup_*_win()).
- *
- * Non-CPU Masters address decoding --
- * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
- * banks only (the typical use case).
- * Setup access for each master to DDR is issued by platform device setup.
- */
-/*
- * Generic Address Decode Windows bit settings
- */
-#define TARGET_DEV_BUS          1
-#define TARGET_PCI              3
-#define TARGET_PCIE             4
-#define TARGET_SRAM             9
-#define ATTR_PCIE_MEM           0x59
-#define ATTR_PCIE_IO            0x51
-#define ATTR_PCIE_WA            0x79
-#define ATTR_PCI_MEM            0x59
-#define ATTR_PCI_IO             0x51
-#define ATTR_DEV_CS0            0x1e
-#define ATTR_DEV_CS1            0x1d
-#define ATTR_DEV_CS2            0x1b
-#define ATTR_DEV_BOOT           0xf
-#define ATTR_SRAM               0x0
-static int __initdata win_alloc_count;
-static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
-                  const int win)
-{
-        u32 dev, rev;
-        orion5x_pcie_id(&dev, &rev);
-        if ((dev == MV88F5281_DEV_ID && win < 4)
-            || (dev == MV88F5182_DEV_ID && win < 2)
-            || (dev == MV88F5181_DEV_ID && win < 2)
-            || (dev == MV88F6183_DEV_ID && win < 4))
-                return 1;
-        return 0;
-}
-/*
- * Description of the windows needed by the platform code
- */
-static struct orion_addr_map_cfg addr_map_cfg __initdata = {
-        .num_wins = 8,
-        .cpu_win_can_remap = cpu_win_can_remap,
-        .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
-};
-static const struct __initdata orion_addr_map_info addr_map_info[] = {
-        /*
-         * Setup windows for PCI+PCIe IO+MEM space.
-         */
-        { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
-          TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE
-        },
-        { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
-          TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE
-        },
-        { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
-          TARGET_PCIE, ATTR_PCIE_MEM, -1
-        },
-        { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
-          TARGET_PCI, ATTR_PCI_MEM, -1
-        },
-        /* End marker */
-        { -1, 0, 0, 0, 0, 0 }
-};
-void __init orion5x_setup_cpu_mbus_bridge(void)
-{
-        /*
-         * Disable, clear and configure windows.
-         */
-        orion_config_wins(&addr_map_cfg, addr_map_info);
-        win_alloc_count = 4;
-        /*
-         * Setup MBUS dram target info.
-         */
-        orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                    (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
-}
-void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
-{
-        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                            TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
-}
-void __init orion5x_setup_dev0_win(u32 base, u32 size)
-{
-        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                            TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
-}
-void __init orion5x_setup_dev1_win(u32 base, u32 size)
-{
-        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                            TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
-}
-void __init orion5x_setup_dev2_win(u32 base, u32 size)
-{
-        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                            TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
-}
-void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
-{
-        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                            TARGET_PCIE, ATTR_PCIE_WA, -1);
-}
-void __init orion5x_setup_sram_win(void)
-{
-        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
-                            ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
-                            TARGET_SRAM, ATTR_SRAM, -1);
-}
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index 35a8014529ca..6bbc8786c1e3 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -41,7 +41,7 @@ static void __init orion5x_dt_init(void)
        /*
         * Setup Orion address map
         */
-        orion5x_setup_cpu_mbus_bridge();
+        orion5x_setup_wins();
        /* Setup root of clk tree */
        clk_init();
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index d068f1431c40..8e468e3a6015 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -34,7 +34,6 @@
 #include <linux/platform_data/usb-ehci-orion.h>
 #include <plat/time.h>
 #include <plat/common.h>
-#include <plat/addr-map.h>
 #include "common.h"
 /*****************************************************************************
@@ -174,7 +173,8 @@ void __init orion5x_xor_init(void)
 ****************************************************************************/
 static void __init orion5x_crypto_init(void)
 {
-        orion5x_setup_sram_win();
+        mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
+                              ORION5X_SRAM_SIZE);
        orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
                          SZ_8K, IRQ_ORION5X_CESA);
 }
@@ -193,6 +193,9 @@ void __init orion5x_wdt_init(void)
 ****************************************************************************/
 void __init orion5x_init_early(void)
 {
+        u32 rev, dev;
+        const char *mbus_soc_name;
        orion_time_set_base(TIMER_VIRT_BASE);
        /*
@@ -201,6 +204,46 @@ void __init orion5x_init_early(void)
         * the allocations won't fail.
         */
        init_dma_coherent_pool_size(SZ_1M);
+        /* Initialize the MBUS driver */
+        orion5x_pcie_id(&dev, &rev);
+        if (dev == MV88F5281_DEV_ID)
+                mbus_soc_name = "marvell,orion5x-88f5281-mbus";
+        else if (dev == MV88F5182_DEV_ID)
+                mbus_soc_name = "marvell,orion5x-88f5182-mbus";
+        else if (dev == MV88F5181_DEV_ID)
+                mbus_soc_name = "marvell,orion5x-88f5181-mbus";
+        else if (dev == MV88F6183_DEV_ID)
+                mbus_soc_name = "marvell,orion5x-88f6183-mbus";
+        else
+                mbus_soc_name = NULL;
+        mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
+                        ORION5X_BRIDGE_WINS_SZ,
+                        ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
+}
+void orion5x_setup_wins(void)
+{
+        /*
+         * The PCIe windows will no longer be statically allocated
+         * here once Orion5x is migrated to the pci-mvebu driver.
+         */
+        mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
+                                          ORION5X_PCIE_IO_SIZE,
+                                          ORION5X_PCIE_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
+                                          ORION5X_PCIE_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+        mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
+                                          ORION5X_PCI_IO_SIZE,
+                                          ORION5X_PCI_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
+                                          ORION5X_PCI_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
 }
 int orion5x_tclk;
@@ -282,7 +325,7 @@ void __init orion5x_init(void)
        /*
         * Setup Orion address map
         */
-        orion5x_setup_cpu_mbus_bridge();
+        orion5x_setup_wins();
        /* Setup root of clk tree */
        clk_init();
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index e60345760283..cdaa01f3d186 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -17,18 +17,7 @@ void clk_init(void);
 extern int orion5x_tclk;
 extern void orion5x_timer_init(void);
-/*
+void orion5x_setup_wins(void);
- * Enumerations and functions for Orion windows mapping. Used by Orion core
- * functions to map its interfaces and by the machine-setup to map its on-
- * board devices. Details in /mach-orion/addr-map.c
- */
-void orion5x_setup_cpu_mbus_bridge(void);
-void orion5x_setup_dev_boot_win(u32 base, u32 size);
-void orion5x_setup_dev0_win(u32 base, u32 size);
-void orion5x_setup_dev1_win(u32 base, u32 size);
-void orion5x_setup_dev2_win(u32 base, u32 size);
-void orion5x_setup_pcie_wa_win(u32 base, u32 size);
-void orion5x_setup_sram_win(void);
 void orion5x_ehci0_init(void);
 void orion5x_ehci1_init(void);
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 57d0af74874d..16c88bbabc98 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -317,8 +317,8 @@ static void __init d2net_init(void)
        d2net_sata_power_init();
        orion5x_sata_init(&d2net_sata_data);
-        orion5x_setup_dev_boot_win(D2NET_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE,
-                                D2NET_NOR_BOOT_SIZE);
+                              D2NET_NOR_BOOT_SIZE);
        platform_device_register(&d2net_nor_flash);
        platform_device_register(&d2net_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 76665640087b..4e1263da38bb 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -340,16 +340,19 @@ static void __init db88f5281_init(void)
        orion5x_uart0_init();
        orion5x_uart1_init();
-        orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE,
-                                DB88F5281_NOR_BOOT_SIZE);
+                              DB88F5281_NOR_BOOT_SIZE);
        platform_device_register(&db88f5281_boot_flash);
-        orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
+        mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE,
+                              DB88F5281_7SEG_SIZE);
-        orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
+        mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE,
+                              DB88F5281_NOR_SIZE);
        platform_device_register(&db88f5281_nor_flash);
-        orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
+        mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE,
+                              DB88F5281_NAND_SIZE);
        platform_device_register(&db88f5281_nand_flash);
        i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 6eb1732757fd..9e6baf581ed3 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -611,7 +611,8 @@ static void __init dns323_init(void)
        /* setup flash mapping
         * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
         */
-        orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE,
+                              DNS323_NOR_BOOT_SIZE);
        platform_device_register(&dns323_nor_flash);
        /* Sort out LEDs, Buttons and i2c devices */
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index d675e727803d..147615510dd0 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -154,8 +154,8 @@ void __init edmini_v2_init(void)
        orion5x_ehci0_init();
        orion5x_eth_init(&edmini_v2_eth_data);
-        orion5x_setup_dev_boot_win(EDMINI_V2_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
-                                EDMINI_V2_NOR_BOOT_SIZE);
+                              EDMINI_V2_NOR_BOOT_SIZE);
        platform_device_register(&edmini_v2_nor_flash);
        pr_notice("edmini_v2: USB device port, flash write and power-off "
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index d265f5484a8e..b78ff3248868 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -66,8 +66,10 @@
 * Orion Registers Map
 ******************************************************************************/
+#define ORION5X_DDR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x00000)
+#define  ORION5X_DDR_WINS_BASE          (ORION5X_DDR_PHYS_BASE + 0x1500)
+#define  ORION5X_DDR_WINS_SZ            (0x10)
 #define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x00000)
-#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE + 0x1500)
 #define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE + 0x10000)
 #define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE + 0x10000)
 #define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE + (x))
@@ -81,6 +83,8 @@
 #define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE + 0x20000)
 #define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x20000)
+#define  ORION5X_BRIDGE_WINS_BASE       (ORION5X_BRIDGE_PHYS_BASE)
+#define  ORION5X_BRIDGE_WINS_SZ         (0x80)
 #define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x30000)
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index b98403526218..aae10e4a917c 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -359,13 +359,13 @@ static void __init kurobox_pro_init(void)
        orion5x_uart1_init();
        orion5x_xor_init();
-        orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE,
-                                   KUROBOX_PRO_NOR_BOOT_SIZE);
+                              KUROBOX_PRO_NOR_BOOT_SIZE);
        platform_device_register(&kurobox_pro_nor_flash);
        if (machine_is_kurobox_pro()) {
-                orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE,
+                mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE,
-                                       KUROBOX_PRO_NAND_SIZE);
+                                      KUROBOX_PRO_NAND_SIZE);
                platform_device_register(&kurobox_pro_nand_flash);
        }
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 044da5b6a6ae..24f4e14e5893 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -294,8 +294,8 @@ static void __init lschl_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
-        orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE,
-                                   LSCHL_NOR_BOOT_SIZE);
+                              LSCHL_NOR_BOOT_SIZE);
        platform_device_register(&lschl_nor_flash);
        platform_device_register(&lschl_leds);
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index d49f93423f52..fc653bb41e78 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -243,8 +243,8 @@ static void __init ls_hgl_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
-        orion5x_setup_dev_boot_win(LS_HGL_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE,
-                                   LS_HGL_NOR_BOOT_SIZE);
+                              LS_HGL_NOR_BOOT_SIZE);
        platform_device_register(&ls_hgl_nor_flash);
        platform_device_register(&ls_hgl_button_device);
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 8e3965c6c0fe..18e66e617dc2 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -244,8 +244,8 @@ static void __init lsmini_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
-        orion5x_setup_dev_boot_win(LSMINI_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE,
-                                   LSMINI_NOR_BOOT_SIZE);
+                              LSMINI_NOR_BOOT_SIZE);
        platform_device_register(&lsmini_nor_flash);
        platform_device_register(&lsmini_button_device);
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 0ec94a1f2b16..827acbafc9dc 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -241,7 +241,8 @@ static void __init mss2_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
-        orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE,
+                              MSS2_NOR_BOOT_SIZE);
        platform_device_register(&mss2_nor_flash);
        platform_device_register(&mss2_button_device);
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 18143f2a9093..92600ae2b4b6 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -204,7 +204,8 @@ static void __init mv2120_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
-        orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE,
+                              MV2120_NOR_BOOT_SIZE);
        platform_device_register(&mv2120_nor_flash);
        platform_device_register(&mv2120_button_device);
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 282e503b003e..dd0641a0d074 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -397,8 +397,8 @@ static void __init net2big_init(void)
        net2big_sata_power_init();
        orion5x_sata_init(&net2big_sata_data);
-        orion5x_setup_dev_boot_win(NET2BIG_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE,
-                                   NET2BIG_NOR_BOOT_SIZE);
+                              NET2BIG_NOR_BOOT_SIZE);
        platform_device_register(&net2big_nor_flash);
        platform_device_register(&net2big_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index d9c7c3bf0d9c..503368023bb1 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -157,8 +157,11 @@ static int __init pcie_setup(struct pci_sys_data *sys)
        if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
                printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
                                   "read transaction workaround\n");
-                orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          ORION5X_PCIE_WA_SIZE);
+                                                  ORION5X_PCIE_WA_PHYS_BASE,
+                                                  ORION5X_PCIE_WA_SIZE,
+                                                  MVEBU_MBUS_NO_REMAP,
+                                                  MVEBU_MBUS_PCI_WA);
                pcie_ops.read = pcie_rd_conf_wa;
        }
@@ -402,8 +405,9 @@ static void __init orion5x_pci_master_slave_enable(void)
        orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
 }
-static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
+static void __init orion5x_setup_pci_wins(void)
 {
+        const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
        u32 win_enable;
        int bus;
        int i;
@@ -420,7 +424,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
        bus = orion5x_pci_local_bus_nr();
        for (i = 0; i < dram->num_cs; i++) {
-                struct mbus_dram_window *cs = dram->cs + i;
+                const struct mbus_dram_window *cs = dram->cs + i;
                u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
                u32 reg;
                u32 val;
@@ -467,7 +471,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
        /*
         * Point PCI unit MBUS decode windows to DRAM space.
         */
-        orion5x_setup_pci_wins(&orion_mbus_dram_info);
+        orion5x_setup_pci_wins();
        /*
         * Master + Slave enable
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index d6e72f672afb..1c4498bf650a 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -123,8 +123,8 @@ static void __init rd88f5181l_fxo_init(void)
        orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
        orion5x_uart0_init();
-        orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE,
-                                   RD88F5181L_FXO_NOR_BOOT_SIZE);
+                              RD88F5181L_FXO_NOR_BOOT_SIZE);
        platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
 }
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index c8b7913310e5..adabe34c4fc6 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -130,8 +130,8 @@ static void __init rd88f5181l_ge_init(void)
        orion5x_i2c_init();
        orion5x_uart0_init();
-        orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE,
-                                   RD88F5181L_GE_NOR_BOOT_SIZE);
+                              RD88F5181L_GE_NOR_BOOT_SIZE);
        platform_device_register(&rd88f5181l_ge_nor_boot_flash);
        i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index f9e156725d7c..66e77ec91532 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -264,10 +264,11 @@ static void __init rd88f5182_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
-        orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE,
-                                   RD88F5182_NOR_BOOT_SIZE);
+                              RD88F5182_NOR_BOOT_SIZE);
-        orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
+        mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE,
+                              RD88F5182_NOR_SIZE);
        platform_device_register(&rd88f5182_nor_flash);
        platform_device_register(&rd88f5182_gpio_leds);
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index acc0877ec1c9..a0bfa53e7556 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -329,8 +329,8 @@ static void __init tsp2_init(void)
        /*
         * Configure peripherals.
         */
-        orion5x_setup_dev_boot_win(TSP2_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE,
-                                   TSP2_NOR_BOOT_SIZE);
+                              TSP2_NOR_BOOT_SIZE);
        platform_device_register(&tsp2_nor_flash);
        orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 9c17f0c2b488..80174f0f168e 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -286,8 +286,8 @@ static void __init qnap_ts209_init(void)
        /*
         * Configure peripherals.
         */
-        orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE,
-                                   QNAP_TS209_NOR_BOOT_SIZE);
+                              QNAP_TS209_NOR_BOOT_SIZE);
        platform_device_register(&qnap_ts209_nor_flash);
        orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 8cc5ab6c503e..92592790d6da 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -277,8 +277,8 @@ static void __init qnap_ts409_init(void)
        /*
         * Configure peripherals.
         */
-        orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE,
-                                   QNAP_TS409_NOR_BOOT_SIZE);
+                              QNAP_TS409_NOR_BOOT_SIZE);
        platform_device_register(&qnap_ts409_nor_flash);
        orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 66552ca7e05d..6b84863c018d 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -127,8 +127,8 @@ static void __init wnr854t_init(void)
        orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
        orion5x_uart0_init();
-        orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE,
-                                   WNR854T_NOR_BOOT_SIZE);
+                              WNR854T_NOR_BOOT_SIZE);
        platform_device_register(&wnr854t_nor_flash);
 }
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 2c5408e2e689..fae684bc54f2 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -213,8 +213,8 @@ static void __init wrt350n_v2_init(void)
        orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
        orion5x_uart0_init();
-        orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
+        mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE,
-                                   WRT350N_V2_NOR_BOOT_SIZE);
+                              WRT350N_V2_NOR_BOOT_SIZE);
        platform_device_register(&wrt350n_v2_nor_flash);
        platform_device_register(&wrt350n_v2_leds);
        platform_device_register(&wrt350n_v2_button_device);
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index af41888acbd6..969b0ba7fa70 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -505,6 +505,7 @@ static struct w1_gpio_platform_data w1_gpio_platform_data = {
        .pin                    = GPIO_ONE_WIRE,
        .is_open_drain          = 0,
        .enable_external_pullup = w1_enable_external_pullup,
+        .ext_pullup_enable_pin  = -EINVAL,
 };
 struct platform_device raumfeld_w1_gpio_device = {
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index fcdf52dbcc49..f051f53e35b7 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -214,11 +214,6 @@ static struct clk clk_pcmcdclk2 = {
        .name           = "pcmcdclk",
 };
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
 static struct clk *clkset_vpllsrc_list[] = {
        [0] = &clk_fin_vpll,
        [1] = &clk_sclk_hdmi27m,
@@ -305,18 +300,6 @@ static struct clk_ops clk_fout_apll_ops = {
 static struct clk init_clocks_off[] = {
        {
-                .name           = "dma",
-                .devname        = "dma-pl330.0",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip0_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "dma",
-                .devname        = "dma-pl330.1",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
                .name           = "rot",
                .parent         = &clk_hclk_dsys.clk,
                .enable         = s5pv210_clk_ip0_ctrl,
@@ -573,6 +556,20 @@ static struct clk clk_hsmmc3 = {
        .ctrlbit        = (1<<19),
 };
+static struct clk clk_pdma0 = {
+        .name           = "pdma0",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip0_ctrl,
+        .ctrlbit        = (1 << 3),
+};
+static struct clk clk_pdma1 = {
+        .name           = "pdma1",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip0_ctrl,
+        .ctrlbit        = (1 << 4),
+};
 static struct clk *clkset_uart_list[] = {
        [6] = &clk_mout_mpll.clk,
        [7] = &clk_mout_epll.clk,
@@ -1075,6 +1072,8 @@ static struct clk *clk_cdev[] = {
        &clk_hsmmc1,
        &clk_hsmmc2,
        &clk_hsmmc3,
+        &clk_pdma0,
+        &clk_pdma1,
 };
 /* Clock initialisation code */
@@ -1333,6 +1332,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
        CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
        CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
+        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
 };
 void __init s5pv210_register_clocks(void)
@@ -1361,6 +1362,5 @@ void __init s5pv210_register_clocks(void)
        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
                s3c_disable_clocks(clk_cdev[ptr], 1);
-        s3c24xx_register_clock(&dummy_apb_pclk);
        s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 3a38f7b34b94..e373de44a8b6 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -845,7 +845,7 @@ static struct fimc_source_info goni_camera_sensors[] = {
                .mux_id         = 0,
                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .bus_type       = FIMC_BUS_TYPE_ITU_601,
+                .fimc_bus_type  = FIMC_BUS_TYPE_ITU_601,
                .board_info     = &noon010pc30_board_info,
                .i2c_bus_num    = 0,
                .clk_frequency  = 16000000UL,
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index cdcb799e802f..fec49ebc359a 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -32,6 +32,7 @@
 #include <linux/smsc911x.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/sh_hspi.h>
+#include <linux/mmc/host.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/usb/otg.h>
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index f9d754f90c59..d2b3937c4014 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -14,7 +14,7 @@
 #define pr_fmt(fmt) "SPEAr3xx: " fmt
 #include <linux/amba/pl022.h>
-#include <linux/amba/pl08x.h>
+#include <linux/amba/pl080.h>
 #include <linux/io.h>
 #include <plat/pl080.h>
 #include <mach/generic.h>
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c7e3759f16d3..e9db6b4bf65a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -342,6 +342,7 @@ static int __init atomic_pool_init(void)
 {
        struct dma_pool *pool = &atomic_pool;
        pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
+        gfp_t gfp = GFP_KERNEL | GFP_DMA;
        unsigned long nr_pages = pool->size >> PAGE_SHIFT;
        unsigned long *bitmap;
        struct page *page;
@@ -361,8 +362,8 @@ static int __init atomic_pool_init(void)
                ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
                                              atomic_pool_init);
        else
-                ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot,
+                ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
-                                           &page, atomic_pool_init);
+                                           atomic_pool_init);
        if (ptr) {
                int i;
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index 6828ef6ce80e..a0bd8a755bdf 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -576,7 +576,7 @@ load_ind:
                        /* x = ((*(frame + k)) & 0xf) << 2; */
                        ctx->seen |= SEEN_X | SEEN_DATA | SEEN_CALL;
                        /* the interpreter should deal with the negative K */
-                        if (k < 0)
+                        if ((int)k < 0)
                                return -1;
                        /* offset in r1: we might have to take the slow path */
                        emit_mov_i(r_off, k, ctx);
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index a82cecb84948..2eca54b65906 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -3,8 +3,6 @@
 #
 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-obj-y                             += addr-map.o
 orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
 obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
 obj-$(CONFIG_PLAT_ORION_LEGACY)   += $(orion-gpio-y)
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
deleted file mode 100644
index 807ac8e5cbc0..000000000000
--- a/arch/arm/plat-orion/addr-map.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * arch/arm/plat-orion/addr-map.c
- *
- * Address map functions for Marvell Orion based SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/mbus.h>
-#include <linux/io.h>
-#include <plat/addr-map.h>
-struct mbus_dram_target_info orion_mbus_dram_info;
-const struct mbus_dram_target_info *mv_mbus_dram_info(void)
-{
-        return &orion_mbus_dram_info;
-}
-EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
-/*
- * DDR target is the same on all Orion platforms.
- */
-#define TARGET_DDR              0
-/*
- * Helpers to get DDR bank info
- */
-#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
-#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
-/*
- * CPU Address Decode Windows registers
- */
-#define WIN_CTRL_OFF            0x0000
-#define WIN_BASE_OFF            0x0004
-#define WIN_REMAP_LO_OFF        0x0008
-#define WIN_REMAP_HI_OFF        0x000c
-#define ATTR_HW_COHERENCY       (0x1 << 4)
-/*
- * Default implementation
- */
-static void __init __iomem *
-orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
-{
-        return cfg->bridge_virt_base + (win << 4);
-}
-/*
- * Default implementation
- */
-static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
-                                          const int win)
-{
-        if (win < cfg->remappable_wins)
-                return 1;
-        return 0;
-}
-void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
-                                const int win, const u32 base,
-                                const u32 size, const u8 target,
-                                const u8 attr, const int remap)
-{
-        void __iomem *addr = cfg->win_cfg_base(cfg, win);
-        u32 ctrl, base_high, remap_addr;
-        if (win >= cfg->num_wins) {
-                printk(KERN_ERR "setup_cpu_win: trying to allocate window "
-                       "%d when only %d allowed\n", win, cfg->num_wins);
-        }
-        base_high = base & 0xffff0000;
-        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
-        writel(base_high, addr + WIN_BASE_OFF);
-        writel(ctrl, addr + WIN_CTRL_OFF);
-        if (cfg->cpu_win_can_remap(cfg, win)) {
-                if (remap < 0)
-                        remap_addr = base;
-                else
-                        remap_addr = remap;
-                writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF);
-                writel(0, addr + WIN_REMAP_HI_OFF);
-        }
-}
-/*
- * Configure a number of windows.
- */
-static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
-                                        const struct orion_addr_map_info *info)
-{
-        while (info->win != -1) {
-                orion_setup_cpu_win(cfg, info->win, info->base, info->size,
-                                    info->target, info->attr, info->remap);
-                info++;
-        }
-}
-static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
-{
-        void __iomem *addr;
-        int i;
-        for (i = 0; i < cfg->num_wins; i++) {
-                addr = cfg->win_cfg_base(cfg, i);
-                writel(0, addr + WIN_BASE_OFF);
-                writel(0, addr + WIN_CTRL_OFF);
-                if (cfg->cpu_win_can_remap(cfg, i)) {
-                        writel(0, addr + WIN_REMAP_LO_OFF);
-                        writel(0, addr + WIN_REMAP_HI_OFF);
-                }
-        }
-}
-/*
- * Disable, clear and configure windows.
- */
-void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
-                              const struct orion_addr_map_info *info)
-{
-        if (!cfg->cpu_win_can_remap)
-                cfg->cpu_win_can_remap = orion_cpu_win_can_remap;
-        if (!cfg->win_cfg_base)
-                cfg->win_cfg_base = orion_win_cfg_base;
-        orion_disable_wins(cfg);
-        if (info)
-                orion_setup_cpu_wins(cfg, info);
-}
-/*
- * Setup MBUS dram target info.
- */
-void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-                                        const void __iomem *ddr_window_cpu_base)
-{
-        int i;
-        int cs;
-        orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
-                u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
-                /*
-                 * We only take care of entries for which the chip
-                 * select is enabled, and that don't have high base
-                 * address bits set (devices can only access the first
-                 * 32 bits of the memory).
-                 */
-                if ((size & 1) && !(base & 0xF)) {
-                        struct mbus_dram_window *w;
-                        w = &orion_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0xf & ~(1 << i);
-                        if (cfg->hw_io_coherency)
-                                w->mbus_attr |= ATTR_HW_COHERENCY;
-                        w->base = base & 0xffff0000;
-                        w->size = (size | 0x0000ffff) + 1;
-                }
-        }
-        orion_mbus_dram_info.num_cs = cs;
-}
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index c29ee7ea200b..e39c2ba6e2fb 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -439,6 +439,64 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
        }
 }
+#ifdef CONFIG_DEBUG_FS
+#include <linux/seq_file.h>
+static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
+        u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
+        int i;
+        out     = readl_relaxed(GPIO_OUT(ochip));
+        io_conf = readl_relaxed(GPIO_IO_CONF(ochip));
+        blink   = readl_relaxed(GPIO_BLINK_EN(ochip));
+        in_pol  = readl_relaxed(GPIO_IN_POL(ochip));
+        data_in = readl_relaxed(GPIO_DATA_IN(ochip));
+        cause   = readl_relaxed(GPIO_EDGE_CAUSE(ochip));
+        edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip));
+        lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip));
+        for (i = 0; i < chip->ngpio; i++) {
+                const char *label;
+                u32 msk;
+                bool is_out;
+                label = gpiochip_is_requested(chip, i);
+                if (!label)
+                        continue;
+                msk = 1 << i;
+                is_out = !(io_conf & msk);
+                seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
+                if (is_out) {
+                        seq_printf(s, " out %s %s\n",
+                                   out & msk ? "hi" : "lo",
+                                   blink & msk ? "(blink )" : "");
+                        continue;
+                }
+                seq_printf(s, " in  %s (act %s) - IRQ",
+                           (data_in ^ in_pol) & msk  ? "hi" : "lo",
+                           in_pol & msk ? "lo" : "hi");
+                if (!((edg_msk | lvl_msk) & msk)) {
+                        seq_printf(s, " disabled\n");
+                        continue;
+                }
+                if (edg_msk & msk)
+                        seq_printf(s, " edge ");
+                if (lvl_msk & msk)
+                        seq_printf(s, " level");
+                seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear  ");
+        }
+}
+#else
+#define orion_gpio_dbg_show NULL
+#endif
 void __init orion_gpio_init(struct device_node *np,
                            int gpio_base, int ngpio,
                            void __iomem *base, int mask_offset,
@@ -471,6 +529,7 @@ void __init orion_gpio_init(struct device_node *np,
 #ifdef CONFIG_OF
        ochip->chip.of_node = np;
 #endif
+        ochip->chip.dbg_show = orion_gpio_dbg_show;
        spin_lock_init(&ochip->lock);
        ochip->base = (void __iomem *)base;
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index f20a321088a2..8b8c06d2e9c4 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base)
 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
 * WIN[0-3] -> DRAM bank[0-3]
 */
-static void __init orion_pcie_setup_wins(void __iomem *base,
+static void __init orion_pcie_setup_wins(void __iomem *base)
-                                         struct mbus_dram_target_info *dram)
 {
+        const struct mbus_dram_target_info *dram;
        u32 size;
        int i;
+        dram = mv_mbus_dram_info();
        /*
         * First, disable and clear BARs and windows.
         */
@@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
         */
        size = 0;
        for (i = 0; i < dram->num_cs; i++) {
-                struct mbus_dram_window *cs = dram->cs + i;
+                const struct mbus_dram_window *cs = dram->cs + i;
                writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
                writel(0, base + PCIE_WIN04_REMAP_OFF(i));
@@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base)
        /*
         * Point PCIe unit MBUS decode windows to DRAM space.
         */
-        orion_pcie_setup_wins(base, &orion_mbus_dram_info);
+        orion_pcie_setup_wins(base);
        /*
         * Master + slave enable.
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 739d016eb273..8a08c31b5e20 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -10,7 +10,7 @@ choice
 config ARCH_SPEAR13XX
        bool "ST SPEAr13xx with Device Tree"
-        select ARCH_HAVE_CPUFREQ
+        select ARCH_HAS_CPUFREQ
        select ARM_GIC
        select CPU_V7
        select GPIO_SPEAR_SPICS
author	Jason Cooper <jason@lakedaemon.net>	2013-04-15 10:55:23 -0400
committer	Jason Cooper <jason@lakedaemon.net>	2013-04-15 10:55:23 -0400
commit	b757f17e9184b65428c48a281d82f9acb3e96f0e (patch)
tree	7dc22c9f82f78c20caeff00fdd68a2e92e40504a /arch/arm
parent	3c76a8a95daeecd881718f88324041f6a5faab86 (diff)
parent	da497f6fbaa190d34907ecc9dd85cfc62ba9f5a2 (diff)