ARM: imx: set up pllv3 POWER and BYPASS sequentially

Currently, POWER and BYPASS bits are set up in a single write to pllv3
register.  This causes problem occasionally from the IPU/HDMI testing.
Let's follow FSL BSP code to set up POWER bit, relock, and then BYPASS
sequentially.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

1 files changed, 10 insertions, 2 deletions

diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index df1736232961..61364050fccd 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -71,16 +71,24 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
 {
         struct clk_pllv3 *pll = to_clk_pllv3(hw);
         u32 val;
+        int ret;
 
         val = readl_relaxed(pll->base);
-        val &= ~BM_PLL_BYPASS;
         if (pll->powerup_set)
                 val |= BM_PLL_POWER;
         else
                 val &= ~BM_PLL_POWER;
         writel_relaxed(val, pll->base);
 
-        return clk_pllv3_wait_lock(pll);
+        ret = clk_pllv3_wait_lock(pll);
+        if (ret)
+                return ret;
+
+        val = readl_relaxed(pll->base);
+        val &= ~BM_PLL_BYPASS;
+        writel_relaxed(val, pll->base);
+
+        return 0;
 }
 
 static void clk_pllv3_unprepare(struct clk_hw *hw)