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authorLinus Walleij <linus.walleij@linaro.org>2016-02-18 08:23:31 -0500
committerLinus Walleij <linus.walleij@linaro.org>2016-04-04 04:58:04 -0400
commit2440d29d2ae2b4f3b1d1ae87c8130351793d6df6 (patch)
tree23cde20c8ff62dbd19fbbffa727ce3fb4b45970f /arch/arm
parent95109b8b4d425d48c802acfc5c6e38f55c6e7fb5 (diff)
ARM: dts: realview: support all the RealView EB board variants
The ARM RealView Evaluation Baseboards are basically these: - The original ARMv5 EB board with an ARM926EJ-S, ARM1136 or ARM1176 core tile here described in arm-realview-eb.dts no matter which of these core tiles is being used. This can be emulated by QEMU "realview-eb" machine, which by default will have the ARM926EJ-S core tile. - The same board with one of three MPCore Core tiles: ARM11MPCore, not to be confused with the similar ARM PB11MPCore ARM11MPCore test system. This exist in two revisions: - Revision A modeled in arm-realview-eb-11mp.dts - Revision B modeled arm-realview-eb-11mp-revb.dts Revision B can be emulated by the QEMU "realview-eb-mpcore" machine, but to match the hardware also the argument -smp cpus=4 must be passed so that it has four CPU cores, like the hardware. There is also evidently from the code in the kernel a Cortex-A9 core tile for the EB, and this is modeled in arm-realview-eb-a9mp.dts based on the kernel boardfile. I have not found a user guide for this EB core tile on the ARM website and it seems uncommon. It is however included for completeness. Cc: Pawel Moll <pawel.moll@arm.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/Makefile6
-rw-r--r--arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts93
-rw-r--r--arch/arm/boot/dts/arm-realview-eb-11mp.dts74
-rw-r--r--arch/arm/boot/dts/arm-realview-eb-a9mp.dts70
-rw-r--r--arch/arm/boot/dts/arm-realview-eb-mp.dtsi225
-rw-r--r--arch/arm/boot/dts/arm-realview-eb.dts166
-rw-r--r--arch/arm/boot/dts/arm-realview-eb.dtsi453
7 files changed, 1086 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 95c1923ce6fa..ea508fdc1fcc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -552,7 +552,11 @@ dtb-$(CONFIG_ARCH_QCOM) += \
552 qcom-msm8974-sony-xperia-honami.dtb 552 qcom-msm8974-sony-xperia-honami.dtb
553dtb-$(CONFIG_ARCH_REALVIEW) += \ 553dtb-$(CONFIG_ARCH_REALVIEW) += \
554 arm-realview-pb1176.dtb \ 554 arm-realview-pb1176.dtb \
555 arm-realview-pb11mp.dtb 555 arm-realview-pb11mp.dtb \
556 arm-realview-eb.dtb \
557 arm-realview-eb-11mp.dtb \
558 arm-realview-eb-11mp-revb.dtb \
559 arm-realview-eb-a9mp.dtb
556dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 560dtb-$(CONFIG_ARCH_ROCKCHIP) += \
557 rk3036-evb.dtb \ 561 rk3036-evb.dtb \
558 rk3036-kylin.dtb \ 562 rk3036-kylin.dtb \
diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts b/arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts
new file mode 100644
index 000000000000..e68527b0d552
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts
@@ -0,0 +1,93 @@
1/*
2 * Copyright 2016 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23#include "arm-realview-eb-11mp.dts"
24
25/ {
26 model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B";
27};
28
29/*
30 * The revision B has a distinctly different layout of the syscon, so
31 * append a specific compatible-string.
32 */
33&syscon {
34 compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd";
35};
36
37&intc {
38 reg = <0x10101000 0x1000>,
39 <0x10100100 0x100>;
40};
41
42&L2 {
43 reg = <0x10102000 0x1000>;
44};
45
46&scu {
47 reg = <0x10100000 0x100>;
48};
49
50&twd_timer {
51 reg = <0x10100600 0x20>;
52};
53
54&twd_wdog {
55 reg = <0x10100620 0x20>;
56};
57
58/*
59 * On revision B, we cannot reach the secondary interrupt
60 * controller, as a result, some peripherals that are dependent
61 * on their IRQ cannot be reached, so disable them.
62 */
63&intc_second {
64 status = "disabled";
65};
66
67&gpio0 {
68 status = "disabled";
69};
70
71&gpio1 {
72 status = "disabled";
73};
74
75&gpio2 {
76 status = "disabled";
77};
78
79&serial2 {
80 status = "disabled";
81};
82
83&serial3 {
84 status = "disabled";
85};
86
87&ssp {
88 status = "disabled";
89};
90
91&wdog {
92 status = "disabled";
93};
diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp.dts b/arch/arm/boot/dts/arm-realview-eb-11mp.dts
new file mode 100644
index 000000000000..87ff602a2a2d
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-eb-11mp.dts
@@ -0,0 +1,74 @@
1/*
2 * Copyright 2016 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23/dts-v1/;
24#include "arm-realview-eb-mp.dtsi"
25
26/ {
27 model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C";
28 arm,hbi = <0x146>;
29
30 /*
31 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
32 * Reference: ARM DUI 0318F
33 *
34 * To run this machine with QEMU, specify the following:
35 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
36 */
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40 enable-method = "arm,realview-smp";
41
42 MP11_0: cpu@0 {
43 device_type = "cpu";
44 compatible = "arm,arm11mpcore";
45 reg = <0>;
46 next-level-cache = <&L2>;
47 };
48
49 MP11_1: cpu@1 {
50 device_type = "cpu";
51 compatible = "arm,arm11mpcore";
52 reg = <1>;
53 next-level-cache = <&L2>;
54 };
55
56 MP11_2: cpu@2 {
57 device_type = "cpu";
58 compatible = "arm,arm11mpcore";
59 reg = <2>;
60 next-level-cache = <&L2>;
61 };
62
63 MP11_3: cpu@3 {
64 device_type = "cpu";
65 compatible = "arm,arm11mpcore";
66 reg = <3>;
67 next-level-cache = <&L2>;
68 };
69 };
70};
71
72&pmu {
73 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
74};
diff --git a/arch/arm/boot/dts/arm-realview-eb-a9mp.dts b/arch/arm/boot/dts/arm-realview-eb-a9mp.dts
new file mode 100644
index 000000000000..967684b3636c
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-eb-a9mp.dts
@@ -0,0 +1,70 @@
1/*
2 * Copyright 2016 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23/dts-v1/;
24#include "arm-realview-eb-mp.dtsi"
25
26/ {
27 model = "ARM RealView EB Cortex A9 MPCore";
28
29 /*
30 * This is the Cortex A9 MPCore tile used with the
31 * RealView EB.
32 */
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
37
38 A9_0: cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a9";
41 reg = <0>;
42 next-level-cache = <&L2>;
43 };
44
45 A9_1: cpu@1 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a9";
48 reg = <1>;
49 next-level-cache = <&L2>;
50 };
51
52 A9_2: cpu@2 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a9";
55 reg = <2>;
56 next-level-cache = <&L2>;
57 };
58
59 A9_3: cpu@3 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a9";
62 reg = <3>;
63 next-level-cache = <&L2>;
64 };
65 };
66};
67
68&pmu {
69 interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
70};
diff --git a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi
new file mode 100644
index 000000000000..7b8d90b7aeea
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi
@@ -0,0 +1,225 @@
1/*
2 * Copyright 2016 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23#include <dt-bindings/interrupt-controller/irq.h>
24#include <dt-bindings/gpio/gpio.h>
25#include "arm-realview-eb.dtsi"
26
27/*
28 * This is the common include file for all MPCore variants of the
29 * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B
30 * and Cortex-A9 MPCore.
31 */
32/ {
33 soc {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-soc", "simple-bus";
37 regmap = <&syscon>;
38 ranges;
39
40 /* Primary interrupt controller in the test chip */
41 intc: interrupt-controller@1f000100 {
42 compatible = "arm,eb11mp-gic";
43 #interrupt-cells = <3>;
44 #address-cells = <1>;
45 interrupt-controller;
46 reg = <0x1f001000 0x1000>,
47 <0x1f000100 0x100>;
48 };
49
50 /* Secondary interrupt controller on the FPGA */
51 intc_second: interrupt-controller@10040000 {
52 compatible = "arm,pl390";
53 #interrupt-cells = <3>;
54 #address-cells = <1>;
55 interrupt-controller;
56 reg = <0x10041000 0x1000>,
57 <0x10040000 0x100>;
58 interrupt-parent = <&intc>;
59 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
60 };
61
62 L2: l2-cache {
63 compatible = "arm,l220-cache";
64 reg = <0x1f002000 0x1000>;
65 interrupt-parent = <&intc>;
66 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
67 <0 30 IRQ_TYPE_LEVEL_HIGH>,
68 <0 31 IRQ_TYPE_LEVEL_HIGH>;
69 cache-unified;
70 cache-level = <2>;
71 /*
72 * Override default cache size, sets and
73 * associativity as these may be erroneously set
74 * up by boot loader(s), probably for safety
75 * since th outer sync operation can cause the
76 * cache to hang unless disabled.
77 */
78 cache-size = <1048576>; // 1MB
79 cache-sets = <4096>;
80 cache-line-size = <32>;
81 arm,shared-override;
82 arm,parity-enable;
83 arm,outer-sync-disable;
84 };
85
86 scu: scu@1f000000 {
87 compatible = "arm,arm11mp-scu";
88 reg = <0x1f000000 0x100>;
89 };
90
91 twd_timer: timer@1f000600 {
92 compatible = "arm,arm11mp-twd-timer";
93 reg = <0x1f000600 0x20>;
94 interrupt-parent = <&intc>;
95 interrupts = <1 13 0xf04>;
96 };
97
98 twd_wdog: watchdog@1f000620 {
99 compatible = "arm,arm11mp-twd-wdt";
100 reg = <0x1f000620 0x20>;
101 interrupt-parent = <&intc>;
102 interrupts = <1 14 0xf04>;
103 };
104
105 /* PMU with one IRQ line per core */
106 pmu: pmu@0 {
107 compatible = "arm,arm11mpcore-pmu";
108 interrupt-parent = <&intc>;
109 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
110 <0 18 IRQ_TYPE_LEVEL_HIGH>,
111 <0 19 IRQ_TYPE_LEVEL_HIGH>,
112 <0 20 IRQ_TYPE_LEVEL_HIGH>;
113 };
114 };
115};
116
117/*
118 * This adapts all the peripherals to the interrupt routing
119 * to the GIC on the core tile.
120 */
121
122&ethernet {
123 interrupt-parent = <&intc>;
124 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
125};
126
127&usb {
128 interrupt-parent = <&intc>;
129 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
130};
131
132&aaci {
133 interrupt-parent = <&intc>;
134 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
135};
136
137&mmc {
138 interrupt-parent = <&intc>;
139 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
140 <0 15 IRQ_TYPE_LEVEL_HIGH>;
141};
142
143&kmi0 {
144 interrupt-parent = <&intc>;
145 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
146};
147
148&kmi1 {
149 interrupt-parent = <&intc>;
150 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
151};
152
153&charlcd {
154 interrupt-parent = <&intc>;
155 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
156};
157
158&serial0 {
159 interrupt-parent = <&intc>;
160 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
161};
162
163&serial1 {
164 interrupt-parent = <&intc>;
165 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
166};
167
168&timer01 {
169 interrupt-parent = <&intc>;
170 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
171};
172
173&timer23 {
174 interrupt-parent = <&intc>;
175 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
176};
177
178&rtc {
179 interrupt-parent = <&intc>;
180 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
181};
182
183/*
184 * On revision A, these peripherals does not have their IRQ lines
185 * routed to the core tile, but they can be reached on the secondary
186 * GIC.
187 */
188&gpio0 {
189 interrupt-parent = <&intc_second>;
190 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
191};
192
193&gpio1 {
194 interrupt-parent = <&intc_second>;
195 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
196};
197
198&gpio2 {
199 interrupt-parent = <&intc_second>;
200 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
201};
202
203&serial2 {
204 interrupt-parent = <&intc_second>;
205 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
206 status = "okay";
207};
208
209&serial3 {
210 interrupt-parent = <&intc_second>;
211 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
212 status = "okay";
213};
214
215&ssp {
216 interrupt-parent = <&intc_second>;
217 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
218 status = "okay";
219};
220
221&wdog {
222 interrupt-parent = <&intc_second>;
223 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
224 status = "okay";
225};
diff --git a/arch/arm/boot/dts/arm-realview-eb.dts b/arch/arm/boot/dts/arm-realview-eb.dts
new file mode 100644
index 000000000000..15431077f00c
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-eb.dts
@@ -0,0 +1,166 @@
1/*
2 * Copyright 2016 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23/dts-v1/;
24#include <dt-bindings/interrupt-controller/irq.h>
25#include <dt-bindings/gpio/gpio.h>
26#include "arm-realview-eb.dtsi"
27
28/ {
29 model = "ARM RealView Emulation Baseboard";
30 compatible = "arm,realview-eb";
31 arm,hbi = <0x140>;
32
33 /*
34 * This is the core tile with the CPU and GIC etc for the
35 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
36 * or PMU.
37 *
38 * To run this machine with QEMU, specify the following:
39 * qemu-system-arm -M realview-eb
40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
41 * Switches -cpu arm1136 or -cpu arm1176 emulates the other
42 * core tiles.
43 */
44 soc {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "arm,realview-eb-soc", "simple-bus";
48 regmap = <&syscon>;
49 ranges;
50
51 intc: interrupt-controller@10040000 {
52 compatible = "arm,pl390";
53 #interrupt-cells = <3>;
54 #address-cells = <1>;
55 interrupt-controller;
56 reg = <0x10041000 0x1000>,
57 <0x10040000 0x100>;
58 };
59 };
60};
61
62/*
63 * This adapts all the peripherals to the interrupt routing
64 * to the GIC on the core tile.
65 */
66
67&ethernet {
68 interrupt-parent = <&intc>;
69 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
70};
71
72&usb {
73 interrupt-parent = <&intc>;
74 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
75};
76
77&aaci {
78 interrupt-parent = <&intc>;
79 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
80};
81
82&mmc {
83 interrupt-parent = <&intc>;
84 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
85 <0 18 IRQ_TYPE_LEVEL_HIGH>;
86};
87
88&kmi0 {
89 interrupt-parent = <&intc>;
90 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
91};
92
93&kmi1 {
94 interrupt-parent = <&intc>;
95 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
96};
97
98&charlcd {
99 interrupt-parent = <&intc>;
100 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
101};
102
103&serial0 {
104 interrupt-parent = <&intc>;
105 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
106};
107
108&serial1 {
109 interrupt-parent = <&intc>;
110 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
111};
112
113&serial2 {
114 interrupt-parent = <&intc>;
115 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
116};
117
118&serial3 {
119 interrupt-parent = <&intc>;
120 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
121};
122
123&ssp {
124 interrupt-parent = <&intc>;
125 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
126};
127
128&wdog {
129 interrupt-parent = <&intc>;
130 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
131};
132
133&timer01 {
134 interrupt-parent = <&intc>;
135 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
136};
137
138&timer23 {
139 interrupt-parent = <&intc>;
140 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
141};
142
143&gpio0 {
144 interrupt-parent = <&intc>;
145 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
146};
147
148&gpio1 {
149 interrupt-parent = <&intc>;
150 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
151};
152
153&gpio2 {
154 interrupt-parent = <&intc>;
155 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
156};
157
158&rtc {
159 interrupt-parent = <&intc>;
160 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
161};
162
163&clcd {
164 interrupt-parent = <&intc>;
165 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
166};
diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi
new file mode 100644
index 000000000000..1c6a040218e3
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-eb.dtsi
@@ -0,0 +1,453 @@
1/*
2 * Copyright 2016 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23#include <dt-bindings/interrupt-controller/irq.h>
24#include <dt-bindings/gpio/gpio.h>
25#include "skeleton.dtsi"
26
27/ {
28 compatible = "arm,realview-eb";
29
30 chosen { };
31
32 aliases {
33 serial0 = &serial0;
34 serial1 = &serial1;
35 serial2 = &serial2;
36 serial3 = &serial3;
37 i2c0 = &i2c;
38 };
39
40 memory {
41 /* 128 MiB memory @ 0x0 */
42 reg = <0x00000000 0x08000000>;
43 };
44
45 /* The voltage to the MMC card is hardwired at 3.3V */
46 vmmc: fixedregulator@0 {
47 compatible = "regulator-fixed";
48 regulator-name = "vmmc";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 regulator-boot-on;
52 };
53
54 veth: fixedregulator@0 {
55 compatible = "regulator-fixed";
56 regulator-name = "veth";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 regulator-boot-on;
60 };
61
62 xtal24mhz: xtal24mhz@24M {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <24000000>;
66 };
67
68 timclk: timclk@1M {
69 #clock-cells = <0>;
70 compatible = "fixed-factor-clock";
71 clock-div = <24>;
72 clock-mult = <1>;
73 clocks = <&xtal24mhz>;
74 };
75
76 mclk: mclk@24M {
77 #clock-cells = <0>;
78 compatible = "fixed-factor-clock";
79 clock-div = <1>;
80 clock-mult = <1>;
81 clocks = <&xtal24mhz>;
82 };
83
84 kmiclk: kmiclk@24M {
85 #clock-cells = <0>;
86 compatible = "fixed-factor-clock";
87 clock-div = <1>;
88 clock-mult = <1>;
89 clocks = <&xtal24mhz>;
90 };
91
92 sspclk: sspclk@24M {
93 #clock-cells = <0>;
94 compatible = "fixed-factor-clock";
95 clock-div = <1>;
96 clock-mult = <1>;
97 clocks = <&xtal24mhz>;
98 };
99
100 uartclk: uartclk@24M {
101 #clock-cells = <0>;
102 compatible = "fixed-factor-clock";
103 clock-div = <1>;
104 clock-mult = <1>;
105 clocks = <&xtal24mhz>;
106 };
107
108 wdogclk: wdogclk@24M {
109 #clock-cells = <0>;
110 compatible = "fixed-factor-clock";
111 clock-div = <1>;
112 clock-mult = <1>;
113 clocks = <&xtal24mhz>;
114 };
115
116 /* FIXME: this actually hangs off the PLL clocks */
117 pclk: pclk@0 {
118 #clock-cells = <0>;
119 compatible = "fixed-clock";
120 clock-frequency = <0>;
121 };
122
123 flash0@40000000 {
124 /* 2 * 32MiB NOR Flash memory */
125 compatible = "arm,versatile-flash", "cfi-flash";
126 reg = <0x40000000 0x04000000>;
127 bank-width = <4>;
128 };
129
130 flash1@44000000 {
131 /* 2 * 32MiB NOR Flash memory */
132 compatible = "arm,versatile-flash", "cfi-flash";
133 reg = <0x44000000 0x04000000>;
134 bank-width = <4>;
135 };
136
137 /* SMSC 9118 ethernet with PHY and EEPROM */
138 ethernet: ethernet@4e000000 {
139 compatible = "smsc,lan9118", "smsc,lan9115";
140 reg = <0x4e000000 0x10000>;
141 phy-mode = "mii";
142 reg-io-width = <4>;
143 smsc,irq-active-high;
144 smsc,irq-push-pull;
145 vdd33a-supply = <&veth>;
146 vddvario-supply = <&veth>;
147 };
148
149 usb: usb@4f000000 {
150 compatible = "nxp,usb-isp1761";
151 reg = <0x4f000000 0x20000>;
152 port1-otg;
153 };
154
155 /* These peripherals are inside the FPGA */
156 fpga {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 compatible = "simple-bus";
160 ranges;
161
162 syscon: syscon@10000000 {
163 compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
164 reg = <0x10000000 0x1000>;
165
166 led@08.0 {
167 compatible = "register-bit-led";
168 offset = <0x08>;
169 mask = <0x01>;
170 label = "versatile:0";
171 linux,default-trigger = "heartbeat";
172 default-state = "on";
173 };
174 led@08.1 {
175 compatible = "register-bit-led";
176 offset = <0x08>;
177 mask = <0x02>;
178 label = "versatile:1";
179 linux,default-trigger = "mmc0";
180 default-state = "off";
181 };
182 led@08.2 {
183 compatible = "register-bit-led";
184 offset = <0x08>;
185 mask = <0x04>;
186 label = "versatile:2";
187 linux,default-trigger = "cpu0";
188 default-state = "off";
189 };
190 led@08.3 {
191 compatible = "register-bit-led";
192 offset = <0x08>;
193 mask = <0x08>;
194 label = "versatile:3";
195 default-state = "off";
196 };
197 led@08.4 {
198 compatible = "register-bit-led";
199 offset = <0x08>;
200 mask = <0x10>;
201 label = "versatile:4";
202 default-state = "off";
203 };
204 led@08.5 {
205 compatible = "register-bit-led";
206 offset = <0x08>;
207 mask = <0x20>;
208 label = "versatile:5";
209 default-state = "off";
210 };
211 led@08.6 {
212 compatible = "register-bit-led";
213 offset = <0x08>;
214 mask = <0x40>;
215 label = "versatile:6";
216 default-state = "off";
217 };
218 led@08.7 {
219 compatible = "register-bit-led";
220 offset = <0x08>;
221 mask = <0x80>;
222 label = "versatile:7";
223 default-state = "off";
224 };
225 oscclk0: osc0@0c {
226 compatible = "arm,syscon-icst307";
227 #clock-cells = <0>;
228 lock-offset = <0x20>;
229 vco-offset = <0x0C>;
230 clocks = <&xtal24mhz>;
231 };
232 oscclk1: osc1@10 {
233 compatible = "arm,syscon-icst307";
234 #clock-cells = <0>;
235 lock-offset = <0x20>;
236 vco-offset = <0x10>;
237 clocks = <&xtal24mhz>;
238 };
239 oscclk2: osc2@14 {
240 compatible = "arm,syscon-icst307";
241 #clock-cells = <0>;
242 lock-offset = <0x20>;
243 vco-offset = <0x14>;
244 clocks = <&xtal24mhz>;
245 };
246 oscclk3: osc3@18 {
247 compatible = "arm,syscon-icst307";
248 #clock-cells = <0>;
249 lock-offset = <0x20>;
250 vco-offset = <0x18>;
251 clocks = <&xtal24mhz>;
252 };
253 oscclk4: osc4@1c {
254 compatible = "arm,syscon-icst307";
255 #clock-cells = <0>;
256 lock-offset = <0x20>;
257 vco-offset = <0x1c>;
258 clocks = <&xtal24mhz>;
259 };
260 };
261
262 i2c: i2c@10002000 {
263 #address-cells = <1>;
264 #size-cells = <0>;
265 compatible = "arm,versatile-i2c";
266 reg = <0x10002000 0x1000>;
267
268 rtc@68 {
269 compatible = "dallas,ds1338";
270 reg = <0x68>;
271 };
272 };
273
274 aaci: aaci@10004000 {
275 compatible = "arm,pl041", "arm,primecell";
276 reg = <0x10004000 0x1000>;
277 clocks = <&pclk>;
278 clock-names = "apb_pclk";
279 };
280
281 mmc: mmcsd@10005000 {
282 compatible = "arm,pl18x", "arm,primecell";
283 reg = <0x10005000 0x1000>;
284
285 /* Due to frequent FIFO overruns, use just 500 kHz */
286 max-frequency = <500000>;
287 bus-width = <4>;
288 cap-sd-highspeed;
289 cap-mmc-highspeed;
290 clocks = <&mclk>, <&pclk>;
291 clock-names = "mclk", "apb_pclk";
292 vmmc-supply = <&vmmc>;
293 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
294 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
295 };
296
297 kmi0: kmi@10006000 {
298 compatible = "arm,pl050", "arm,primecell";
299 reg = <0x10006000 0x1000>;
300 clocks = <&kmiclk>, <&pclk>;
301 clock-names = "KMIREFCLK", "apb_pclk";
302 };
303
304 kmi1: kmi@10007000 {
305 compatible = "arm,pl050", "arm,primecell";
306 reg = <0x10007000 0x1000>;
307 clocks = <&kmiclk>, <&pclk>;
308 clock-names = "KMIREFCLK", "apb_pclk";
309 };
310
311 charlcd: fpga_charlcd: charlcd@10008000 {
312 compatible = "arm,versatile-lcd";
313 reg = <0x10008000 0x1000>;
314 clocks = <&pclk>;
315 clock-names = "apb_pclk";
316 };
317
318 serial0: serial@10009000 {
319 compatible = "arm,pl011", "arm,primecell";
320 reg = <0x10009000 0x1000>;
321 clocks = <&uartclk>, <&pclk>;
322 clock-names = "uartclk", "apb_pclk";
323 };
324
325 serial1: serial@1000a000 {
326 compatible = "arm,pl011", "arm,primecell";
327 reg = <0x1000a000 0x1000>;
328 clocks = <&uartclk>, <&pclk>;
329 clock-names = "uartclk", "apb_pclk";
330 };
331
332 serial2: serial@1000b000 {
333 compatible = "arm,pl011", "arm,primecell";
334 reg = <0x1000b000 0x1000>;
335 clocks = <&uartclk>, <&pclk>;
336 clock-names = "uartclk", "apb_pclk";
337 };
338
339 serial3: serial@1000c000 {
340 compatible = "arm,pl011", "arm,primecell";
341 reg = <0x1000c000 0x1000>;
342 clocks = <&uartclk>, <&pclk>;
343 clock-names = "uartclk", "apb_pclk";
344 };
345
346 ssp: ssp@1000d000 {
347 compatible = "arm,pl022", "arm,primecell";
348 reg = <0x1000d000 0x1000>;
349 clocks = <&sspclk>, <&pclk>;
350 clock-names = "SSPCLK", "apb_pclk";
351 };
352
353 wdog: watchdog@10010000 {
354 compatible = "arm,sp805", "arm,primecell";
355 reg = <0x10010000 0x1000>;
356 clocks = <&wdogclk>, <&pclk>;
357 clock-names = "wdogclk", "apb_pclk";
358 status = "disabled";
359 };
360
361 timer01: timer@10011000 {
362 compatible = "arm,sp804", "arm,primecell";
363 reg = <0x10011000 0x1000>;
364 clocks = <&timclk>, <&timclk>, <&pclk>;
365 clock-names = "timer1", "timer2", "apb_pclk";
366 };
367
368 timer23: timer@10012000 {
369 compatible = "arm,sp804", "arm,primecell";
370 reg = <0x10012000 0x1000>;
371 clocks = <&timclk>, <&timclk>, <&pclk>;
372 clock-names = "timer1", "timer2", "apb_pclk";
373 };
374
375 gpio0: gpio@10013000 {
376 compatible = "arm,pl061", "arm,primecell";
377 reg = <0x10013000 0x1000>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 clocks = <&pclk>;
383 clock-names = "apb_pclk";
384 };
385
386 gpio1: gpio@10014000 {
387 compatible = "arm,pl061", "arm,primecell";
388 reg = <0x10014000 0x1000>;
389 gpio-controller;
390 #gpio-cells = <2>;
391 interrupt-controller;
392 #interrupt-cells = <2>;
393 clocks = <&pclk>;
394 clock-names = "apb_pclk";
395 };
396
397 gpio2: gpio@10015000 {
398 compatible = "arm,pl061", "arm,primecell";
399 reg = <0x10015000 0x1000>;
400 gpio-controller;
401 #gpio-cells = <2>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 clocks = <&pclk>;
405 clock-names = "apb_pclk";
406 };
407
408 rtc: rtc@10017000 {
409 compatible = "arm,pl031", "arm,primecell";
410 reg = <0x10017000 0x1000>;
411 clocks = <&pclk>;
412 clock-names = "apb_pclk";
413 };
414
415 clcd: clcd@10020000 {
416 compatible = "arm,pl111", "arm,primecell";
417 reg = <0x10020000 0x1000>;
418 interrupt-names = "combined";
419 clocks = <&oscclk0>, <&pclk>;
420 clock-names = "clcdclk", "apb_pclk";
421
422 port {
423 clcd_pads: endpoint {
424 remote-endpoint = <&clcd_panel>;
425 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
426 };
427 };
428
429 panel {
430 compatible = "panel-dpi";
431
432 port {
433 clcd_panel: endpoint {
434 remote-endpoint = <&clcd_pads>;
435 };
436 };
437
438 /* Standard 640x480 VGA timings */
439 panel-timing {
440 clock-frequency = <25175000>;
441 hactive = <640>;
442 hback-porch = <48>;
443 hfront-porch = <16>;
444 hsync-len = <96>;
445 vactive = <480>;
446 vback-porch = <33>;
447 vfront-porch = <10>;
448 vsync-len = <2>;
449 };
450 };
451 };
452 };
453};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 05:46:51 -0500