Merge tag 'kvmarm-for-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/arm updates for 4.19

- Support for Group0 interrupts in guests
- Cache management optimizations for ARMv8.4 systems
- Userspace interface for RAS, allowing error retrival and injection
- Fault path optimization
- Emulated physical timer fixes
- Random cleanups

6 files changed, 92 insertions, 16 deletions

diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
index cdd4d9d6d575..07256b08226c 100644
--- a/arch/arm64/kvm/guest.c
+++ b/arch/arm64/kvm/guest.c
@@ -289,6 +289,39 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         return -EINVAL;
 }
 
+int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
+                              struct kvm_vcpu_events *events)
+{
+        events->exception.serror_pending = !!(vcpu->arch.hcr_el2 & HCR_VSE);
+        events->exception.serror_has_esr = cpus_have_const_cap(ARM64_HAS_RAS_EXTN);
+
+        if (events->exception.serror_pending && events->exception.serror_has_esr)
+                events->exception.serror_esr = vcpu_get_vsesr(vcpu);
+
+        return 0;
+}
+
+int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
+                              struct kvm_vcpu_events *events)
+{
+        bool serror_pending = events->exception.serror_pending;
+        bool has_esr = events->exception.serror_has_esr;
+
+        if (serror_pending && has_esr) {
+                if (!cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
+                        return -EINVAL;
+
+                if (!((events->exception.serror_esr) & ~ESR_ELx_ISS_MASK))
+                        kvm_set_sei_esr(vcpu, events->exception.serror_esr);
+                else
+                        return -EINVAL;
+        } else if (serror_pending) {
+                kvm_inject_vabt(vcpu);
+        }
+
+        return 0;
+}
+
 int __attribute_const__ kvm_target_cpu(void)
 {
         unsigned long implementor = read_cpuid_implementor();
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
index 6fd91b31a131..ea9225160786 100644
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@@ -57,6 +57,7 @@ __invalid:
          * x0: HYP pgd
          * x1: HYP stack
          * x2: HYP vectors
+         * x3: per-CPU offset
          */
 __do_hyp_init:
         /* Check for a stub HVC call */
@@ -119,9 +120,8 @@ CPU_BE(	orr	x4, x4, #SCTLR_ELx_EE)
         mov     sp, x1
         msr     vbar_el2, x2
 
-        /* copy tpidr_el1 into tpidr_el2 for use by HYP */
-        mrs     x1, tpidr_el1
-        msr     tpidr_el2, x1
+        /* Set tpidr_el2 for use by HYP */
+        msr     tpidr_el2, x3
 
         /* Hello, World! */
         eret
diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
index 35bc16832efe..9ce223944983 100644
--- a/arch/arm64/kvm/hyp/sysreg-sr.c
+++ b/arch/arm64/kvm/hyp/sysreg-sr.c
@@ -288,8 +288,3 @@ void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu)
 
         vcpu->arch.sysregs_loaded_on_cpu = false;
 }
-
-void __hyp_text __kvm_set_tpidr_el2(u64 tpidr_el2)
-{
-        asm("msr tpidr_el2, %0": : "r" (tpidr_el2));
-}
diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
index d8e71659ba7e..a55e91dfcf8f 100644
--- a/arch/arm64/kvm/inject_fault.c
+++ b/arch/arm64/kvm/inject_fault.c
@@ -164,9 +164,9 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu)
                 inject_undef64(vcpu);
 }
 
-static void pend_guest_serror(struct kvm_vcpu *vcpu, u64 esr)
+void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 esr)
 {
-        vcpu_set_vsesr(vcpu, esr);
+        vcpu_set_vsesr(vcpu, esr & ESR_ELx_ISS_MASK);
         *vcpu_hcr(vcpu) |= HCR_VSE;
 }
 
@@ -184,5 +184,5 @@ static void pend_guest_serror(struct kvm_vcpu *vcpu, u64 esr)
  */
 void kvm_inject_vabt(struct kvm_vcpu *vcpu)
 {
-        pend_guest_serror(vcpu, ESR_ELx_ISV);
+        kvm_set_sei_esr(vcpu, ESR_ELx_ISV);
 }
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index 4e4aedaf7ab7..e37c78bbe1ca 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -77,8 +77,12 @@ int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext)
         case KVM_CAP_ARM_PMU_V3:
                 r = kvm_arm_support_pmu_v3();
                 break;
+        case KVM_CAP_ARM_INJECT_SERROR_ESR:
+                r = cpus_have_const_cap(ARM64_HAS_RAS_EXTN);
+                break;
         case KVM_CAP_SET_GUEST_DEBUG:
         case KVM_CAP_VCPU_ATTRIBUTES:
+        case KVM_CAP_VCPU_EVENTS:
                 r = 1;
                 break;
         default:
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index a4363735d3f8..22fbbdbece3c 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -194,7 +194,16 @@ static bool access_dcsw(struct kvm_vcpu *vcpu,
         if (!p->is_write)
                 return read_from_write_only(vcpu, p, r);
 
-        kvm_set_way_flush(vcpu);
+        /*
+         * Only track S/W ops if we don't have FWB. It still indicates
+         * that the guest is a bit broken (S/W operations should only
+         * be done by firmware, knowing that there is only a single
+         * CPU left in the system, and certainly not from non-secure
+         * software).
+         */
+        if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
+                kvm_set_way_flush(vcpu);
+
         return true;
 }
 
@@ -243,10 +252,43 @@ static bool access_gic_sgi(struct kvm_vcpu *vcpu,
                            struct sys_reg_params *p,
                            const struct sys_reg_desc *r)
 {
+        bool g1;
+
         if (!p->is_write)
                 return read_from_write_only(vcpu, p, r);
 
-        vgic_v3_dispatch_sgi(vcpu, p->regval);
+        /*
+         * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
+         * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
+         * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
+         * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
+         * group.
+         */
+        if (p->is_aarch32) {
+                switch (p->Op1) {
+                default:                /* Keep GCC quiet */
+                case 0:                 /* ICC_SGI1R */
+                        g1 = true;
+                        break;
+                case 1:                 /* ICC_ASGI1R */
+                case 2:                 /* ICC_SGI0R */
+                        g1 = false;
+                        break;
+                }
+        } else {
+                switch (p->Op2) {
+                default:                /* Keep GCC quiet */
+                case 5:                 /* ICC_SGI1R_EL1 */
+                        g1 = true;
+                        break;
+                case 6:                 /* ICC_ASGI1R_EL1 */
+                case 7:                 /* ICC_SGI0R_EL1 */
+                        g1 = false;
+                        break;
+                }
+        }
+
+        vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
 
         return true;
 }
@@ -1303,6 +1345,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
         { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
         { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
         { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
+        { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
+        { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
         { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
         { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
         { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
@@ -1613,8 +1657,6 @@ static const struct sys_reg_desc cp14_64_regs[] = {
  * register).
  */
 static const struct sys_reg_desc cp15_regs[] = {
-        { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
-
         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
@@ -1737,8 +1779,10 @@ static const struct sys_reg_desc cp15_regs[] = {
 static const struct sys_reg_desc cp15_64_regs[] = {
         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
         { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
-        { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
+        { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
+        { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
+        { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
         { Op1( 2), CRn( 0), CRm(14), Op2( 0), access_cntp_cval },
 };