Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
 "Most of these are CC'd for stable, but there are a few fixing issues
  introduced during the recent merge window too.

  There's also a fix for the xgene PMU driver, but it seemed daft to
  send as a separate pull request, so I've included it here with the
  rest of the fixes.

   - Fix ACPI boot due to recent broken NUMA changes
   - Fix remote enabling of CPU features requiring PSTATE bit manipulation
   - Add address range check when emulating user cache maintenance
   - Fix LL/SC loops that allow compiler to introduce memory accesses
   - Fix recently added write_sysreg_s macro
   - Ensure MDCR_EL2 is initialised on qemu targets without a PMU
   - Avoid kaslr breakage due to MODVERSIONs and DYNAMIC_FTRACE
   - Correctly drive recent ld when building relocatable Image
   - Remove junk IS_ERR check from xgene PMU driver added during merge window
   - pr_cont fixes after core changes in the merge window"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: remove pr_cont abuse from mem_init
  arm64: fix show_regs fallout from KERN_CONT changes
  arm64: kernel: force ET_DYN ELF type for CONFIG_RELOCATABLE=y
  arm64: suspend: Reconfigure PSTATE after resume from idle
  arm64: mm: Set PSTATE.PAN from the cpu_enable_pan() call
  arm64: cpufeature: Schedule enable() calls instead of calling them via IPI
  arm64: Cortex-A53 errata workaround: check for kernel addresses
  arm64: percpu: rewrite ll/sc loops in assembly
  arm64: swp emulation: bound LL/SC retries before rescheduling
  arm64: sysreg: Fix use of XZR in write_sysreg_s
  arm64: kaslr: keep modules close to the kernel when DYNAMIC_FTRACE=y
  arm64: kernel: Init MDCR_EL2 even in the absence of a PMU
  perf: xgene: Remove bogus IS_ERR() check
  arm64: kernel: numa: fix ACPI boot cpu numa node mapping
  arm64: kaslr: fix breakage with CONFIG_MODVERSIONS=y

8 files changed, 78 insertions, 34 deletions

diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c
index 42ffdb54e162..b0988bb1bf64 100644
--- a/arch/arm64/kernel/armv8_deprecated.c
+++ b/arch/arm64/kernel/armv8_deprecated.c
@@ -280,35 +280,43 @@ static void __init register_insn_emulation_sysctl(struct ctl_table *table)
 /*
  * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
  */
-#define __user_swpX_asm(data, addr, res, temp, B)               \
+
+/* Arbitrary constant to ensure forward-progress of the LL/SC loop */
+#define __SWP_LL_SC_LOOPS       4
+
+#define __user_swpX_asm(data, addr, res, temp, temp2, B)        \
         __asm__ __volatile__(                                   \
+        "       mov             %w3, %w7\n"                     \
         ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN,    \
                     CONFIG_ARM64_PAN)                           \
-        "0:     ldxr"B"         %w2, [%3]\n"                    \
-        "1:     stxr"B"         %w0, %w1, [%3]\n"               \
+        "0:     ldxr"B"         %w2, [%4]\n"                    \
+        "1:     stxr"B"         %w0, %w1, [%4]\n"               \
         "       cbz             %w0, 2f\n"                      \
-        "       mov             %w0, %w4\n"                     \
+        "       sub             %w3, %w3, #1\n"                 \
+        "       cbnz            %w3, 0b\n"                      \
+        "       mov             %w0, %w5\n"                     \
         "       b               3f\n"                           \
         "2:\n"                                                  \
         "       mov             %w1, %w2\n"                     \
         "3:\n"                                                  \
         "       .pushsection     .fixup,\"ax\"\n"               \
         "       .align          2\n"                            \
-        "4:     mov             %w0, %w5\n"                     \
+        "4:     mov             %w0, %w6\n"                     \
         "       b               3b\n"                           \
         "       .popsection"                                    \
         _ASM_EXTABLE(0b, 4b)                                    \
         _ASM_EXTABLE(1b, 4b)                                    \
         ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN,    \
                 CONFIG_ARM64_PAN)                               \
-        : "=&r" (res), "+r" (data), "=&r" (temp)                \
-        : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT)              \
+        : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
+        : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT),             \
+          "i" (__SWP_LL_SC_LOOPS)                               \
         : "memory")
 
-#define __user_swp_asm(data, addr, res, temp) \
-        __user_swpX_asm(data, addr, res, temp, "")
-#define __user_swpb_asm(data, addr, res, temp) \
-        __user_swpX_asm(data, addr, res, temp, "b")
+#define __user_swp_asm(data, addr, res, temp, temp2) \
+        __user_swpX_asm(data, addr, res, temp, temp2, "")
+#define __user_swpb_asm(data, addr, res, temp, temp2) \
+        __user_swpX_asm(data, addr, res, temp, temp2, "b")
 
 /*
  * Bit 22 of the instruction encoding distinguishes between
@@ -328,12 +336,12 @@ static int emulate_swpX(unsigned int address, unsigned int *data,
         }
 
         while (1) {
-                unsigned long temp;
+                unsigned long temp, temp2;
 
                 if (type == TYPE_SWPB)
-                        __user_swpb_asm(*data, address, res, temp);
+                        __user_swpb_asm(*data, address, res, temp, temp2);
                 else
-                        __user_swp_asm(*data, address, res, temp);
+                        __user_swp_asm(*data, address, res, temp, temp2);
 
                 if (likely(res != -EAGAIN) || signal_pending(current))
                         break;
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 0150394f4cab..b75e917aac46 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -39,10 +39,11 @@ has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
                 (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
 }
 
-static void cpu_enable_trap_ctr_access(void *__unused)
+static int cpu_enable_trap_ctr_access(void *__unused)
 {
         /* Clear SCTLR_EL1.UCT */
         config_sctlr_el1(SCTLR_EL1_UCT, 0);
+        return 0;
 }
 
 #define MIDR_RANGE(model, min, max) \
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index d577f263cc4a..c02504ea304b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -19,7 +19,9 @@
 #define pr_fmt(fmt) "CPU features: " fmt
 
 #include <linux/bsearch.h>
+#include <linux/cpumask.h>
 #include <linux/sort.h>
+#include <linux/stop_machine.h>
 #include <linux/types.h>
 #include <asm/cpu.h>
 #include <asm/cpufeature.h>
@@ -941,7 +943,13 @@ void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 {
         for (; caps->matches; caps++)
                 if (caps->enable && cpus_have_cap(caps->capability))
-                        on_each_cpu(caps->enable, NULL, true);
+                        /*
+                         * Use stop_machine() as it schedules the work allowing
+                         * us to modify PSTATE, instead of on_each_cpu() which
+                         * uses an IPI, giving us a PSTATE that disappears when
+                         * we return.
+                         */
+                        stop_machine(caps->enable, NULL, cpu_online_mask);
 }
 
 /*
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 427f6d3f084c..332e33193ccf 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -586,8 +586,9 @@ CPU_LE(	movk	x0, #0x30d0, lsl #16	)	// Clear EE and E0E on LE systems
         b.lt    4f                              // Skip if no PMU present
         mrs     x0, pmcr_el0                    // Disable debug access traps
         ubfx    x0, x0, #11, #5                 // to EL2 and allow access to
-        msr     mdcr_el2, x0                    // all PMU counters from EL1
 4:
+        csel    x0, xzr, x0, lt                 // all PMU counters from EL1
+        msr     mdcr_el2, x0                    // (if they exist)
 
         /* Stage-2 translation */
         msr     vttbr_el2, xzr
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 27b2f1387df4..01753cd7d3f0 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -49,6 +49,7 @@
 #include <asm/alternative.h>
 #include <asm/compat.h>
 #include <asm/cacheflush.h>
+#include <asm/exec.h>
 #include <asm/fpsimd.h>
 #include <asm/mmu_context.h>
 #include <asm/processor.h>
@@ -186,10 +187,19 @@ void __show_regs(struct pt_regs *regs)
         printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
                regs->pc, lr, regs->pstate);
         printk("sp : %016llx\n", sp);
-        for (i = top_reg; i >= 0; i--) {
+
+        i = top_reg;
+
+        while (i >= 0) {
                 printk("x%-2d: %016llx ", i, regs->regs[i]);
-                if (i % 2 == 0)
-                        printk("\n");
+                i--;
+
+                if (i % 2 == 0) {
+                        pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
+                        i--;
+                }
+
+                pr_cont("\n");
         }
         printk("\n");
 }
@@ -301,7 +311,7 @@ static void tls_thread_switch(struct task_struct *next)
 }
 
 /* Restore the UAO state depending on next's addr_limit */
-static void uao_thread_switch(struct task_struct *next)
+void uao_thread_switch(struct task_struct *next)
 {
         if (IS_ENABLED(CONFIG_ARM64_UAO)) {
                 if (task_thread_info(next)->addr_limit == KERNEL_DS)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index d3f151cfd4a1..8507703dabe4 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -544,6 +544,7 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
                         return;
                 }
                 bootcpu_valid = true;
+                early_map_cpu_to_node(0, acpi_numa_get_nid(0, hwid));
                 return;
         }
 
diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c
index ad734142070d..bb0cd787a9d3 100644
--- a/arch/arm64/kernel/suspend.c
+++ b/arch/arm64/kernel/suspend.c
@@ -1,8 +1,11 @@
 #include <linux/ftrace.h>
 #include <linux/percpu.h>
 #include <linux/slab.h>
+#include <asm/alternative.h>
 #include <asm/cacheflush.h>
+#include <asm/cpufeature.h>
 #include <asm/debug-monitors.h>
+#include <asm/exec.h>
 #include <asm/pgtable.h>
 #include <asm/memory.h>
 #include <asm/mmu_context.h>
@@ -50,6 +53,14 @@ void notrace __cpu_suspend_exit(void)
         set_my_cpu_offset(per_cpu_offset(cpu));
 
         /*
+         * PSTATE was not saved over suspend/resume, re-enable any detected
+         * features that might not have been set correctly.
+         */
+        asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN,
+                        CONFIG_ARM64_PAN));
+        uao_thread_switch(current);
+
+        /*
          * Restore HW breakpoint registers to sane values
          * before debug exceptions are possibly reenabled
          * through local_dbg_restore.
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 5ff020f8fb7f..c9986b3e0a96 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -428,24 +428,28 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
         force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
 }
 
-void cpu_enable_cache_maint_trap(void *__unused)
+int cpu_enable_cache_maint_trap(void *__unused)
 {
         config_sctlr_el1(SCTLR_EL1_UCI, 0);
+        return 0;
 }
 
 #define __user_cache_maint(insn, address, res)                  \
-        asm volatile (                                          \
-                "1:     " insn ", %1\n"                         \
-                "       mov     %w0, #0\n"                      \
-                "2:\n"                                          \
-                "       .pushsection .fixup,\"ax\"\n"           \
-                "       .align  2\n"                            \
-                "3:     mov     %w0, %w2\n"                     \
-                "       b       2b\n"                           \
-                "       .popsection\n"                          \
-                _ASM_EXTABLE(1b, 3b)                            \
-                : "=r" (res)                                    \
-                : "r" (address), "i" (-EFAULT) )
+        if (untagged_addr(address) >= user_addr_max())          \
+                res = -EFAULT;                                  \
+        else                                                    \
+                asm volatile (                                  \
+                        "1:     " insn ", %1\n"                 \
+                        "       mov     %w0, #0\n"              \
+                        "2:\n"                                  \
+                        "       .pushsection .fixup,\"ax\"\n"   \
+                        "       .align  2\n"                    \
+                        "3:     mov     %w0, %w2\n"             \
+                        "       b       2b\n"                   \
+                        "       .popsection\n"                  \
+                        _ASM_EXTABLE(1b, 3b)                    \
+                        : "=r" (res)                            \
+                        : "r" (address), "i" (-EFAULT) )
 
 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
 {