arm64: simplify sysreg manipulation

A while back we added {read,write}_sysreg accessors to handle accesses
to system registers, without the usual boilerplate asm volatile,
temporary variable, etc.

This patch makes use of these across arm64 to make code shorter and
clearer. For sequences with a trailing ISB, the existing isb() macro is
also used so that asm blocks can be removed entirely.

A few uses of inline assembly for msr/mrs are left as-is. Those
manipulating sp_el0 for the current thread_info value have special
clobber requiremends.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

4 files changed, 13 insertions, 19 deletions

diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
index b8629d52fba9..9617301f76b5 100644
--- a/arch/arm64/kernel/cacheinfo.c
+++ b/arch/arm64/kernel/cacheinfo.c
@@ -39,7 +39,7 @@ static inline enum cache_type get_cache_type(int level)
 
         if (level > MAX_CACHE_LEVEL)
                 return CACHE_TYPE_NOCACHE;
-        asm volatile ("mrs     %x0, clidr_el1" : "=r" (clidr));
+        clidr = read_sysreg(clidr_el1);
         return CLIDR_CTYPE(clidr, level);
 }
 
@@ -55,11 +55,9 @@ u64 __attribute_const__ cache_get_ccsidr(u64 csselr)
 
         WARN_ON(preemptible());
 
-        /* Put value into CSSELR */
-        asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
+        write_sysreg(csselr, csselr_el1);
         isb();
-        /* Read result out of CCSIDR */
-        asm volatile("mrs %x0, ccsidr_el1" : "=r" (ccsidr));
+        ccsidr = read_sysreg(ccsidr_el1);
 
         return ccsidr;
 }
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index d97fdc1f6a38..73ae90ef434c 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -46,16 +46,14 @@ static void mdscr_write(u32 mdscr)
 {
         unsigned long flags;
         local_dbg_save(flags);
-        asm volatile("msr mdscr_el1, %0" :: "r" (mdscr));
+        write_sysreg(mdscr, mdscr_el1);
         local_dbg_restore(flags);
 }
 NOKPROBE_SYMBOL(mdscr_write);
 
 static u32 mdscr_read(void)
 {
-        u32 mdscr;
-        asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr));
-        return mdscr;
+        return read_sysreg(mdscr_el1);
 }
 NOKPROBE_SYMBOL(mdscr_read);
 
@@ -134,7 +132,7 @@ NOKPROBE_SYMBOL(disable_debug_monitors);
  */
 static int clear_os_lock(unsigned int cpu)
 {
-        asm volatile("msr oslar_el1, %0" : : "r" (0));
+        write_sysreg(0, oslar_el1);
         isb();
         return 0;
 }
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 6cd2612236dc..a4f5f766af08 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -202,7 +202,7 @@ void show_regs(struct pt_regs * regs)
 
 static void tls_thread_flush(void)
 {
-        asm ("msr tpidr_el0, xzr");
+        write_sysreg(0, tpidr_el0);
 
         if (is_compat_task()) {
                 current->thread.tp_value = 0;
@@ -213,7 +213,7 @@ static void tls_thread_flush(void)
                  * with a stale shadow state during context switch.
                  */
                 barrier();
-                asm ("msr tpidrro_el0, xzr");
+                write_sysreg(0, tpidrro_el0);
         }
 }
 
@@ -253,7 +253,7 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
                  * Read the current TLS pointer from tpidr_el0 as it may be
                  * out-of-sync with the saved value.
                  */
-                asm("mrs %0, tpidr_el0" : "=r" (*task_user_tls(p)));
+                *task_user_tls(p) = read_sysreg(tpidr_el0);
 
                 if (stack_start) {
                         if (is_compat_thread(task_thread_info(p)))
@@ -289,17 +289,15 @@ static void tls_thread_switch(struct task_struct *next)
 {
         unsigned long tpidr, tpidrro;
 
-        asm("mrs %0, tpidr_el0" : "=r" (tpidr));
+        tpidr = read_sysreg(tpidr_el0);
         *task_user_tls(current) = tpidr;
 
         tpidr = *task_user_tls(next);
         tpidrro = is_compat_thread(task_thread_info(next)) ?
                   next->thread.tp_value : 0;
 
-        asm(
-        "       msr     tpidr_el0, %0\n"
-        "       msr     tpidrro_el0, %1"
-        : : "r" (tpidr), "r" (tpidrro));
+        write_sysreg(tpidr, tpidr_el0);
+        write_sysreg(tpidrro, tpidrro_el0);
 }
 
 /* Restore the UAO state depending on next's addr_limit */
diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c
index 28c511b06edf..abaf582fc7a8 100644
--- a/arch/arm64/kernel/sys_compat.c
+++ b/arch/arm64/kernel/sys_compat.c
@@ -94,7 +94,7 @@ long compat_arm_syscall(struct pt_regs *regs)
                  * See comment in tls_thread_flush.
                  */
                 barrier();
-                asm ("msr tpidrro_el0, %0" : : "r" (regs->regs[0]));
+                write_sysreg(regs->regs[0], tpidrro_el0);
                 return 0;
 
         default: