arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1

Neoverse-N1 is also affected by ARM64_ERRATUM_1188873, so let's
add it to the list of affected CPUs.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[will: Update silicon-errata.txt]
Signed-off-by: Will Deacon <will.deacon@arm.com>

1 files changed, 11 insertions, 2 deletions

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 9950bb0cbd52..06f1c8aae1dc 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -603,6 +603,16 @@ static const struct midr_range workaround_clean_cache[] = {
 };
 #endif
 
+#ifdef CONFIG_ARM64_ERRATUM_1188873
+static const struct midr_range erratum_1188873_list[] = {
+        /* Cortex-A76 r0p0 to r2p0 */
+        MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
+        /* Neoverse-N1 r0p0 to r2p0 */
+        MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 2, 0),
+        {},
+};
+#endif
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
         {
@@ -725,10 +735,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_1188873
         {
-                /* Cortex-A76 r0p0 to r2p0 */
                 .desc = "ARM erratum 1188873",
                 .capability = ARM64_WORKAROUND_1188873,
-                ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
+                ERRATA_MIDR_RANGE_LIST(erratum_1188873_list),
         },
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_1165522