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author | Dave Airlie <airlied@redhat.com> | 2018-11-28 19:34:03 -0500 |
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committer | Dave Airlie <airlied@redhat.com> | 2018-11-28 19:34:03 -0500 |
commit | 1ec28f8b8ada4e4f77d1af006a3a474f4f83b8e3 (patch) | |
tree | 2e810e02a66cdec0bc82a8555796b7083ad03416 /arch/arm64/kernel/cpufeature.c | |
parent | 61647c77cb15354a329cbb36fe7a2253b36b51b1 (diff) | |
parent | 2e6e902d185027f8e3cb8b7305238f7e35d6a436 (diff) |
Merge v4.20-rc4 into drm-next
Requested by Boris Brezillon for some vc4 fixes that are needed for future vc4 work.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'arch/arm64/kernel/cpufeature.c')
-rw-r--r-- | arch/arm64/kernel/cpufeature.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index af50064dea51..aec5ecb85737 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c | |||
@@ -1333,7 +1333,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { | |||
1333 | .cpu_enable = cpu_enable_hw_dbm, | 1333 | .cpu_enable = cpu_enable_hw_dbm, |
1334 | }, | 1334 | }, |
1335 | #endif | 1335 | #endif |
1336 | #ifdef CONFIG_ARM64_SSBD | ||
1337 | { | 1336 | { |
1338 | .desc = "CRC32 instructions", | 1337 | .desc = "CRC32 instructions", |
1339 | .capability = ARM64_HAS_CRC32, | 1338 | .capability = ARM64_HAS_CRC32, |
@@ -1343,6 +1342,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { | |||
1343 | .field_pos = ID_AA64ISAR0_CRC32_SHIFT, | 1342 | .field_pos = ID_AA64ISAR0_CRC32_SHIFT, |
1344 | .min_field_value = 1, | 1343 | .min_field_value = 1, |
1345 | }, | 1344 | }, |
1345 | #ifdef CONFIG_ARM64_SSBD | ||
1346 | { | 1346 | { |
1347 | .desc = "Speculative Store Bypassing Safe (SSBS)", | 1347 | .desc = "Speculative Store Bypassing Safe (SSBS)", |
1348 | .capability = ARM64_SSBS, | 1348 | .capability = ARM64_SSBS, |