Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Olof Johansson:
 "As usual, this is the massive branch we have for each release.  Lots
  of various updates and additions of hardware descriptions on existing
  hardware, as well as the usual additions of new boards and SoCs.

  This is also the first release where we've started mixing 64- and
  32-bit DT updates in one branch.

  (Specific details on what's actually here and new is pretty easy to
  tell from the diffstat, so there's little point in duplicating listing
  it here)"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits)
  ARM: dts: uniphier: add system-bus-controller nodes
  ARM64: juno: disable NOR flash node by default
  ARM: dts: uniphier: add outer cache controller nodes
  arm64: defconfig: Enable PCI generic host bridge by default
  arm64: Juno: Add support for the PCIe host bridge on Juno R1
  Documentation: of: Document the bindings used by Juno R1 PCIe host bridge
  ARM: dts: uniphier: add I2C aliases for ProXstream2 boards
  dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
  dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards
  dts/ls2080a: Update Simulator DTS to add support of various peripherals
  dts/ls2080a: Remove text about writing to Free Software Foundation
  dts/ls2080a: Update DTSI to add support of various peripherals
  doc: DTS: Update DWC3 binding to provide reference to generic bindings
  doc/bindings: Update GPIO devicetree binding documentation for LS2080A
  Documentation/dts: Move FSL board-specific bindings out of /powerpc
  Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards
  arm64: Rename FSL LS2085A SoC support code to LS2080A
  arm64: Use generic Layerscape SoC family naming
  ARM: dts: uniphier: add ProXstream2 Vodka board support
  ARM: dts: uniphier: add ProXstream2 Gentil board support
  ...

5 files changed, 355 insertions, 4 deletions

diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
index fa81a6ee6473..cd158b80e29b 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,4 +1,4 @@
-dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb
 
 always          := $(dtb-y)
 subdir-y        := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index e36a539468a5..8d43a0fce522 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -17,11 +17,14 @@
         compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
 
         aliases {
-                serial0 = &uart0;
+                serial0 = &uart0; /* On board UART0 */
+                serial1 = &uart1; /* BT UART */
+                serial2 = &uart2; /* LS Expansion UART0 */
+                serial3 = &uart3; /* LS Expansion UART1 */
         };
 
         chosen {
-                stdout-path = "serial0:115200n8";
+                stdout-path = "serial3:115200n8";
         };
 
         memory@0 {
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380815b6..82d2488a0e86 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/hi6220-clock.h>
 
 / {
         compatible = "hisilicon,hi6220";
@@ -164,8 +165,48 @@
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x0 0xf8015000 0x0 0x1000>;
                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
+                        clocks = <&ao_ctrl HI6220_UART0_PCLK>,
+                                 <&ao_ctrl HI6220_UART0_PCLK>;
                         clock-names = "uartclk", "apb_pclk";
                 };
+
+                uart1: uart@f7111000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x0 0xf7111000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sys_ctrl HI6220_UART1_PCLK>,
+                                 <&sys_ctrl HI6220_UART1_PCLK>;
+                        clock-names = "uartclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart2: uart@f7112000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x0 0xf7112000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sys_ctrl HI6220_UART2_PCLK>,
+                                 <&sys_ctrl HI6220_UART2_PCLK>;
+                        clock-names = "uartclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart3: uart@f7113000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x0 0xf7113000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sys_ctrl HI6220_UART3_PCLK>,
+                                 <&sys_ctrl HI6220_UART3_PCLK>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+
+                uart4: uart@f7114000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x0 0xf7114000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sys_ctrl HI6220_UART4_PCLK>,
+                                 <&sys_ctrl HI6220_UART4_PCLK>;
+                        clock-names = "uartclk", "apb_pclk";
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
new file mode 100644
index 000000000000..ae34e250456f
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
@@ -0,0 +1,36 @@
+/**
+ * dts file for Hisilicon D02 Development Board
+ *
+ * Copyright (C) 2014,2015 Hisilicon Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ */
+
+/dts-v1/;
+
+#include "hip05.dtsi"
+
+/ {
+        model = "Hisilicon Hip05 D02 Development Board";
+        compatible = "hisilicon,hip05-d02";
+
+        memory@00000000 {
+                device_type = "memory";
+                reg = <0x0 0x00000000 0x0 0x80000000>;
+        };
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+};
+
+&uart0 {
+        status = "ok";
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
new file mode 100644
index 000000000000..4ff16d016e34
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -0,0 +1,271 @@
+/**
+ * dts file for Hisilicon D02 Development Board
+ *
+ * Copyright (C) 2014,2015 Hisilicon Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        compatible = "hisilicon,hip05-d02";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        psci {
+                compatible = "arm,psci-0.2";
+                method = "smc";
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu-map {
+                        cluster0 {
+                                core0 {
+                                        cpu = <&cpu0>;
+                                };
+                                core1 {
+                                        cpu = <&cpu1>;
+                                };
+                                core2 {
+                                        cpu = <&cpu2>;
+                                };
+                                core3 {
+                                        cpu = <&cpu3>;
+                                };
+                        };
+                        cluster1 {
+                                core0 {
+                                        cpu = <&cpu4>;
+                                };
+                                core1 {
+                                        cpu = <&cpu5>;
+                                };
+                                core2 {
+                                        cpu = <&cpu6>;
+                                };
+                                core3 {
+                                        cpu = <&cpu7>;
+                                };
+                        };
+                        cluster2 {
+                                core0 {
+                                        cpu = <&cpu8>;
+                                };
+                                core1 {
+                                        cpu = <&cpu9>;
+                                };
+                                core2 {
+                                        cpu = <&cpu10>;
+                                };
+                                core3 {
+                                        cpu = <&cpu11>;
+                                };
+                        };
+                        cluster3 {
+                                core0 {
+                                        cpu = <&cpu12>;
+                                };
+                                core1 {
+                                        cpu = <&cpu13>;
+                                };
+                                core2 {
+                                        cpu = <&cpu14>;
+                                };
+                                core3 {
+                                        cpu = <&cpu15>;
+                                };
+                        };
+                };
+
+                cpu0: cpu@20000 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20000>;
+                        enable-method = "psci";
+                };
+
+                cpu1: cpu@20001 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20001>;
+                        enable-method = "psci";
+                };
+
+                cpu2: cpu@20002 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20002>;
+                        enable-method = "psci";
+                };
+
+                cpu3: cpu@20003 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20003>;
+                        enable-method = "psci";
+                };
+
+                cpu4: cpu@20100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20100>;
+                        enable-method = "psci";
+                };
+
+                cpu5: cpu@20101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20101>;
+                        enable-method = "psci";
+                };
+
+                cpu6: cpu@20102 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20102>;
+                        enable-method = "psci";
+                };
+
+                cpu7: cpu@20103 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20103>;
+                        enable-method = "psci";
+                };
+
+                cpu8: cpu@20200 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20200>;
+                        enable-method = "psci";
+                };
+
+                cpu9: cpu@20201 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20201>;
+                        enable-method = "psci";
+                };
+
+                cpu10: cpu@20202 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20202>;
+                        enable-method = "psci";
+                };
+
+                cpu11: cpu@20203 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20203>;
+                        enable-method = "psci";
+                };
+
+                cpu12: cpu@20300 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20300>;
+                        enable-method = "psci";
+                };
+
+                cpu13: cpu@20301 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20301>;
+                        enable-method = "psci";
+                };
+
+                cpu14: cpu@20302 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20302>;
+                        enable-method = "psci";
+                };
+
+                cpu15: cpu@20303 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x20303>;
+                        enable-method = "psci";
+                };
+        };
+
+        gic: interrupt-controller@8d000000 {
+                compatible = "arm,gic-v3";
+                #interrupt-cells = <3>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                interrupt-controller;
+                #redistributor-regions = <1>;
+                redistributor-stride = <0x0 0x30000>;
+                reg = <0x0 0x8d000000 0 0x10000>,       /* GICD */
+                      <0x0 0x8d100000 0 0x300000>,      /* GICR */
+                      <0x0 0xfe000000 0 0x10000>,       /* GICC */
+                      <0x0 0xfe010000 0 0x10000>,       /* GICH */
+                      <0x0 0xfe020000 0 0x10000>;       /* GICV */
+                interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+                its_totems: interrupt-controller@8c000000 {
+                        compatible = "arm,gic-v3-its";
+                        msi-controller;
+                        reg = <0x0 0x8c000000 0x0 0x40000>;
+                };
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+        };
+
+        pmu {
+                compatible = "arm,armv8-pmuv3";
+                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                refclk200mhz: refclk200mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <200000000>;
+                };
+
+                uart0: uart@80300000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x0 0x80300000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&refclk200mhz>;
+                        clock-names = "apb_pclk";
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        status = "disabled";
+                };
+
+                uart1: uart@80310000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x0 0x80310000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&refclk200mhz>;
+                        clock-names = "apb_pclk";
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        status = "disabled";
+                };
+        };
+};