OMAP: PM constraints: add omap_pm_set_min_clk_rate()

Add omap_pm_set_min_clk_rate().  This constraint is meant for use by
device drivers to translate a certain device-specific performance
constraint (e.g., "minimum polygons per second") to a clock rate for
the driver's device, given the driver's intimate knowledge of the
device hardware (e.g., device type, device hardware revision, firmware
revision, etc.)  From a general PM core perspective, clock rate is
probably the closest general analog to "performance" that is
available, but the exact mapping from a use-case-specific performance
constraint to clock rate must be done by the driver.  Drivers intended for
upstream merging shouldn't hardcode specific clock rates in their code
without basing those rates on some performance criteria requested through
the driver's subsystem (ideally, from userspace).

Imre Deak <imre.deak@nokia.com> described the need and use-case for
this constraint, and discussed the implementation - thanks, Imre.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Imre Deak <imre.deak@nokia.com>

1 files changed, 27 insertions, 0 deletions

diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index b0414f90c6e3..e129ce80c53b 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -149,6 +149,33 @@ int omap_pm_set_max_sdma_lat(struct device *dev, long t)
         return 0;
 }
 
+int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
+{
+        if (!dev || !c || r < 0) {
+                WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+                return -EINVAL;
+        }
+
+        if (r == 0)
+                pr_debug("OMAP PM: remove min clk rate constraint: "
+                         "dev %s\n", dev_name(dev));
+        else
+                pr_debug("OMAP PM: add min clk rate constraint: "
+                         "dev %s, rate = %ld Hz\n", dev_name(dev), r);
+
+        /*
+         * Code in a real implementation should keep track of these
+         * constraints on the clock, and determine the highest minimum
+         * clock rate.  It should iterate over each OPP and determine
+         * whether the OPP will result in a clock rate that would
+         * satisfy this constraint (and any other PM constraint in effect
+         * at that time).  Once it finds the lowest-voltage OPP that
+         * meets those conditions, it should switch to it, or return
+         * an error if the code is not capable of doing so.
+         */
+
+        return 0;
+}
 
 /*
  * DSP Bridge-specific constraints