ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9

For supporting single image on all Tegra series, we need to skip some HW
support code for Cortex-A9 only.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

1 files changed, 18 insertions, 6 deletions

diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index f9f2164a2fc7..2269c0d6fa67 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -70,19 +70,31 @@
         movt    \reg, #:upper16:\val
 .endm
 
+/* Marco to check CPU part num */
+.macro check_cpu_part_num part_num, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c0, c0, 0
+        ubfx    \tmp1, \tmp1, #4, #12
+        mov32   \tmp2, \part_num
+        cmp     \tmp1, \tmp2
+.endm
+
 /* Macro to exit SMP coherency. */
 .macro exit_smp, tmp1, tmp2
         mrc     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
         bic     \tmp1, \tmp1, #(1<<6) | (1<<0)  @ clear ACTLR.SMP | ACTLR.FW
         mcr     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
         isb
-        cpu_id  \tmp1
-        mov     \tmp1, \tmp1, lsl #2
-        mov     \tmp2, #0xf
-        mov     \tmp2, \tmp2, lsl \tmp1
-        mov32   \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
-        str     \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
+#ifdef CONFIG_HAVE_ARM_SCU
+        check_cpu_part_num 0xc09, \tmp1, \tmp2
+        mrceq   p15, 0, \tmp1, c0, c0, 5
+        andeq   \tmp1, \tmp1, #0xF
+        moveq   \tmp1, \tmp1, lsl #2
+        moveq   \tmp2, #0xf
+        moveq   \tmp2, \tmp2, lsl \tmp1
+        ldreq   \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
+        streq   \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
         dsb
+#endif
 .endm
 
 /* Macro to check Tegra revision */