SPEAr: Use CLKDEV_INIT for defining clk_lookups

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>

1 files changed, 40 insertions, 40 deletions

diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index f0518049c12e..5a469800b142 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -623,53 +623,53 @@ static struct clk dummy_apb_pclk;
 
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
+        CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
         /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-        { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},
+        CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+        CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
         /* clock derived from 32 KHz os          clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
+        CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
         /* clock derived from 30 MHz os          clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-        { .dev_id = "wdt",              .clk = &wdt_clk},
+        CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+        CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+        CLKDEV_INIT("wdt", NULL, &wdt_clk),
         /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-        { .con_id = "clcd_synth_clk",   .clk = &clcd_synth_clk},
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-        { .con_id = "gpt3_synth_clk",   .clk = &gpt3_synth_clk},
-        { .dev_id = "d0000000.serial",  .clk = &uart0_clk},
-        { .dev_id = "d0080000.serial",  .clk = &uart1_clk},
-        { .dev_id = "firda",            .clk = &firda_clk},
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
-        { .dev_id = "gpt3",             .clk = &gpt3_clk},
+        CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+        CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+        CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+        CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+        CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
+        CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+        CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+        CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
+        CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
+        CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
+        CLKDEV_INIT("firda", NULL, &firda_clk),
+        CLKDEV_INIT("clcd", NULL, &clcd_clk),
+        CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+        CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+        CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
+        CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
         /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
-        { .con_id = "usbh.0_clk",       .clk = &usbh0_clk},
-        { .con_id = "usbh.1_clk",       .clk = &usbh1_clk},
+        CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+        CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+        CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
         /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "d0200000.i2c",     .clk = &i2c_clk},
-        { .dev_id = "dma",              .clk = &dma_clk},
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
-        { .dev_id = "gmac",             .clk = &gmac_clk},
-        { .dev_id = "fc000000.flash",   .clk = &smi_clk},
-        { .dev_id = "d1800000.flash",   .clk = &fsmc_clk},
+        CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+        CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
+        CLKDEV_INIT("dma", NULL, &dma_clk),
+        CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+        CLKDEV_INIT("gmac", NULL, &gmac_clk),
+        CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
+        CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
         /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-        { .dev_id = "f0100000.gpio",    .clk = &gpio0_clk},
-        { .dev_id = "fc980000.gpio",    .clk = &gpio1_clk},
-        { .dev_id = "d8100000.gpio",    .clk = &gpio2_clk},
+        CLKDEV_INIT("adc", NULL, &adc_clk),
+        CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
+        CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
+        CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
+        CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
+        CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
+        CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
 };
 
 void __init spear6xx_clk_init(void)