ARM: socfpga: Enable Arria10 L2 cache ECC on startup

Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be
enabled before data is stored in memory otherwise the ECC will fail on
reads.

Use DT_MACHINE to select Arria10 L2 cache function.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1458576106-24505-9-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>

1 files changed, 9 insertions, 1 deletions

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 7e0aad2ec3d1..e9b5b603df4b 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -66,6 +66,14 @@ static void __init socfpga_init_irq(void)
                 socfpga_init_ocram_ecc();
 }
 
+static void __init socfpga_arria10_init_irq(void)
+{
+        irqchip_init();
+        socfpga_sysmgr_init();
+        if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
+                socfpga_init_arria10_l2_ecc();
+}
+
 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 {
         u32 temp;
@@ -113,7 +121,7 @@ static const char *altera_a10_dt_match[] = {
 DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
         .l2c_aux_val    = 0,
         .l2c_aux_mask   = ~0,
-        .init_irq       = socfpga_init_irq,
+        .init_irq       = socfpga_arria10_init_irq,
         .restart        = socfpga_arria10_restart,
         .dt_compat      = altera_a10_dt_match,
 MACHINE_END