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author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-06-26 14:34:35 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-06-26 14:34:35 -0400 |
commit | 4aa705b18bf17c4ff33ff7bbcd3f0c596443fa81 (patch) | |
tree | 3b166bff290d123ccaa88598ad2d45be67f5b358 /arch/arm/mach-socfpga/core.h | |
parent | c11d716218910c3aa2bac1bb641e6086ad649555 (diff) | |
parent | 2879e43f09122f8b3ef5456e3d7e48716b086e60 (diff) |
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform support updates from Kevin Hilman:
"Our SoC branch usually contains expanded support for new SoCs and
other core platform code. Some highlights from this round:
- sunxi: SMP support for A23 SoC
- socpga: big-endian support
- pxa: conversion to common clock framework
- bcm: SMP support for BCM63138
- imx: support new I.MX7D SoC
- zte: basic support for ZX296702 SoC"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits)
ARM: zx: Add basic defconfig support for ZX296702
ARM: dts: zx: add an initial zx296702 dts and doc
clk: zx: add clock support to zx296702
dt-bindings: Add #defines for ZTE ZX296702 clocks
ARM: socfpga: fix build error due to secondary_startup
MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS
ARM: ep93xx: simone: support for SPI-based MMC/SD cards
MAINTAINERS: update Shawn's email to use kernel.org one
ARM: socfpga: support suspend to ram
ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
ARM: EXYNOS: register power domain driver from core_initcall
ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs
ARM: SAMSUNG: Constify platform_device_id
ARM: EXYNOS: Constify irq_domain_ops
ARM: EXYNOS: add coupled cpuidle support for Exynos3250
ARM: EXYNOS: add exynos_get_boot_addr() helper
ARM: EXYNOS: add exynos_set_boot_addr() helper
ARM: EXYNOS: make exynos_core_restart() less verbose
ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout
...
Diffstat (limited to 'arch/arm/mach-socfpga/core.h')
-rw-r--r-- | arch/arm/mach-socfpga/core.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 767c09e954a0..7259c3732702 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2012 Pavel Machek <pavel@denx.de> | 2 | * Copyright 2012 Pavel Machek <pavel@denx.de> |
3 | * Copyright (C) 2012 Altera Corporation | 3 | * Copyright (C) 2012-2015 Altera Corporation |
4 | * | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
@@ -25,21 +25,24 @@ | |||
25 | #define SOCFPGA_RSTMGR_MODPERRST 0x14 | 25 | #define SOCFPGA_RSTMGR_MODPERRST 0x14 |
26 | #define SOCFPGA_RSTMGR_BRGMODRST 0x1c | 26 | #define SOCFPGA_RSTMGR_BRGMODRST 0x1c |
27 | 27 | ||
28 | #define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 | ||
29 | |||
28 | /* System Manager bits */ | 30 | /* System Manager bits */ |
29 | #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ | 31 | #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ |
30 | #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ | 32 | #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ |
31 | 33 | ||
32 | #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ | 34 | #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ |
33 | 35 | ||
34 | extern void __iomem *socfpga_scu_base_addr; | ||
35 | |||
36 | extern void socfpga_init_clocks(void); | 36 | extern void socfpga_init_clocks(void); |
37 | extern void socfpga_sysmgr_init(void); | 37 | extern void socfpga_sysmgr_init(void); |
38 | 38 | ||
39 | extern void __iomem *sys_manager_base_addr; | 39 | extern void __iomem *sys_manager_base_addr; |
40 | extern void __iomem *rst_manager_base_addr; | 40 | extern void __iomem *rst_manager_base_addr; |
41 | extern void __iomem *sdr_ctl_base_addr; | ||
42 | |||
43 | u32 socfpga_sdram_self_refresh(u32 sdr_base); | ||
44 | extern unsigned int socfpga_sdram_self_refresh_sz; | ||
41 | 45 | ||
42 | extern struct smp_operations socfpga_smp_ops; | ||
43 | extern char secondary_trampoline, secondary_trampoline_end; | 46 | extern char secondary_trampoline, secondary_trampoline_end; |
44 | 47 | ||
45 | extern unsigned long socfpga_cpu1start_addr; | 48 | extern unsigned long socfpga_cpu1start_addr; |