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authorSebastien Guiriec <s-guiriec@ti.com>2013-02-10 13:22:24 -0500
committerPaul Walmsley <paul@pwsan.com>2013-02-10 13:22:24 -0500
commit9f0c5996b73b31b482136462c8118148469c2030 (patch)
tree94e790fece4d13afede1701d2dbffce90fe3d3b1 /arch/arm/mach-omap2
parentc02060d869247215c2ea15fd650c333d30f5b210 (diff)
ARM: OMAP4: hwmod data: Update AESS data with memory bank area
Add AESS memory bank data in hwmod in order to provide memory address information to the driver. This version also changes the AESS main clock to use a non-CLKCTRL-based functional clock. These are being removed from the clock data, since they should be handled by the IP block integration code. Without this change, the kernel crashes during boot. Thanks to Tony Lindgren for reporting this during a test merge. Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com> [paul@pwsan.com: updated to change the AESS main_clk] Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c44
1 files changed, 43 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c9c251e23147..a30c113a7f5e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -349,7 +349,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
349 .clkdm_name = "abe_clkdm", 349 .clkdm_name = "abe_clkdm",
350 .mpu_irqs = omap44xx_aess_irqs, 350 .mpu_irqs = omap44xx_aess_irqs,
351 .sdma_reqs = omap44xx_aess_sdma_reqs, 351 .sdma_reqs = omap44xx_aess_sdma_reqs,
352 .main_clk = "aess_fck", 352 .main_clk = "aess_fclk",
353 .prcm = { 353 .prcm = {
354 .omap4 = { 354 .omap4 = {
355 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, 355 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
@@ -4250,6 +4250,27 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4250 4250
4251static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { 4251static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4252 { 4252 {
4253 .name = "dmem",
4254 .pa_start = 0x40180000,
4255 .pa_end = 0x4018ffff
4256 },
4257 {
4258 .name = "cmem",
4259 .pa_start = 0x401a0000,
4260 .pa_end = 0x401a1fff
4261 },
4262 {
4263 .name = "smem",
4264 .pa_start = 0x401c0000,
4265 .pa_end = 0x401c5fff
4266 },
4267 {
4268 .name = "pmem",
4269 .pa_start = 0x401e0000,
4270 .pa_end = 0x401e1fff
4271 },
4272 {
4273 .name = "mpu",
4253 .pa_start = 0x401f1000, 4274 .pa_start = 0x401f1000,
4254 .pa_end = 0x401f13ff, 4275 .pa_end = 0x401f13ff,
4255 .flags = ADDR_TYPE_RT 4276 .flags = ADDR_TYPE_RT
@@ -4268,6 +4289,27 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4268 4289
4269static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { 4290static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4270 { 4291 {
4292 .name = "dmem_dma",
4293 .pa_start = 0x49080000,
4294 .pa_end = 0x4908ffff
4295 },
4296 {
4297 .name = "cmem_dma",
4298 .pa_start = 0x490a0000,
4299 .pa_end = 0x490a1fff
4300 },
4301 {
4302 .name = "smem_dma",
4303 .pa_start = 0x490c0000,
4304 .pa_end = 0x490c5fff
4305 },
4306 {
4307 .name = "pmem_dma",
4308 .pa_start = 0x490e0000,
4309 .pa_end = 0x490e1fff
4310 },
4311 {
4312 .name = "dma",
4271 .pa_start = 0x490f1000, 4313 .pa_start = 0x490f1000,
4272 .pa_end = 0x490f13ff, 4314 .pa_end = 0x490f13ff,
4273 .flags = ADDR_TYPE_RT 4315 .flags = ADDR_TYPE_RT