Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into clk-next

4 files changed, 62 insertions, 17 deletions

diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index b935ed2922d8..85e0b0c06718 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -208,3 +208,56 @@ void omap2xxx_clkt_vps_late_init(void)
                 clk_put(c);
         }
 }
+
+#ifdef CONFIG_OF
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
+static const struct clk_ops virt_prcm_set_ops = {
+        .recalc_rate    = &omap2_table_mpu_recalc,
+        .set_rate       = &omap2_select_table_rate,
+        .round_rate     = &omap2_round_to_table_rate,
+};
+
+/**
+ * omap2xxx_clkt_vps_init - initialize virt_prcm_set clock
+ *
+ * Does a manual init for the virtual prcm DVFS clock for OMAP2. This
+ * function is called only from omap2 DT clock init, as the virtual
+ * node is not modelled in the DT clock data.
+ */
+void omap2xxx_clkt_vps_init(void)
+{
+        struct clk_init_data init = { NULL };
+        struct clk_hw_omap *hw = NULL;
+        struct clk *clk;
+        const char *parent_name = "mpu_ck";
+        struct clk_lookup *lookup = NULL;
+
+        omap2xxx_clkt_vps_late_init();
+        omap2xxx_clkt_vps_check_bootloader_rates();
+
+        hw = kzalloc(sizeof(*hw), GFP_KERNEL);
+        lookup = kzalloc(sizeof(*lookup), GFP_KERNEL);
+        if (!hw || !lookup)
+                goto cleanup;
+        init.name = "virt_prcm_set";
+        init.ops = &virt_prcm_set_ops;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        hw->hw.init = &init;
+
+        clk = clk_register(NULL, &hw->hw);
+
+        lookup->dev_id = NULL;
+        lookup->con_id = "cpufreq_ck";
+        lookup->clk = clk;
+
+        clkdev_add(lookup);
+        return;
+cleanup:
+        kfree(hw);
+        kfree(lookup);
+}
+#endif
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index bda767a9dea8..12f54d428d7c 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -178,17 +178,6 @@ struct clksel {
         const struct clksel_rate *rates;
 };
 
-struct clk_hw_omap_ops {
-        void                    (*find_idlest)(struct clk_hw_omap *oclk,
-                                        void __iomem **idlest_reg,
-                                        u8 *idlest_bit, u8 *idlest_val);
-        void                    (*find_companion)(struct clk_hw_omap *oclk,
-                                        void __iomem **other_reg,
-                                        u8 *other_bit);
-        void                    (*allow_idle)(struct clk_hw_omap *oclk);
-        void                    (*deny_idle)(struct clk_hw_omap *oclk);
-};
-
 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
                                         unsigned long parent_rate);
 
@@ -279,8 +268,6 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
 extern const struct clk_hw_omap_ops clkhwops_apll54;
 extern const struct clk_hw_omap_ops clkhwops_apll96;
-extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
-extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
 
 /* clksel_rate blocks shared between OMAP44xx and AM33xx */
 extern const struct clksel_rate div_1_0_rates[];
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index 539dc08afbba..45f41a411603 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -21,10 +21,6 @@ unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
                                       unsigned long parent_rate);
 unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
                                    unsigned long parent_rate);
-unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
-                                    unsigned long parent_rate);
-int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
-                             unsigned long parent_rate);
 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
 unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
                                       unsigned long parent_rate);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index fcd8036af910..6d7ba37e2257 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -319,6 +319,15 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
 
         /* Set DPLL multiplier, divider */
         v = omap2_clk_readl(clk, dd->mult_div1_reg);
+
+        /* Handle Duty Cycle Correction */
+        if (dd->dcc_mask) {
+                if (dd->last_rounded_rate >= dd->dcc_rate)
+                        v |= dd->dcc_mask; /* Enable DCC */
+                else
+                        v &= ~dd->dcc_mask; /* Disable DCC */
+        }
+
         v &= ~(dd->mult_mask | dd->div1_mask);
         v |= dd->last_rounded_m << __ffs(dd->mult_mask);
         v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);