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authorLinus Torvalds <torvalds@linux-foundation.org>2015-02-21 15:30:30 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-02-21 15:30:30 -0500
commit18a8d49973667aa016e68826eeb374788b7c63b0 (patch)
treed7f90fcf05087ce50ee931b596e60e4c3c082a29 /arch/arm/mach-omap2
parentc189cb8ef62832f33b6cf757350a0270532a1ad8 (diff)
parentec02ace8ca0a50eef430d3676de5c5fa978b0e29 (diff)
Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c3688
-rw-r--r--arch/arm/mach-omap2/clock.c16
-rw-r--r--arch/arm/mach-omap2/clock.h14
-rw-r--r--arch/arm/mach-omap2/clock_common_data.c11
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c13
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c2
-rw-r--r--arch/arm/mach-omap2/io.c26
-rw-r--r--arch/arm/mach-omap2/prm.h1
-rw-r--r--arch/arm/mach-omap2/prm_common.c11
10 files changed, 50 insertions, 3734 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 00d5d8f9f150..b83f18fcec9b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -190,7 +190,7 @@ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
190obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o 190obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
191obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o 191obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
192obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o 192obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
193obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o 193obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
194obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o 194obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
195obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) 195obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
196obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 196obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
deleted file mode 100644
index e79c80bbc755..000000000000
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ /dev/null
@@ -1,3688 +0,0 @@
1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
9 * With many device clock fixes by Kevin Hilman and Jouni Högander
10 * DPLL bypass clock support added by Roman Tereshonkov
11 *
12 */
13
14/*
15 * Virtual clocks are introduced as convenient tools.
16 * They are sources for other clocks and not supposed
17 * to be requested from drivers directly.
18 */
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/clk-private.h>
23#include <linux/list.h>
24#include <linux/io.h>
25
26#include "soc.h"
27#include "iomap.h"
28#include "clock.h"
29#include "clock3xxx.h"
30#include "clock34xx.h"
31#include "clock36xx.h"
32#include "clock3517.h"
33#include "cm3xxx.h"
34#include "cm-regbits-34xx.h"
35#include "prm3xxx.h"
36#include "prm-regbits-34xx.h"
37#include "control.h"
38
39/*
40 * clocks
41 */
42
43#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
44
45/* Maximum DPLL multiplier, divider values for OMAP3 */
46#define OMAP3_MAX_DPLL_MULT 2047
47#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
48#define OMAP3_MAX_DPLL_DIV 128
49
50DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
51
52DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
53
54DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
55
56DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
57
58DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
59
60DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
61
62DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
63
64DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
65
66DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
67
68DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
69
70DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
71
72DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
73
74DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
75
76static const char *osc_sys_ck_parent_names[] = {
77 "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
78 "virt_38_4m_ck", "virt_16_8m_ck",
79};
80
81DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
82 OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
83 OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
84
85DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
86 OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
87 OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
88
89static struct dpll_data dpll3_dd = {
90 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
91 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
92 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
93 .clk_bypass = &sys_ck,
94 .clk_ref = &sys_ck,
95 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
96 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
97 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
98 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
99 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
100 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
101 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
102 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
103 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
104 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
105 .max_multiplier = OMAP3_MAX_DPLL_MULT,
106 .min_divider = 1,
107 .max_divider = OMAP3_MAX_DPLL_DIV,
108};
109
110static struct clk dpll3_ck;
111
112static const char *dpll3_ck_parent_names[] = {
113 "sys_ck",
114 "sys_ck",
115};
116
117static const struct clk_ops dpll3_ck_ops = {
118 .init = &omap2_init_clk_clkdm,
119 .get_parent = &omap2_init_dpll_parent,
120 .recalc_rate = &omap3_dpll_recalc,
121 .round_rate = &omap2_dpll_round_rate,
122};
123
124static struct clk_hw_omap dpll3_ck_hw = {
125 .hw = {
126 .clk = &dpll3_ck,
127 },
128 .ops = &clkhwops_omap3_dpll,
129 .dpll_data = &dpll3_dd,
130 .clkdm_name = "dpll3_clkdm",
131};
132
133DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
134
135DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
136 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
137 OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
138 OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
139 CLK_DIVIDER_ONE_BASED, NULL);
140
141static struct clk core_ck;
142
143static const char *core_ck_parent_names[] = {
144 "dpll3_m2_ck",
145};
146
147static const struct clk_ops core_ck_ops = {};
148
149DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
150DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
151
152DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
153 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
154 OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
155 CLK_DIVIDER_ONE_BASED, NULL);
156
157DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
158 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
159 OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
160 CLK_DIVIDER_ONE_BASED, NULL);
161
162static struct clk security_l4_ick2;
163
164static const char *security_l4_ick2_parent_names[] = {
165 "l4_ick",
166};
167
168DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
169DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
170
171static struct clk aes1_ick;
172
173static const char *aes1_ick_parent_names[] = {
174 "security_l4_ick2",
175};
176
177static const struct clk_ops aes1_ick_ops = {
178 .enable = &omap2_dflt_clk_enable,
179 .disable = &omap2_dflt_clk_disable,
180 .is_enabled = &omap2_dflt_clk_is_enabled,
181};
182
183static struct clk_hw_omap aes1_ick_hw = {
184 .hw = {
185 .clk = &aes1_ick,
186 },
187 .ops = &clkhwops_iclk_wait,
188 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
189 .enable_bit = OMAP3430_EN_AES1_SHIFT,
190};
191
192DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
193
194static struct clk core_l4_ick;
195
196static const struct clk_ops core_l4_ick_ops = {
197 .init = &omap2_init_clk_clkdm,
198};
199
200DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
201DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
202
203static struct clk aes2_ick;
204
205static const char *aes2_ick_parent_names[] = {
206 "core_l4_ick",
207};
208
209static const struct clk_ops aes2_ick_ops = {
210 .init = &omap2_init_clk_clkdm,
211 .enable = &omap2_dflt_clk_enable,
212 .disable = &omap2_dflt_clk_disable,
213 .is_enabled = &omap2_dflt_clk_is_enabled,
214};
215
216static struct clk_hw_omap aes2_ick_hw = {
217 .hw = {
218 .clk = &aes2_ick,
219 },
220 .ops = &clkhwops_iclk_wait,
221 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
222 .enable_bit = OMAP3430_EN_AES2_SHIFT,
223 .clkdm_name = "core_l4_clkdm",
224};
225
226DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
227
228static struct clk dpll1_fck;
229
230static struct dpll_data dpll1_dd = {
231 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
232 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
233 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
234 .clk_bypass = &dpll1_fck,
235 .clk_ref = &sys_ck,
236 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
237 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
238 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
239 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
240 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
241 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
242 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
243 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
244 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
245 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
246 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
247 .max_multiplier = OMAP3_MAX_DPLL_MULT,
248 .min_divider = 1,
249 .max_divider = OMAP3_MAX_DPLL_DIV,
250};
251
252static struct clk dpll1_ck;
253
254static const struct clk_ops dpll1_ck_ops = {
255 .init = &omap2_init_clk_clkdm,
256 .enable = &omap3_noncore_dpll_enable,
257 .disable = &omap3_noncore_dpll_disable,
258 .get_parent = &omap2_init_dpll_parent,
259 .recalc_rate = &omap3_dpll_recalc,
260 .set_rate = &omap3_noncore_dpll_set_rate,
261 .set_parent = &omap3_noncore_dpll_set_parent,
262 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
263 .determine_rate = &omap3_noncore_dpll_determine_rate,
264 .round_rate = &omap2_dpll_round_rate,
265};
266
267static struct clk_hw_omap dpll1_ck_hw = {
268 .hw = {
269 .clk = &dpll1_ck,
270 },
271 .ops = &clkhwops_omap3_dpll,
272 .dpll_data = &dpll1_dd,
273 .clkdm_name = "dpll1_clkdm",
274};
275
276DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
277
278DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
279
280DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
281 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
282 OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
283 OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
284 CLK_DIVIDER_ONE_BASED, NULL);
285
286static struct clk mpu_ck;
287
288static const char *mpu_ck_parent_names[] = {
289 "dpll1_x2m2_ck",
290};
291
292DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
293DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
294
295DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
296 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
297 OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
298 0x0, NULL);
299
300static struct clk cam_ick;
301
302static struct clk_hw_omap cam_ick_hw = {
303 .hw = {
304 .clk = &cam_ick,
305 },
306 .ops = &clkhwops_iclk,
307 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
308 .enable_bit = OMAP3430_EN_CAM_SHIFT,
309 .clkdm_name = "cam_clkdm",
310};
311
312DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
313
314/* DPLL4 */
315/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
316/* Type: DPLL */
317static struct dpll_data dpll4_dd;
318
319static struct dpll_data dpll4_dd_34xx __initdata = {
320 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
321 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
322 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
323 .clk_bypass = &sys_ck,
324 .clk_ref = &sys_ck,
325 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
326 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
327 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
328 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
329 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
330 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
331 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
332 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
333 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
334 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
335 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
336 .max_multiplier = OMAP3_MAX_DPLL_MULT,
337 .min_divider = 1,
338 .max_divider = OMAP3_MAX_DPLL_DIV,
339};
340
341static struct dpll_data dpll4_dd_3630 __initdata = {
342 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
343 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
344 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
345 .clk_bypass = &sys_ck,
346 .clk_ref = &sys_ck,
347 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
348 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
349 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
350 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
351 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
352 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
353 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
354 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
355 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
356 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
357 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
358 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
359 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
360 .min_divider = 1,
361 .max_divider = OMAP3_MAX_DPLL_DIV,
362 .flags = DPLL_J_TYPE
363};
364
365static struct clk dpll4_ck;
366
367static const struct clk_ops dpll4_ck_ops = {
368 .init = &omap2_init_clk_clkdm,
369 .enable = &omap3_noncore_dpll_enable,
370 .disable = &omap3_noncore_dpll_disable,
371 .get_parent = &omap2_init_dpll_parent,
372 .recalc_rate = &omap3_dpll_recalc,
373 .set_rate = &omap3_dpll4_set_rate,
374 .set_parent = &omap3_noncore_dpll_set_parent,
375 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
376 .determine_rate = &omap3_noncore_dpll_determine_rate,
377 .round_rate = &omap2_dpll_round_rate,
378};
379
380static struct clk_hw_omap dpll4_ck_hw = {
381 .hw = {
382 .clk = &dpll4_ck,
383 },
384 .dpll_data = &dpll4_dd,
385 .ops = &clkhwops_omap3_dpll,
386 .clkdm_name = "dpll4_clkdm",
387};
388
389DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
390
391static const struct clk_div_table dpll4_mx_ck_div_table[] = {
392 { .div = 1, .val = 1 },
393 { .div = 2, .val = 2 },
394 { .div = 3, .val = 3 },
395 { .div = 4, .val = 4 },
396 { .div = 5, .val = 5 },
397 { .div = 6, .val = 6 },
398 { .div = 7, .val = 7 },
399 { .div = 8, .val = 8 },
400 { .div = 9, .val = 9 },
401 { .div = 10, .val = 10 },
402 { .div = 11, .val = 11 },
403 { .div = 12, .val = 12 },
404 { .div = 13, .val = 13 },
405 { .div = 14, .val = 14 },
406 { .div = 15, .val = 15 },
407 { .div = 16, .val = 16 },
408 { .div = 17, .val = 17 },
409 { .div = 18, .val = 18 },
410 { .div = 19, .val = 19 },
411 { .div = 20, .val = 20 },
412 { .div = 21, .val = 21 },
413 { .div = 22, .val = 22 },
414 { .div = 23, .val = 23 },
415 { .div = 24, .val = 24 },
416 { .div = 25, .val = 25 },
417 { .div = 26, .val = 26 },
418 { .div = 27, .val = 27 },
419 { .div = 28, .val = 28 },
420 { .div = 29, .val = 29 },
421 { .div = 30, .val = 30 },
422 { .div = 31, .val = 31 },
423 { .div = 32, .val = 32 },
424 { .div = 0 },
425};
426
427DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
428 OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
429 OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
430 CLK_DIVIDER_ONE_BASED, NULL);
431
432static struct clk dpll4_m5x2_ck;
433
434static const char *dpll4_m5x2_ck_parent_names[] = {
435 "dpll4_m5_ck",
436};
437
438static const struct clk_ops dpll4_m5x2_ck_ops = {
439 .init = &omap2_init_clk_clkdm,
440 .enable = &omap2_dflt_clk_enable,
441 .disable = &omap2_dflt_clk_disable,
442 .is_enabled = &omap2_dflt_clk_is_enabled,
443 .set_rate = &omap3_clkoutx2_set_rate,
444 .recalc_rate = &omap3_clkoutx2_recalc,
445 .round_rate = &omap3_clkoutx2_round_rate,
446};
447
448static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
449 .init = &omap2_init_clk_clkdm,
450 .enable = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
451 .disable = &omap2_dflt_clk_disable,
452 .recalc_rate = &omap3_clkoutx2_recalc,
453};
454
455static struct clk_hw_omap dpll4_m5x2_ck_hw = {
456 .hw = {
457 .clk = &dpll4_m5x2_ck,
458 },
459 .ops = &clkhwops_wait,
460 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
461 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
462 .flags = INVERT_ENABLE,
463 .clkdm_name = "dpll4_clkdm",
464};
465
466DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
467 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
468
469static struct clk dpll4_m5x2_ck_3630 = {
470 .name = "dpll4_m5x2_ck",
471 .hw = &dpll4_m5x2_ck_hw.hw,
472 .parent_names = dpll4_m5x2_ck_parent_names,
473 .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
474 .ops = &dpll4_m5x2_ck_3630_ops,
475 .flags = CLK_SET_RATE_PARENT,
476};
477
478static struct clk cam_mclk;
479
480static const char *cam_mclk_parent_names[] = {
481 "dpll4_m5x2_ck",
482};
483
484static struct clk_hw_omap cam_mclk_hw = {
485 .hw = {
486 .clk = &cam_mclk,
487 },
488 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
489 .enable_bit = OMAP3430_EN_CAM_SHIFT,
490 .clkdm_name = "cam_clkdm",
491};
492
493static struct clk cam_mclk = {
494 .name = "cam_mclk",
495 .hw = &cam_mclk_hw.hw,
496 .parent_names = cam_mclk_parent_names,
497 .num_parents = ARRAY_SIZE(cam_mclk_parent_names),
498 .ops = &aes2_ick_ops,
499 .flags = CLK_SET_RATE_PARENT,
500};
501
502static const struct clksel_rate clkout2_src_core_rates[] = {
503 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
504 { .div = 0 }
505};
506
507static const struct clksel_rate clkout2_src_sys_rates[] = {
508 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
509 { .div = 0 }
510};
511
512static const struct clksel_rate clkout2_src_96m_rates[] = {
513 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
514 { .div = 0 }
515};
516
517DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
518 OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
519 OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
520 CLK_DIVIDER_ONE_BASED, NULL);
521
522static struct clk dpll4_m2x2_ck;
523
524static const char *dpll4_m2x2_ck_parent_names[] = {
525 "dpll4_m2_ck",
526};
527
528static struct clk_hw_omap dpll4_m2x2_ck_hw = {
529 .hw = {
530 .clk = &dpll4_m2x2_ck,
531 },
532 .ops = &clkhwops_wait,
533 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
534 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
535 .flags = INVERT_ENABLE,
536 .clkdm_name = "dpll4_clkdm",
537};
538
539DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
540
541static struct clk dpll4_m2x2_ck_3630 = {
542 .name = "dpll4_m2x2_ck",
543 .hw = &dpll4_m2x2_ck_hw.hw,
544 .parent_names = dpll4_m2x2_ck_parent_names,
545 .num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
546 .ops = &dpll4_m5x2_ck_3630_ops,
547};
548
549static struct clk omap_96m_alwon_fck;
550
551static const char *omap_96m_alwon_fck_parent_names[] = {
552 "dpll4_m2x2_ck",
553};
554
555DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
556DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
557 core_ck_ops);
558
559static struct clk cm_96m_fck;
560
561static const char *cm_96m_fck_parent_names[] = {
562 "omap_96m_alwon_fck",
563};
564
565DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
566DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
567
568static const struct clksel_rate clkout2_src_54m_rates[] = {
569 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
570 { .div = 0 }
571};
572
573DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
574 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
575 OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
576 0, dpll4_mx_ck_div_table, NULL);
577
578static struct clk dpll4_m3x2_ck;
579
580static const char *dpll4_m3x2_ck_parent_names[] = {
581 "dpll4_m3_ck",
582};
583
584static struct clk_hw_omap dpll4_m3x2_ck_hw = {
585 .hw = {
586 .clk = &dpll4_m3x2_ck,
587 },
588 .ops = &clkhwops_wait,
589 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
590 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
591 .flags = INVERT_ENABLE,
592 .clkdm_name = "dpll4_clkdm",
593};
594
595DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
596
597static struct clk dpll4_m3x2_ck_3630 = {
598 .name = "dpll4_m3x2_ck",
599 .hw = &dpll4_m3x2_ck_hw.hw,
600 .parent_names = dpll4_m3x2_ck_parent_names,
601 .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
602 .ops = &dpll4_m5x2_ck_3630_ops,
603};
604
605static const char *omap_54m_fck_parent_names[] = {
606 "dpll4_m3x2_ck", "sys_altclk",
607};
608
609DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
610 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
611 OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
612
613static const struct clksel clkout2_src_clksel[] = {
614 { .parent = &core_ck, .rates = clkout2_src_core_rates },
615 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
616 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
617 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
618 { .parent = NULL },
619};
620
621static const char *clkout2_src_ck_parent_names[] = {
622 "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
623};
624
625static const struct clk_ops clkout2_src_ck_ops = {
626 .init = &omap2_init_clk_clkdm,
627 .enable = &omap2_dflt_clk_enable,
628 .disable = &omap2_dflt_clk_disable,
629 .is_enabled = &omap2_dflt_clk_is_enabled,
630 .recalc_rate = &omap2_clksel_recalc,
631 .get_parent = &omap2_clksel_find_parent_index,
632 .set_parent = &omap2_clksel_set_parent,
633};
634
635DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
636 clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
637 OMAP3430_CLKOUT2SOURCE_MASK,
638 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
639 NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
640
641static const struct clksel_rate omap_48m_cm96m_rates[] = {
642 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
643 { .div = 0 }
644};
645
646static const struct clksel_rate omap_48m_alt_rates[] = {
647 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
648 { .div = 0 }
649};
650
651static const struct clksel omap_48m_clksel[] = {
652 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
653 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
654 { .parent = NULL },
655};
656
657static const char *omap_48m_fck_parent_names[] = {
658 "cm_96m_fck", "sys_altclk",
659};
660
661static struct clk omap_48m_fck;
662
663static const struct clk_ops omap_48m_fck_ops = {
664 .recalc_rate = &omap2_clksel_recalc,
665 .get_parent = &omap2_clksel_find_parent_index,
666 .set_parent = &omap2_clksel_set_parent,
667};
668
669static struct clk_hw_omap omap_48m_fck_hw = {
670 .hw = {
671 .clk = &omap_48m_fck,
672 },
673 .clksel = omap_48m_clksel,
674 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
675 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
676};
677
678DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
679
680DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
681
682static struct clk core_12m_fck;
683
684static const char *core_12m_fck_parent_names[] = {
685 "omap_12m_fck",
686};
687
688DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
689DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
690
691static struct clk core_48m_fck;
692
693static const char *core_48m_fck_parent_names[] = {
694 "omap_48m_fck",
695};
696
697DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
698DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
699
700static const char *omap_96m_fck_parent_names[] = {
701 "cm_96m_fck", "sys_ck",
702};
703
704DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
705 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
706 OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
707
708static struct clk core_96m_fck;
709
710static const char *core_96m_fck_parent_names[] = {
711 "omap_96m_fck",
712};
713
714DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
715DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
716
717static struct clk core_l3_ick;
718
719static const char *core_l3_ick_parent_names[] = {
720 "l3_ick",
721};
722
723DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
724DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
725
726DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
727
728static struct clk corex2_fck;
729
730static const char *corex2_fck_parent_names[] = {
731 "dpll3_m2x2_ck",
732};
733
734DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
735DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
736
737static const char *cpefuse_fck_parent_names[] = {
738 "sys_ck",
739};
740
741static struct clk cpefuse_fck;
742
743static struct clk_hw_omap cpefuse_fck_hw = {
744 .hw = {
745 .clk = &cpefuse_fck,
746 },
747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
748 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
749 .clkdm_name = "core_l4_clkdm",
750};
751
752DEFINE_STRUCT_CLK(cpefuse_fck, cpefuse_fck_parent_names, aes2_ick_ops);
753
754static struct clk csi2_96m_fck;
755
756static const char *csi2_96m_fck_parent_names[] = {
757 "core_96m_fck",
758};
759
760static struct clk_hw_omap csi2_96m_fck_hw = {
761 .hw = {
762 .clk = &csi2_96m_fck,
763 },
764 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
765 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
766 .clkdm_name = "cam_clkdm",
767};
768
769DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
770
771static struct clk d2d_26m_fck;
772
773static struct clk_hw_omap d2d_26m_fck_hw = {
774 .hw = {
775 .clk = &d2d_26m_fck,
776 },
777 .ops = &clkhwops_wait,
778 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
779 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
780 .clkdm_name = "d2d_clkdm",
781};
782
783DEFINE_STRUCT_CLK(d2d_26m_fck, cpefuse_fck_parent_names, aes2_ick_ops);
784
785static struct clk des1_ick;
786
787static struct clk_hw_omap des1_ick_hw = {
788 .hw = {
789 .clk = &des1_ick,
790 },
791 .ops = &clkhwops_iclk_wait,
792 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
793 .enable_bit = OMAP3430_EN_DES1_SHIFT,
794};
795
796DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
797
798static struct clk des2_ick;
799
800static struct clk_hw_omap des2_ick_hw = {
801 .hw = {
802 .clk = &des2_ick,
803 },
804 .ops = &clkhwops_iclk_wait,
805 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
806 .enable_bit = OMAP3430_EN_DES2_SHIFT,
807 .clkdm_name = "core_l4_clkdm",
808};
809
810DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
811
812DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
813 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
814 OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
815 CLK_DIVIDER_ONE_BASED, NULL);
816
817static struct clk dpll2_fck;
818
819static struct dpll_data dpll2_dd = {
820 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
821 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
822 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
823 .clk_bypass = &dpll2_fck,
824 .clk_ref = &sys_ck,
825 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
826 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
827 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
828 .modes = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
829 (1 << DPLL_LOW_POWER_BYPASS)),
830 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
831 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
832 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
833 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
834 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
835 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
836 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
837 .max_multiplier = OMAP3_MAX_DPLL_MULT,
838 .min_divider = 1,
839 .max_divider = OMAP3_MAX_DPLL_DIV,
840};
841
842static struct clk dpll2_ck;
843
844static struct clk_hw_omap dpll2_ck_hw = {
845 .hw = {
846 .clk = &dpll2_ck,
847 },
848 .ops = &clkhwops_omap3_dpll,
849 .dpll_data = &dpll2_dd,
850 .clkdm_name = "dpll2_clkdm",
851};
852
853DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
854
855DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
856 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
857 OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
858 CLK_DIVIDER_ONE_BASED, NULL);
859
860DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
861 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
862 OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
863 OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
864 CLK_DIVIDER_ONE_BASED, NULL);
865
866DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
867 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
868 OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
869 CLK_DIVIDER_ONE_BASED, NULL);
870
871static struct clk dpll3_m3x2_ck;
872
873static const char *dpll3_m3x2_ck_parent_names[] = {
874 "dpll3_m3_ck",
875};
876
877static struct clk_hw_omap dpll3_m3x2_ck_hw = {
878 .hw = {
879 .clk = &dpll3_m3x2_ck,
880 },
881 .ops = &clkhwops_wait,
882 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
883 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
884 .flags = INVERT_ENABLE,
885 .clkdm_name = "dpll3_clkdm",
886};
887
888DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
889
890static struct clk dpll3_m3x2_ck_3630 = {
891 .name = "dpll3_m3x2_ck",
892 .hw = &dpll3_m3x2_ck_hw.hw,
893 .parent_names = dpll3_m3x2_ck_parent_names,
894 .num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
895 .ops = &dpll4_m5x2_ck_3630_ops,
896};
897
898DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
899
900DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
901 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
902 OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
903 0, dpll4_mx_ck_div_table, NULL);
904
905static struct clk dpll4_m4x2_ck;
906
907static const char *dpll4_m4x2_ck_parent_names[] = {
908 "dpll4_m4_ck",
909};
910
911static struct clk_hw_omap dpll4_m4x2_ck_hw = {
912 .hw = {
913 .clk = &dpll4_m4x2_ck,
914 },
915 .ops = &clkhwops_wait,
916 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
917 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
918 .flags = INVERT_ENABLE,
919 .clkdm_name = "dpll4_clkdm",
920};
921
922DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
923 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
924
925static struct clk dpll4_m4x2_ck_3630 = {
926 .name = "dpll4_m4x2_ck",
927 .hw = &dpll4_m4x2_ck_hw.hw,
928 .parent_names = dpll4_m4x2_ck_parent_names,
929 .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
930 .ops = &dpll4_m5x2_ck_3630_ops,
931 .flags = CLK_SET_RATE_PARENT,
932};
933
934DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
935 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
936 OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
937 CLK_DIVIDER_ONE_BASED, NULL);
938
939static struct clk dpll4_m6x2_ck;
940
941static const char *dpll4_m6x2_ck_parent_names[] = {
942 "dpll4_m6_ck",
943};
944
945static struct clk_hw_omap dpll4_m6x2_ck_hw = {
946 .hw = {
947 .clk = &dpll4_m6x2_ck,
948 },
949 .ops = &clkhwops_wait,
950 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
951 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
952 .flags = INVERT_ENABLE,
953 .clkdm_name = "dpll4_clkdm",
954};
955
956DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
957
958static struct clk dpll4_m6x2_ck_3630 = {
959 .name = "dpll4_m6x2_ck",
960 .hw = &dpll4_m6x2_ck_hw.hw,
961 .parent_names = dpll4_m6x2_ck_parent_names,
962 .num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
963 .ops = &dpll4_m5x2_ck_3630_ops,
964};
965
966DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
967
968static struct dpll_data dpll5_dd = {
969 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
970 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
971 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
972 .clk_bypass = &sys_ck,
973 .clk_ref = &sys_ck,
974 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
975 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
976 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
977 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
978 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
979 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
980 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
981 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
982 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
983 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
984 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
985 .max_multiplier = OMAP3_MAX_DPLL_MULT,
986 .min_divider = 1,
987 .max_divider = OMAP3_MAX_DPLL_DIV,
988};
989
990static struct clk dpll5_ck;
991
992static struct clk_hw_omap dpll5_ck_hw = {
993 .hw = {
994 .clk = &dpll5_ck,
995 },
996 .ops = &clkhwops_omap3_dpll,
997 .dpll_data = &dpll5_dd,
998 .clkdm_name = "dpll5_clkdm",
999};
1000
1001DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
1002
1003DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
1004 OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1005 OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
1006 CLK_DIVIDER_ONE_BASED, NULL);
1007
1008static struct clk dss1_alwon_fck_3430es1;
1009
1010static const char *dss1_alwon_fck_3430es1_parent_names[] = {
1011 "dpll4_m4x2_ck",
1012};
1013
1014static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
1015 .hw = {
1016 .clk = &dss1_alwon_fck_3430es1,
1017 },
1018 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1019 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1020 .clkdm_name = "dss_clkdm",
1021};
1022
1023DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1,
1024 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1025 CLK_SET_RATE_PARENT);
1026
1027static struct clk dss1_alwon_fck_3430es2;
1028
1029static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
1030 .hw = {
1031 .clk = &dss1_alwon_fck_3430es2,
1032 },
1033 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
1034 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1035 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1036 .clkdm_name = "dss_clkdm",
1037};
1038
1039DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2,
1040 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1041 CLK_SET_RATE_PARENT);
1042
1043static struct clk dss2_alwon_fck;
1044
1045static struct clk_hw_omap dss2_alwon_fck_hw = {
1046 .hw = {
1047 .clk = &dss2_alwon_fck,
1048 },
1049 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1050 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
1051 .clkdm_name = "dss_clkdm",
1052};
1053
1054DEFINE_STRUCT_CLK(dss2_alwon_fck, cpefuse_fck_parent_names, aes2_ick_ops);
1055
1056static struct clk dss_96m_fck;
1057
1058static struct clk_hw_omap dss_96m_fck_hw = {
1059 .hw = {
1060 .clk = &dss_96m_fck,
1061 },
1062 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1063 .enable_bit = OMAP3430_EN_TV_SHIFT,
1064 .clkdm_name = "dss_clkdm",
1065};
1066
1067DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1068
1069static struct clk dss_ick_3430es1;
1070
1071static struct clk_hw_omap dss_ick_3430es1_hw = {
1072 .hw = {
1073 .clk = &dss_ick_3430es1,
1074 },
1075 .ops = &clkhwops_iclk,
1076 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1077 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1078 .clkdm_name = "dss_clkdm",
1079};
1080
1081DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1082
1083static struct clk dss_ick_3430es2;
1084
1085static struct clk_hw_omap dss_ick_3430es2_hw = {
1086 .hw = {
1087 .clk = &dss_ick_3430es2,
1088 },
1089 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1090 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1091 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1092 .clkdm_name = "dss_clkdm",
1093};
1094
1095DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1096
1097static struct clk dss_tv_fck;
1098
1099static const char *dss_tv_fck_parent_names[] = {
1100 "omap_54m_fck",
1101};
1102
1103static struct clk_hw_omap dss_tv_fck_hw = {
1104 .hw = {
1105 .clk = &dss_tv_fck,
1106 },
1107 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1108 .enable_bit = OMAP3430_EN_TV_SHIFT,
1109 .clkdm_name = "dss_clkdm",
1110};
1111
1112DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1113
1114static struct clk emac_fck;
1115
1116static const char *emac_fck_parent_names[] = {
1117 "rmii_ck",
1118};
1119
1120static struct clk_hw_omap emac_fck_hw = {
1121 .hw = {
1122 .clk = &emac_fck,
1123 },
1124 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1125 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
1126};
1127
1128DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1129
1130static struct clk ipss_ick;
1131
1132static const char *ipss_ick_parent_names[] = {
1133 "core_l3_ick",
1134};
1135
1136static struct clk_hw_omap ipss_ick_hw = {
1137 .hw = {
1138 .clk = &ipss_ick,
1139 },
1140 .ops = &clkhwops_am35xx_ipss_wait,
1141 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1142 .enable_bit = AM35XX_EN_IPSS_SHIFT,
1143 .clkdm_name = "core_l3_clkdm",
1144};
1145
1146DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1147
1148static struct clk emac_ick;
1149
1150static const char *emac_ick_parent_names[] = {
1151 "ipss_ick",
1152};
1153
1154static struct clk_hw_omap emac_ick_hw = {
1155 .hw = {
1156 .clk = &emac_ick,
1157 },
1158 .ops = &clkhwops_am35xx_ipss_module_wait,
1159 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1160 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1161 .clkdm_name = "core_l3_clkdm",
1162};
1163
1164DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1165
1166static struct clk emu_core_alwon_ck;
1167
1168static const char *emu_core_alwon_ck_parent_names[] = {
1169 "dpll3_m3x2_ck",
1170};
1171
1172DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1173DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1174 core_l4_ick_ops);
1175
1176static struct clk emu_mpu_alwon_ck;
1177
1178static const char *emu_mpu_alwon_ck_parent_names[] = {
1179 "mpu_ck",
1180};
1181
1182DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1183DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1184
1185static struct clk emu_per_alwon_ck;
1186
1187static const char *emu_per_alwon_ck_parent_names[] = {
1188 "dpll4_m6x2_ck",
1189};
1190
1191DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1192DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1193 core_l4_ick_ops);
1194
1195static const char *emu_src_ck_parent_names[] = {
1196 "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1197};
1198
1199static const struct clksel_rate emu_src_sys_rates[] = {
1200 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1201 { .div = 0 },
1202};
1203
1204static const struct clksel_rate emu_src_core_rates[] = {
1205 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1206 { .div = 0 },
1207};
1208
1209static const struct clksel_rate emu_src_per_rates[] = {
1210 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1211 { .div = 0 },
1212};
1213
1214static const struct clksel_rate emu_src_mpu_rates[] = {
1215 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1216 { .div = 0 },
1217};
1218
1219static const struct clksel emu_src_clksel[] = {
1220 { .parent = &sys_ck, .rates = emu_src_sys_rates },
1221 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1222 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
1223 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
1224 { .parent = NULL },
1225};
1226
1227static const struct clk_ops emu_src_ck_ops = {
1228 .init = &omap2_init_clk_clkdm,
1229 .recalc_rate = &omap2_clksel_recalc,
1230 .get_parent = &omap2_clksel_find_parent_index,
1231 .set_parent = &omap2_clksel_set_parent,
1232 .enable = &omap2_clkops_enable_clkdm,
1233 .disable = &omap2_clkops_disable_clkdm,
1234};
1235
1236static struct clk emu_src_ck;
1237
1238static struct clk_hw_omap emu_src_ck_hw = {
1239 .hw = {
1240 .clk = &emu_src_ck,
1241 },
1242 .clksel = emu_src_clksel,
1243 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1244 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
1245 .clkdm_name = "emu_clkdm",
1246};
1247
1248DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1249
1250DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
1251 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1252 OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1253 CLK_DIVIDER_ONE_BASED, NULL);
1254
1255static struct clk fac_ick;
1256
1257static struct clk_hw_omap fac_ick_hw = {
1258 .hw = {
1259 .clk = &fac_ick,
1260 },
1261 .ops = &clkhwops_iclk_wait,
1262 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1263 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1264 .clkdm_name = "core_l4_clkdm",
1265};
1266
1267DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1268
1269static struct clk fshostusb_fck;
1270
1271static const char *fshostusb_fck_parent_names[] = {
1272 "core_48m_fck",
1273};
1274
1275static struct clk_hw_omap fshostusb_fck_hw = {
1276 .hw = {
1277 .clk = &fshostusb_fck,
1278 },
1279 .ops = &clkhwops_wait,
1280 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1281 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1282 .clkdm_name = "core_l4_clkdm",
1283};
1284
1285DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1286
1287static struct clk gfx_l3_ck;
1288
1289static struct clk_hw_omap gfx_l3_ck_hw = {
1290 .hw = {
1291 .clk = &gfx_l3_ck,
1292 },
1293 .ops = &clkhwops_wait,
1294 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1295 .enable_bit = OMAP_EN_GFX_SHIFT,
1296 .clkdm_name = "gfx_3430es1_clkdm",
1297};
1298
1299DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1300
1301DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
1302 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1303 OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1304 CLK_DIVIDER_ONE_BASED, NULL);
1305
1306static struct clk gfx_cg1_ck;
1307
1308static const char *gfx_cg1_ck_parent_names[] = {
1309 "gfx_l3_fck",
1310};
1311
1312static struct clk_hw_omap gfx_cg1_ck_hw = {
1313 .hw = {
1314 .clk = &gfx_cg1_ck,
1315 },
1316 .ops = &clkhwops_wait,
1317 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1318 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1319 .clkdm_name = "gfx_3430es1_clkdm",
1320};
1321
1322DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1323
1324static struct clk gfx_cg2_ck;
1325
1326static struct clk_hw_omap gfx_cg2_ck_hw = {
1327 .hw = {
1328 .clk = &gfx_cg2_ck,
1329 },
1330 .ops = &clkhwops_wait,
1331 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1332 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1333 .clkdm_name = "gfx_3430es1_clkdm",
1334};
1335
1336DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1337
1338static struct clk gfx_l3_ick;
1339
1340static const char *gfx_l3_ick_parent_names[] = {
1341 "gfx_l3_ck",
1342};
1343
1344DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1345DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1346
1347static struct clk wkup_32k_fck;
1348
1349static const char *wkup_32k_fck_parent_names[] = {
1350 "omap_32k_fck",
1351};
1352
1353DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1354DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1355
1356static struct clk gpio1_dbck;
1357
1358static const char *gpio1_dbck_parent_names[] = {
1359 "wkup_32k_fck",
1360};
1361
1362static struct clk_hw_omap gpio1_dbck_hw = {
1363 .hw = {
1364 .clk = &gpio1_dbck,
1365 },
1366 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1367 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1368 .clkdm_name = "wkup_clkdm",
1369};
1370
1371DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1372
1373static struct clk wkup_l4_ick;
1374
1375DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1376DEFINE_STRUCT_CLK(wkup_l4_ick, cpefuse_fck_parent_names, core_l4_ick_ops);
1377
1378static struct clk gpio1_ick;
1379
1380static const char *gpio1_ick_parent_names[] = {
1381 "wkup_l4_ick",
1382};
1383
1384static struct clk_hw_omap gpio1_ick_hw = {
1385 .hw = {
1386 .clk = &gpio1_ick,
1387 },
1388 .ops = &clkhwops_iclk_wait,
1389 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1390 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1391 .clkdm_name = "wkup_clkdm",
1392};
1393
1394DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1395
1396static struct clk per_32k_alwon_fck;
1397
1398DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1399DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1400 core_l4_ick_ops);
1401
1402static struct clk gpio2_dbck;
1403
1404static const char *gpio2_dbck_parent_names[] = {
1405 "per_32k_alwon_fck",
1406};
1407
1408static struct clk_hw_omap gpio2_dbck_hw = {
1409 .hw = {
1410 .clk = &gpio2_dbck,
1411 },
1412 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1413 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1414 .clkdm_name = "per_clkdm",
1415};
1416
1417DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1418
1419static struct clk per_l4_ick;
1420
1421DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1422DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1423
1424static struct clk gpio2_ick;
1425
1426static const char *gpio2_ick_parent_names[] = {
1427 "per_l4_ick",
1428};
1429
1430static struct clk_hw_omap gpio2_ick_hw = {
1431 .hw = {
1432 .clk = &gpio2_ick,
1433 },
1434 .ops = &clkhwops_iclk_wait,
1435 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1436 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1437 .clkdm_name = "per_clkdm",
1438};
1439
1440DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1441
1442static struct clk gpio3_dbck;
1443
1444static struct clk_hw_omap gpio3_dbck_hw = {
1445 .hw = {
1446 .clk = &gpio3_dbck,
1447 },
1448 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1449 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1450 .clkdm_name = "per_clkdm",
1451};
1452
1453DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1454
1455static struct clk gpio3_ick;
1456
1457static struct clk_hw_omap gpio3_ick_hw = {
1458 .hw = {
1459 .clk = &gpio3_ick,
1460 },
1461 .ops = &clkhwops_iclk_wait,
1462 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1463 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1464 .clkdm_name = "per_clkdm",
1465};
1466
1467DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1468
1469static struct clk gpio4_dbck;
1470
1471static struct clk_hw_omap gpio4_dbck_hw = {
1472 .hw = {
1473 .clk = &gpio4_dbck,
1474 },
1475 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1476 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1477 .clkdm_name = "per_clkdm",
1478};
1479
1480DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1481
1482static struct clk gpio4_ick;
1483
1484static struct clk_hw_omap gpio4_ick_hw = {
1485 .hw = {
1486 .clk = &gpio4_ick,
1487 },
1488 .ops = &clkhwops_iclk_wait,
1489 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1490 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1491 .clkdm_name = "per_clkdm",
1492};
1493
1494DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1495
1496static struct clk gpio5_dbck;
1497
1498static struct clk_hw_omap gpio5_dbck_hw = {
1499 .hw = {
1500 .clk = &gpio5_dbck,
1501 },
1502 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1503 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1504 .clkdm_name = "per_clkdm",
1505};
1506
1507DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1508
1509static struct clk gpio5_ick;
1510
1511static struct clk_hw_omap gpio5_ick_hw = {
1512 .hw = {
1513 .clk = &gpio5_ick,
1514 },
1515 .ops = &clkhwops_iclk_wait,
1516 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1517 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1518 .clkdm_name = "per_clkdm",
1519};
1520
1521DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1522
1523static struct clk gpio6_dbck;
1524
1525static struct clk_hw_omap gpio6_dbck_hw = {
1526 .hw = {
1527 .clk = &gpio6_dbck,
1528 },
1529 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1530 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1531 .clkdm_name = "per_clkdm",
1532};
1533
1534DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1535
1536static struct clk gpio6_ick;
1537
1538static struct clk_hw_omap gpio6_ick_hw = {
1539 .hw = {
1540 .clk = &gpio6_ick,
1541 },
1542 .ops = &clkhwops_iclk_wait,
1543 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1544 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1545 .clkdm_name = "per_clkdm",
1546};
1547
1548DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1549
1550static struct clk gpmc_fck;
1551
1552static struct clk_hw_omap gpmc_fck_hw = {
1553 .hw = {
1554 .clk = &gpmc_fck,
1555 },
1556 .flags = ENABLE_ON_INIT,
1557 .clkdm_name = "core_l3_clkdm",
1558};
1559
1560DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1561
1562static const struct clksel omap343x_gpt_clksel[] = {
1563 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1564 { .parent = &sys_ck, .rates = gpt_sys_rates },
1565 { .parent = NULL },
1566};
1567
1568static const char *gpt10_fck_parent_names[] = {
1569 "omap_32k_fck", "sys_ck",
1570};
1571
1572DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1573 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1574 OMAP3430_CLKSEL_GPT10_MASK,
1575 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1576 OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1577 gpt10_fck_parent_names, clkout2_src_ck_ops);
1578
1579static struct clk gpt10_ick;
1580
1581static struct clk_hw_omap gpt10_ick_hw = {
1582 .hw = {
1583 .clk = &gpt10_ick,
1584 },
1585 .ops = &clkhwops_iclk_wait,
1586 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1587 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1588 .clkdm_name = "core_l4_clkdm",
1589};
1590
1591DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1592
1593DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1594 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1595 OMAP3430_CLKSEL_GPT11_MASK,
1596 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1597 OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1598 gpt10_fck_parent_names, clkout2_src_ck_ops);
1599
1600static struct clk gpt11_ick;
1601
1602static struct clk_hw_omap gpt11_ick_hw = {
1603 .hw = {
1604 .clk = &gpt11_ick,
1605 },
1606 .ops = &clkhwops_iclk_wait,
1607 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1608 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1609 .clkdm_name = "core_l4_clkdm",
1610};
1611
1612DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1613
1614static struct clk gpt12_fck;
1615
1616static const char *gpt12_fck_parent_names[] = {
1617 "secure_32k_fck",
1618};
1619
1620DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1621DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1622
1623static struct clk gpt12_ick;
1624
1625static struct clk_hw_omap gpt12_ick_hw = {
1626 .hw = {
1627 .clk = &gpt12_ick,
1628 },
1629 .ops = &clkhwops_iclk_wait,
1630 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1631 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
1632 .clkdm_name = "wkup_clkdm",
1633};
1634
1635DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1636
1637DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1638 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1639 OMAP3430_CLKSEL_GPT1_MASK,
1640 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1641 OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1642 gpt10_fck_parent_names, clkout2_src_ck_ops);
1643
1644static struct clk gpt1_ick;
1645
1646static struct clk_hw_omap gpt1_ick_hw = {
1647 .hw = {
1648 .clk = &gpt1_ick,
1649 },
1650 .ops = &clkhwops_iclk_wait,
1651 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1652 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
1653 .clkdm_name = "wkup_clkdm",
1654};
1655
1656DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1657
1658DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1659 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1660 OMAP3430_CLKSEL_GPT2_MASK,
1661 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1662 OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1663 gpt10_fck_parent_names, clkout2_src_ck_ops);
1664
1665static struct clk gpt2_ick;
1666
1667static struct clk_hw_omap gpt2_ick_hw = {
1668 .hw = {
1669 .clk = &gpt2_ick,
1670 },
1671 .ops = &clkhwops_iclk_wait,
1672 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1673 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
1674 .clkdm_name = "per_clkdm",
1675};
1676
1677DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1678
1679DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1680 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1681 OMAP3430_CLKSEL_GPT3_MASK,
1682 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1683 OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1684 gpt10_fck_parent_names, clkout2_src_ck_ops);
1685
1686static struct clk gpt3_ick;
1687
1688static struct clk_hw_omap gpt3_ick_hw = {
1689 .hw = {
1690 .clk = &gpt3_ick,
1691 },
1692 .ops = &clkhwops_iclk_wait,
1693 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1694 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
1695 .clkdm_name = "per_clkdm",
1696};
1697
1698DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1699
1700DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1701 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1702 OMAP3430_CLKSEL_GPT4_MASK,
1703 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1704 OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1705 gpt10_fck_parent_names, clkout2_src_ck_ops);
1706
1707static struct clk gpt4_ick;
1708
1709static struct clk_hw_omap gpt4_ick_hw = {
1710 .hw = {
1711 .clk = &gpt4_ick,
1712 },
1713 .ops = &clkhwops_iclk_wait,
1714 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1715 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
1716 .clkdm_name = "per_clkdm",
1717};
1718
1719DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1720
1721DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1722 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1723 OMAP3430_CLKSEL_GPT5_MASK,
1724 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1725 OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1726 gpt10_fck_parent_names, clkout2_src_ck_ops);
1727
1728static struct clk gpt5_ick;
1729
1730static struct clk_hw_omap gpt5_ick_hw = {
1731 .hw = {
1732 .clk = &gpt5_ick,
1733 },
1734 .ops = &clkhwops_iclk_wait,
1735 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1736 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
1737 .clkdm_name = "per_clkdm",
1738};
1739
1740DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1741
1742DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1743 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1744 OMAP3430_CLKSEL_GPT6_MASK,
1745 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1746 OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1747 gpt10_fck_parent_names, clkout2_src_ck_ops);
1748
1749static struct clk gpt6_ick;
1750
1751static struct clk_hw_omap gpt6_ick_hw = {
1752 .hw = {
1753 .clk = &gpt6_ick,
1754 },
1755 .ops = &clkhwops_iclk_wait,
1756 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1757 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
1758 .clkdm_name = "per_clkdm",
1759};
1760
1761DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1762
1763DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1764 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1765 OMAP3430_CLKSEL_GPT7_MASK,
1766 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1767 OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1768 gpt10_fck_parent_names, clkout2_src_ck_ops);
1769
1770static struct clk gpt7_ick;
1771
1772static struct clk_hw_omap gpt7_ick_hw = {
1773 .hw = {
1774 .clk = &gpt7_ick,
1775 },
1776 .ops = &clkhwops_iclk_wait,
1777 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1778 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
1779 .clkdm_name = "per_clkdm",
1780};
1781
1782DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1783
1784DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1785 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1786 OMAP3430_CLKSEL_GPT8_MASK,
1787 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1788 OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1789 gpt10_fck_parent_names, clkout2_src_ck_ops);
1790
1791static struct clk gpt8_ick;
1792
1793static struct clk_hw_omap gpt8_ick_hw = {
1794 .hw = {
1795 .clk = &gpt8_ick,
1796 },
1797 .ops = &clkhwops_iclk_wait,
1798 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1799 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
1800 .clkdm_name = "per_clkdm",
1801};
1802
1803DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1804
1805DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1806 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1807 OMAP3430_CLKSEL_GPT9_MASK,
1808 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1809 OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1810 gpt10_fck_parent_names, clkout2_src_ck_ops);
1811
1812static struct clk gpt9_ick;
1813
1814static struct clk_hw_omap gpt9_ick_hw = {
1815 .hw = {
1816 .clk = &gpt9_ick,
1817 },
1818 .ops = &clkhwops_iclk_wait,
1819 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1820 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
1821 .clkdm_name = "per_clkdm",
1822};
1823
1824DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1825
1826static struct clk hdq_fck;
1827
1828static const char *hdq_fck_parent_names[] = {
1829 "core_12m_fck",
1830};
1831
1832static struct clk_hw_omap hdq_fck_hw = {
1833 .hw = {
1834 .clk = &hdq_fck,
1835 },
1836 .ops = &clkhwops_wait,
1837 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1838 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1839 .clkdm_name = "core_l4_clkdm",
1840};
1841
1842DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1843
1844static struct clk hdq_ick;
1845
1846static struct clk_hw_omap hdq_ick_hw = {
1847 .hw = {
1848 .clk = &hdq_ick,
1849 },
1850 .ops = &clkhwops_iclk_wait,
1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1852 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1853 .clkdm_name = "core_l4_clkdm",
1854};
1855
1856DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1857
1858static struct clk hecc_ck;
1859
1860static struct clk_hw_omap hecc_ck_hw = {
1861 .hw = {
1862 .clk = &hecc_ck,
1863 },
1864 .ops = &clkhwops_am35xx_ipss_module_wait,
1865 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1866 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
1867 .clkdm_name = "core_l3_clkdm",
1868};
1869
1870DEFINE_STRUCT_CLK(hecc_ck, cpefuse_fck_parent_names, aes2_ick_ops);
1871
1872static struct clk hsotgusb_fck_am35xx;
1873
1874static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1875 .hw = {
1876 .clk = &hsotgusb_fck_am35xx,
1877 },
1878 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1879 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
1880 .clkdm_name = "core_l3_clkdm",
1881};
1882
1883DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, cpefuse_fck_parent_names, aes2_ick_ops);
1884
1885static struct clk hsotgusb_ick_3430es1;
1886
1887static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1888 .hw = {
1889 .clk = &hsotgusb_ick_3430es1,
1890 },
1891 .ops = &clkhwops_iclk,
1892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1893 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1894 .clkdm_name = "core_l3_clkdm",
1895};
1896
1897DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1898
1899static struct clk hsotgusb_ick_3430es2;
1900
1901static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1902 .hw = {
1903 .clk = &hsotgusb_ick_3430es2,
1904 },
1905 .ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1907 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1908 .clkdm_name = "core_l3_clkdm",
1909};
1910
1911DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1912
1913static struct clk hsotgusb_ick_am35xx;
1914
1915static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1916 .hw = {
1917 .clk = &hsotgusb_ick_am35xx,
1918 },
1919 .ops = &clkhwops_am35xx_ipss_module_wait,
1920 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1921 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1922 .clkdm_name = "core_l3_clkdm",
1923};
1924
1925DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1926
1927static struct clk i2c1_fck;
1928
1929static struct clk_hw_omap i2c1_fck_hw = {
1930 .hw = {
1931 .clk = &i2c1_fck,
1932 },
1933 .ops = &clkhwops_wait,
1934 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1935 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1936 .clkdm_name = "core_l4_clkdm",
1937};
1938
1939DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1940
1941static struct clk i2c1_ick;
1942
1943static struct clk_hw_omap i2c1_ick_hw = {
1944 .hw = {
1945 .clk = &i2c1_ick,
1946 },
1947 .ops = &clkhwops_iclk_wait,
1948 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1950 .clkdm_name = "core_l4_clkdm",
1951};
1952
1953DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1954
1955static struct clk i2c2_fck;
1956
1957static struct clk_hw_omap i2c2_fck_hw = {
1958 .hw = {
1959 .clk = &i2c2_fck,
1960 },
1961 .ops = &clkhwops_wait,
1962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1963 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1964 .clkdm_name = "core_l4_clkdm",
1965};
1966
1967DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1968
1969static struct clk i2c2_ick;
1970
1971static struct clk_hw_omap i2c2_ick_hw = {
1972 .hw = {
1973 .clk = &i2c2_ick,
1974 },
1975 .ops = &clkhwops_iclk_wait,
1976 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1977 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1978 .clkdm_name = "core_l4_clkdm",
1979};
1980
1981DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
1982
1983static struct clk i2c3_fck;
1984
1985static struct clk_hw_omap i2c3_fck_hw = {
1986 .hw = {
1987 .clk = &i2c3_fck,
1988 },
1989 .ops = &clkhwops_wait,
1990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1991 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1992 .clkdm_name = "core_l4_clkdm",
1993};
1994
1995DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1996
1997static struct clk i2c3_ick;
1998
1999static struct clk_hw_omap i2c3_ick_hw = {
2000 .hw = {
2001 .clk = &i2c3_ick,
2002 },
2003 .ops = &clkhwops_iclk_wait,
2004 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2005 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2006 .clkdm_name = "core_l4_clkdm",
2007};
2008
2009DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
2010
2011static struct clk icr_ick;
2012
2013static struct clk_hw_omap icr_ick_hw = {
2014 .hw = {
2015 .clk = &icr_ick,
2016 },
2017 .ops = &clkhwops_iclk_wait,
2018 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2019 .enable_bit = OMAP3430_EN_ICR_SHIFT,
2020 .clkdm_name = "core_l4_clkdm",
2021};
2022
2023DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
2024
2025static struct clk iva2_ck;
2026
2027static const char *iva2_ck_parent_names[] = {
2028 "dpll2_m2_ck",
2029};
2030
2031static struct clk_hw_omap iva2_ck_hw = {
2032 .hw = {
2033 .clk = &iva2_ck,
2034 },
2035 .ops = &clkhwops_wait,
2036 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
2037 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
2038 .clkdm_name = "iva2_clkdm",
2039};
2040
2041DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
2042
2043static struct clk mad2d_ick;
2044
2045static struct clk_hw_omap mad2d_ick_hw = {
2046 .hw = {
2047 .clk = &mad2d_ick,
2048 },
2049 .ops = &clkhwops_iclk_wait,
2050 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2051 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
2052 .clkdm_name = "d2d_clkdm",
2053};
2054
2055DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2056
2057static struct clk mailboxes_ick;
2058
2059static struct clk_hw_omap mailboxes_ick_hw = {
2060 .hw = {
2061 .clk = &mailboxes_ick,
2062 },
2063 .ops = &clkhwops_iclk_wait,
2064 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2065 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2066 .clkdm_name = "core_l4_clkdm",
2067};
2068
2069DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2070
2071static const struct clksel_rate common_mcbsp_96m_rates[] = {
2072 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2073 { .div = 0 }
2074};
2075
2076static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2077 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2078 { .div = 0 }
2079};
2080
2081static const struct clksel mcbsp_15_clksel[] = {
2082 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2083 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2084 { .parent = NULL },
2085};
2086
2087static const char *mcbsp1_fck_parent_names[] = {
2088 "core_96m_fck", "mcbsp_clks",
2089};
2090
2091DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2092 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2093 OMAP2_MCBSP1_CLKS_MASK,
2094 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2095 OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2096 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2097
2098static struct clk mcbsp1_ick;
2099
2100static struct clk_hw_omap mcbsp1_ick_hw = {
2101 .hw = {
2102 .clk = &mcbsp1_ick,
2103 },
2104 .ops = &clkhwops_iclk_wait,
2105 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2106 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2107 .clkdm_name = "core_l4_clkdm",
2108};
2109
2110DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2111
2112static struct clk per_96m_fck;
2113
2114DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2115DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2116
2117static const struct clksel mcbsp_234_clksel[] = {
2118 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2119 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2120 { .parent = NULL },
2121};
2122
2123static const char *mcbsp2_fck_parent_names[] = {
2124 "per_96m_fck", "mcbsp_clks",
2125};
2126
2127DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2128 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2129 OMAP2_MCBSP2_CLKS_MASK,
2130 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2131 OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2132 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2133
2134static struct clk mcbsp2_ick;
2135
2136static struct clk_hw_omap mcbsp2_ick_hw = {
2137 .hw = {
2138 .clk = &mcbsp2_ick,
2139 },
2140 .ops = &clkhwops_iclk_wait,
2141 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2142 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2143 .clkdm_name = "per_clkdm",
2144};
2145
2146DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2147
2148DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2149 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2150 OMAP2_MCBSP3_CLKS_MASK,
2151 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2152 OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2153 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2154
2155static struct clk mcbsp3_ick;
2156
2157static struct clk_hw_omap mcbsp3_ick_hw = {
2158 .hw = {
2159 .clk = &mcbsp3_ick,
2160 },
2161 .ops = &clkhwops_iclk_wait,
2162 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2163 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2164 .clkdm_name = "per_clkdm",
2165};
2166
2167DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2168
2169DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2170 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2171 OMAP2_MCBSP4_CLKS_MASK,
2172 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2173 OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2174 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2175
2176static struct clk mcbsp4_ick;
2177
2178static struct clk_hw_omap mcbsp4_ick_hw = {
2179 .hw = {
2180 .clk = &mcbsp4_ick,
2181 },
2182 .ops = &clkhwops_iclk_wait,
2183 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2184 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2185 .clkdm_name = "per_clkdm",
2186};
2187
2188DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2189
2190DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2191 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2192 OMAP2_MCBSP5_CLKS_MASK,
2193 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2194 OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2195 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2196
2197static struct clk mcbsp5_ick;
2198
2199static struct clk_hw_omap mcbsp5_ick_hw = {
2200 .hw = {
2201 .clk = &mcbsp5_ick,
2202 },
2203 .ops = &clkhwops_iclk_wait,
2204 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2205 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2206 .clkdm_name = "core_l4_clkdm",
2207};
2208
2209DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2210
2211static struct clk mcspi1_fck;
2212
2213static struct clk_hw_omap mcspi1_fck_hw = {
2214 .hw = {
2215 .clk = &mcspi1_fck,
2216 },
2217 .ops = &clkhwops_wait,
2218 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2219 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2220 .clkdm_name = "core_l4_clkdm",
2221};
2222
2223DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2224
2225static struct clk mcspi1_ick;
2226
2227static struct clk_hw_omap mcspi1_ick_hw = {
2228 .hw = {
2229 .clk = &mcspi1_ick,
2230 },
2231 .ops = &clkhwops_iclk_wait,
2232 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2233 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2234 .clkdm_name = "core_l4_clkdm",
2235};
2236
2237DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2238
2239static struct clk mcspi2_fck;
2240
2241static struct clk_hw_omap mcspi2_fck_hw = {
2242 .hw = {
2243 .clk = &mcspi2_fck,
2244 },
2245 .ops = &clkhwops_wait,
2246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2247 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2248 .clkdm_name = "core_l4_clkdm",
2249};
2250
2251DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2252
2253static struct clk mcspi2_ick;
2254
2255static struct clk_hw_omap mcspi2_ick_hw = {
2256 .hw = {
2257 .clk = &mcspi2_ick,
2258 },
2259 .ops = &clkhwops_iclk_wait,
2260 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2261 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2262 .clkdm_name = "core_l4_clkdm",
2263};
2264
2265DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2266
2267static struct clk mcspi3_fck;
2268
2269static struct clk_hw_omap mcspi3_fck_hw = {
2270 .hw = {
2271 .clk = &mcspi3_fck,
2272 },
2273 .ops = &clkhwops_wait,
2274 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2275 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2276 .clkdm_name = "core_l4_clkdm",
2277};
2278
2279DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2280
2281static struct clk mcspi3_ick;
2282
2283static struct clk_hw_omap mcspi3_ick_hw = {
2284 .hw = {
2285 .clk = &mcspi3_ick,
2286 },
2287 .ops = &clkhwops_iclk_wait,
2288 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2289 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2290 .clkdm_name = "core_l4_clkdm",
2291};
2292
2293DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2294
2295static struct clk mcspi4_fck;
2296
2297static struct clk_hw_omap mcspi4_fck_hw = {
2298 .hw = {
2299 .clk = &mcspi4_fck,
2300 },
2301 .ops = &clkhwops_wait,
2302 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2303 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2304 .clkdm_name = "core_l4_clkdm",
2305};
2306
2307DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2308
2309static struct clk mcspi4_ick;
2310
2311static struct clk_hw_omap mcspi4_ick_hw = {
2312 .hw = {
2313 .clk = &mcspi4_ick,
2314 },
2315 .ops = &clkhwops_iclk_wait,
2316 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2317 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2318 .clkdm_name = "core_l4_clkdm",
2319};
2320
2321DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2322
2323static struct clk mmchs1_fck;
2324
2325static struct clk_hw_omap mmchs1_fck_hw = {
2326 .hw = {
2327 .clk = &mmchs1_fck,
2328 },
2329 .ops = &clkhwops_wait,
2330 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2331 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2332 .clkdm_name = "core_l4_clkdm",
2333};
2334
2335DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2336
2337static struct clk mmchs1_ick;
2338
2339static struct clk_hw_omap mmchs1_ick_hw = {
2340 .hw = {
2341 .clk = &mmchs1_ick,
2342 },
2343 .ops = &clkhwops_iclk_wait,
2344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2345 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2346 .clkdm_name = "core_l4_clkdm",
2347};
2348
2349DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2350
2351static struct clk mmchs2_fck;
2352
2353static struct clk_hw_omap mmchs2_fck_hw = {
2354 .hw = {
2355 .clk = &mmchs2_fck,
2356 },
2357 .ops = &clkhwops_wait,
2358 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2359 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2360 .clkdm_name = "core_l4_clkdm",
2361};
2362
2363DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2364
2365static struct clk mmchs2_ick;
2366
2367static struct clk_hw_omap mmchs2_ick_hw = {
2368 .hw = {
2369 .clk = &mmchs2_ick,
2370 },
2371 .ops = &clkhwops_iclk_wait,
2372 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2373 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2374 .clkdm_name = "core_l4_clkdm",
2375};
2376
2377DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2378
2379static struct clk mmchs3_fck;
2380
2381static struct clk_hw_omap mmchs3_fck_hw = {
2382 .hw = {
2383 .clk = &mmchs3_fck,
2384 },
2385 .ops = &clkhwops_wait,
2386 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2387 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2388 .clkdm_name = "core_l4_clkdm",
2389};
2390
2391DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2392
2393static struct clk mmchs3_ick;
2394
2395static struct clk_hw_omap mmchs3_ick_hw = {
2396 .hw = {
2397 .clk = &mmchs3_ick,
2398 },
2399 .ops = &clkhwops_iclk_wait,
2400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2401 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2402 .clkdm_name = "core_l4_clkdm",
2403};
2404
2405DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2406
2407static struct clk modem_fck;
2408
2409static struct clk_hw_omap modem_fck_hw = {
2410 .hw = {
2411 .clk = &modem_fck,
2412 },
2413 .ops = &clkhwops_iclk_wait,
2414 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2415 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
2416 .clkdm_name = "d2d_clkdm",
2417};
2418
2419DEFINE_STRUCT_CLK(modem_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2420
2421static struct clk mspro_fck;
2422
2423static struct clk_hw_omap mspro_fck_hw = {
2424 .hw = {
2425 .clk = &mspro_fck,
2426 },
2427 .ops = &clkhwops_wait,
2428 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2429 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2430 .clkdm_name = "core_l4_clkdm",
2431};
2432
2433DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2434
2435static struct clk mspro_ick;
2436
2437static struct clk_hw_omap mspro_ick_hw = {
2438 .hw = {
2439 .clk = &mspro_ick,
2440 },
2441 .ops = &clkhwops_iclk_wait,
2442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2443 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2444 .clkdm_name = "core_l4_clkdm",
2445};
2446
2447DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2448
2449static struct clk omap_192m_alwon_fck;
2450
2451DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2452DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2453 core_ck_ops);
2454
2455static struct clk omap_32ksync_ick;
2456
2457static struct clk_hw_omap omap_32ksync_ick_hw = {
2458 .hw = {
2459 .clk = &omap_32ksync_ick,
2460 },
2461 .ops = &clkhwops_iclk_wait,
2462 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2463 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2464 .clkdm_name = "wkup_clkdm",
2465};
2466
2467DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2468
2469static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2470 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2471 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2472 { .div = 0 }
2473};
2474
2475static const struct clksel omap_96m_alwon_fck_clksel[] = {
2476 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2477 { .parent = NULL }
2478};
2479
2480static struct clk omap_96m_alwon_fck_3630;
2481
2482static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2483 "omap_192m_alwon_fck",
2484};
2485
2486static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2487 .set_rate = &omap2_clksel_set_rate,
2488 .recalc_rate = &omap2_clksel_recalc,
2489 .round_rate = &omap2_clksel_round_rate,
2490};
2491
2492static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2493 .hw = {
2494 .clk = &omap_96m_alwon_fck_3630,
2495 },
2496 .clksel = omap_96m_alwon_fck_clksel,
2497 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2498 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
2499};
2500
2501static struct clk omap_96m_alwon_fck_3630 = {
2502 .name = "omap_96m_alwon_fck",
2503 .hw = &omap_96m_alwon_fck_3630_hw.hw,
2504 .parent_names = omap_96m_alwon_fck_3630_parent_names,
2505 .num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2506 .ops = &omap_96m_alwon_fck_3630_ops,
2507};
2508
2509static struct clk omapctrl_ick;
2510
2511static struct clk_hw_omap omapctrl_ick_hw = {
2512 .hw = {
2513 .clk = &omapctrl_ick,
2514 },
2515 .ops = &clkhwops_iclk_wait,
2516 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2517 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2518 .flags = ENABLE_ON_INIT,
2519 .clkdm_name = "core_l4_clkdm",
2520};
2521
2522DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2523
2524DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
2525 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2526 OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2527 CLK_DIVIDER_ONE_BASED, NULL);
2528
2529DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
2530 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2531 OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2532 CLK_DIVIDER_ONE_BASED, NULL);
2533
2534static struct clk per_48m_fck;
2535
2536DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2537DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2538
2539static struct clk security_l3_ick;
2540
2541DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2542DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2543
2544static struct clk pka_ick;
2545
2546static const char *pka_ick_parent_names[] = {
2547 "security_l3_ick",
2548};
2549
2550static struct clk_hw_omap pka_ick_hw = {
2551 .hw = {
2552 .clk = &pka_ick,
2553 },
2554 .ops = &clkhwops_iclk_wait,
2555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2556 .enable_bit = OMAP3430_EN_PKA_SHIFT,
2557};
2558
2559DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2560
2561DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
2562 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2563 OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2564 CLK_DIVIDER_ONE_BASED, NULL);
2565
2566static struct clk rng_ick;
2567
2568static struct clk_hw_omap rng_ick_hw = {
2569 .hw = {
2570 .clk = &rng_ick,
2571 },
2572 .ops = &clkhwops_iclk_wait,
2573 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2574 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2575};
2576
2577DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2578
2579static struct clk sad2d_ick;
2580
2581static struct clk_hw_omap sad2d_ick_hw = {
2582 .hw = {
2583 .clk = &sad2d_ick,
2584 },
2585 .ops = &clkhwops_iclk_wait,
2586 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2587 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
2588 .clkdm_name = "d2d_clkdm",
2589};
2590
2591DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2592
2593static struct clk sdrc_ick;
2594
2595static struct clk_hw_omap sdrc_ick_hw = {
2596 .hw = {
2597 .clk = &sdrc_ick,
2598 },
2599 .ops = &clkhwops_wait,
2600 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2601 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
2602 .flags = ENABLE_ON_INIT,
2603 .clkdm_name = "core_l3_clkdm",
2604};
2605
2606DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2607
2608static const struct clksel_rate sgx_core_rates[] = {
2609 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2610 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2611 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2612 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2613 { .div = 0 }
2614};
2615
2616static const struct clksel_rate sgx_96m_rates[] = {
2617 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2618 { .div = 0 }
2619};
2620
2621static const struct clksel_rate sgx_192m_rates[] = {
2622 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2623 { .div = 0 }
2624};
2625
2626static const struct clksel_rate sgx_corex2_rates[] = {
2627 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2628 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2629 { .div = 0 }
2630};
2631
2632static const struct clksel sgx_clksel[] = {
2633 { .parent = &core_ck, .rates = sgx_core_rates },
2634 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2635 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2636 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2637 { .parent = NULL },
2638};
2639
2640static const char *sgx_fck_parent_names[] = {
2641 "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2642};
2643
2644static struct clk sgx_fck;
2645
2646static const struct clk_ops sgx_fck_ops = {
2647 .init = &omap2_init_clk_clkdm,
2648 .enable = &omap2_dflt_clk_enable,
2649 .disable = &omap2_dflt_clk_disable,
2650 .is_enabled = &omap2_dflt_clk_is_enabled,
2651 .recalc_rate = &omap2_clksel_recalc,
2652 .set_rate = &omap2_clksel_set_rate,
2653 .round_rate = &omap2_clksel_round_rate,
2654 .get_parent = &omap2_clksel_find_parent_index,
2655 .set_parent = &omap2_clksel_set_parent,
2656};
2657
2658DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2659 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2660 OMAP3430ES2_CLKSEL_SGX_MASK,
2661 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2662 OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2663 &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2664
2665static struct clk sgx_ick;
2666
2667static struct clk_hw_omap sgx_ick_hw = {
2668 .hw = {
2669 .clk = &sgx_ick,
2670 },
2671 .ops = &clkhwops_wait,
2672 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2673 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2674 .clkdm_name = "sgx_clkdm",
2675};
2676
2677DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2678
2679static struct clk sha11_ick;
2680
2681static struct clk_hw_omap sha11_ick_hw = {
2682 .hw = {
2683 .clk = &sha11_ick,
2684 },
2685 .ops = &clkhwops_iclk_wait,
2686 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2687 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2688};
2689
2690DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2691
2692static struct clk sha12_ick;
2693
2694static struct clk_hw_omap sha12_ick_hw = {
2695 .hw = {
2696 .clk = &sha12_ick,
2697 },
2698 .ops = &clkhwops_iclk_wait,
2699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2700 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
2701 .clkdm_name = "core_l4_clkdm",
2702};
2703
2704DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2705
2706static struct clk sr1_fck;
2707
2708static struct clk_hw_omap sr1_fck_hw = {
2709 .hw = {
2710 .clk = &sr1_fck,
2711 },
2712 .ops = &clkhwops_wait,
2713 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2714 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2715 .clkdm_name = "wkup_clkdm",
2716};
2717
2718DEFINE_STRUCT_CLK(sr1_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2719
2720static struct clk sr2_fck;
2721
2722static struct clk_hw_omap sr2_fck_hw = {
2723 .hw = {
2724 .clk = &sr2_fck,
2725 },
2726 .ops = &clkhwops_wait,
2727 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2728 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2729 .clkdm_name = "wkup_clkdm",
2730};
2731
2732DEFINE_STRUCT_CLK(sr2_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2733
2734static struct clk sr_l4_ick;
2735
2736DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2737DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2738
2739static struct clk ssi_l4_ick;
2740
2741DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2742DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2743
2744static struct clk ssi_ick_3430es1;
2745
2746static const char *ssi_ick_3430es1_parent_names[] = {
2747 "ssi_l4_ick",
2748};
2749
2750static struct clk_hw_omap ssi_ick_3430es1_hw = {
2751 .hw = {
2752 .clk = &ssi_ick_3430es1,
2753 },
2754 .ops = &clkhwops_iclk,
2755 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2756 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2757 .clkdm_name = "core_l4_clkdm",
2758};
2759
2760DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2761
2762static struct clk ssi_ick_3430es2;
2763
2764static struct clk_hw_omap ssi_ick_3430es2_hw = {
2765 .hw = {
2766 .clk = &ssi_ick_3430es2,
2767 },
2768 .ops = &clkhwops_omap3430es2_iclk_ssi_wait,
2769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2770 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2771 .clkdm_name = "core_l4_clkdm",
2772};
2773
2774DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2775
2776static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2777 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2778 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2779 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2780 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2781 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2782 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2783 { .div = 0 }
2784};
2785
2786static const struct clksel ssi_ssr_clksel[] = {
2787 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2788 { .parent = NULL },
2789};
2790
2791static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2792 "corex2_fck",
2793};
2794
2795static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2796 .init = &omap2_init_clk_clkdm,
2797 .enable = &omap2_dflt_clk_enable,
2798 .disable = &omap2_dflt_clk_disable,
2799 .is_enabled = &omap2_dflt_clk_is_enabled,
2800 .recalc_rate = &omap2_clksel_recalc,
2801 .set_rate = &omap2_clksel_set_rate,
2802 .round_rate = &omap2_clksel_round_rate,
2803};
2804
2805DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2806 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2807 OMAP3430_CLKSEL_SSI_MASK,
2808 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2809 OMAP3430_EN_SSI_SHIFT,
2810 NULL, ssi_ssr_fck_3430es1_parent_names,
2811 ssi_ssr_fck_3430es1_ops);
2812
2813DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2814 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2815 OMAP3430_CLKSEL_SSI_MASK,
2816 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2817 OMAP3430_EN_SSI_SHIFT,
2818 NULL, ssi_ssr_fck_3430es1_parent_names,
2819 ssi_ssr_fck_3430es1_ops);
2820
2821DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2822 &ssi_ssr_fck_3430es1, 0x0, 1, 2);
2823
2824DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2825 &ssi_ssr_fck_3430es2, 0x0, 1, 2);
2826
2827static struct clk sys_clkout1;
2828
2829static const char *sys_clkout1_parent_names[] = {
2830 "osc_sys_ck",
2831};
2832
2833static struct clk_hw_omap sys_clkout1_hw = {
2834 .hw = {
2835 .clk = &sys_clkout1,
2836 },
2837 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
2838 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
2839};
2840
2841DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2842
2843DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
2844 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2845 OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2846
2847DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2848 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2849 OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2850 0x0, NULL);
2851
2852DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
2853 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2854 OMAP3430_CLKSEL_TRACECLK_SHIFT,
2855 OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2856
2857static struct clk ts_fck;
2858
2859static struct clk_hw_omap ts_fck_hw = {
2860 .hw = {
2861 .clk = &ts_fck,
2862 },
2863 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2864 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
2865 .clkdm_name = "core_l4_clkdm",
2866};
2867
2868DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2869
2870static struct clk uart1_fck;
2871
2872static struct clk_hw_omap uart1_fck_hw = {
2873 .hw = {
2874 .clk = &uart1_fck,
2875 },
2876 .ops = &clkhwops_wait,
2877 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2878 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2879 .clkdm_name = "core_l4_clkdm",
2880};
2881
2882DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2883
2884static struct clk uart1_ick;
2885
2886static struct clk_hw_omap uart1_ick_hw = {
2887 .hw = {
2888 .clk = &uart1_ick,
2889 },
2890 .ops = &clkhwops_iclk_wait,
2891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2892 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2893 .clkdm_name = "core_l4_clkdm",
2894};
2895
2896DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2897
2898static struct clk uart2_fck;
2899
2900static struct clk_hw_omap uart2_fck_hw = {
2901 .hw = {
2902 .clk = &uart2_fck,
2903 },
2904 .ops = &clkhwops_wait,
2905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2906 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2907 .clkdm_name = "core_l4_clkdm",
2908};
2909
2910DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2911
2912static struct clk uart2_ick;
2913
2914static struct clk_hw_omap uart2_ick_hw = {
2915 .hw = {
2916 .clk = &uart2_ick,
2917 },
2918 .ops = &clkhwops_iclk_wait,
2919 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2920 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2921 .clkdm_name = "core_l4_clkdm",
2922};
2923
2924DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2925
2926static struct clk uart3_fck;
2927
2928static const char *uart3_fck_parent_names[] = {
2929 "per_48m_fck",
2930};
2931
2932static struct clk_hw_omap uart3_fck_hw = {
2933 .hw = {
2934 .clk = &uart3_fck,
2935 },
2936 .ops = &clkhwops_wait,
2937 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2938 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2939 .clkdm_name = "per_clkdm",
2940};
2941
2942DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2943
2944static struct clk uart3_ick;
2945
2946static struct clk_hw_omap uart3_ick_hw = {
2947 .hw = {
2948 .clk = &uart3_ick,
2949 },
2950 .ops = &clkhwops_iclk_wait,
2951 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2952 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2953 .clkdm_name = "per_clkdm",
2954};
2955
2956DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2957
2958static struct clk uart4_fck;
2959
2960static struct clk_hw_omap uart4_fck_hw = {
2961 .hw = {
2962 .clk = &uart4_fck,
2963 },
2964 .ops = &clkhwops_wait,
2965 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2966 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2967 .clkdm_name = "per_clkdm",
2968};
2969
2970DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
2971
2972static struct clk uart4_fck_am35xx;
2973
2974static struct clk_hw_omap uart4_fck_am35xx_hw = {
2975 .hw = {
2976 .clk = &uart4_fck_am35xx,
2977 },
2978 .ops = &clkhwops_wait,
2979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2980 .enable_bit = AM35XX_EN_UART4_SHIFT,
2981 .clkdm_name = "core_l4_clkdm",
2982};
2983
2984DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
2985
2986static struct clk uart4_ick;
2987
2988static struct clk_hw_omap uart4_ick_hw = {
2989 .hw = {
2990 .clk = &uart4_ick,
2991 },
2992 .ops = &clkhwops_iclk_wait,
2993 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2994 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2995 .clkdm_name = "per_clkdm",
2996};
2997
2998DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2999
3000static struct clk uart4_ick_am35xx;
3001
3002static struct clk_hw_omap uart4_ick_am35xx_hw = {
3003 .hw = {
3004 .clk = &uart4_ick_am35xx,
3005 },
3006 .ops = &clkhwops_iclk_wait,
3007 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3008 .enable_bit = AM35XX_EN_UART4_SHIFT,
3009 .clkdm_name = "core_l4_clkdm",
3010};
3011
3012DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
3013
3014static const struct clksel_rate div2_rates[] = {
3015 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3016 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3017 { .div = 0 }
3018};
3019
3020static const struct clksel usb_l4_clksel[] = {
3021 { .parent = &l4_ick, .rates = div2_rates },
3022 { .parent = NULL },
3023};
3024
3025static const char *usb_l4_ick_parent_names[] = {
3026 "l4_ick",
3027};
3028
3029DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
3030 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
3031 OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
3032 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3033 OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
3034 &clkhwops_iclk_wait, usb_l4_ick_parent_names,
3035 ssi_ssr_fck_3430es1_ops);
3036
3037static struct clk usbhost_120m_fck;
3038
3039static const char *usbhost_120m_fck_parent_names[] = {
3040 "dpll5_m2_ck",
3041};
3042
3043static struct clk_hw_omap usbhost_120m_fck_hw = {
3044 .hw = {
3045 .clk = &usbhost_120m_fck,
3046 },
3047 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3048 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
3049 .clkdm_name = "usbhost_clkdm",
3050};
3051
3052DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
3053 aes2_ick_ops);
3054
3055static struct clk usbhost_48m_fck;
3056
3057static struct clk_hw_omap usbhost_48m_fck_hw = {
3058 .hw = {
3059 .clk = &usbhost_48m_fck,
3060 },
3061 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
3062 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3063 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3064 .clkdm_name = "usbhost_clkdm",
3065};
3066
3067DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3068
3069static struct clk usbhost_ick;
3070
3071static struct clk_hw_omap usbhost_ick_hw = {
3072 .hw = {
3073 .clk = &usbhost_ick,
3074 },
3075 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3076 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3077 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
3078 .clkdm_name = "usbhost_clkdm",
3079};
3080
3081DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3082
3083static struct clk usbtll_fck;
3084
3085static struct clk_hw_omap usbtll_fck_hw = {
3086 .hw = {
3087 .clk = &usbtll_fck,
3088 },
3089 .ops = &clkhwops_wait,
3090 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3091 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3092 .clkdm_name = "core_l4_clkdm",
3093};
3094
3095DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3096
3097static struct clk usbtll_ick;
3098
3099static struct clk_hw_omap usbtll_ick_hw = {
3100 .hw = {
3101 .clk = &usbtll_ick,
3102 },
3103 .ops = &clkhwops_iclk_wait,
3104 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3105 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3106 .clkdm_name = "core_l4_clkdm",
3107};
3108
3109DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3110
3111static const struct clksel_rate usim_96m_rates[] = {
3112 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3113 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3114 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3115 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3116 { .div = 0 }
3117};
3118
3119static const struct clksel_rate usim_120m_rates[] = {
3120 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3121 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3122 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3123 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3124 { .div = 0 }
3125};
3126
3127static const struct clksel usim_clksel[] = {
3128 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3129 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3130 { .parent = &sys_ck, .rates = div2_rates },
3131 { .parent = NULL },
3132};
3133
3134static const char *usim_fck_parent_names[] = {
3135 "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3136};
3137
3138static struct clk usim_fck;
3139
3140static const struct clk_ops usim_fck_ops = {
3141 .enable = &omap2_dflt_clk_enable,
3142 .disable = &omap2_dflt_clk_disable,
3143 .is_enabled = &omap2_dflt_clk_is_enabled,
3144 .recalc_rate = &omap2_clksel_recalc,
3145 .get_parent = &omap2_clksel_find_parent_index,
3146 .set_parent = &omap2_clksel_set_parent,
3147};
3148
3149DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3150 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3151 OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3152 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3153 OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3154 usim_fck_parent_names, usim_fck_ops);
3155
3156static struct clk usim_ick;
3157
3158static struct clk_hw_omap usim_ick_hw = {
3159 .hw = {
3160 .clk = &usim_ick,
3161 },
3162 .ops = &clkhwops_iclk_wait,
3163 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3164 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
3165 .clkdm_name = "wkup_clkdm",
3166};
3167
3168DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3169
3170static struct clk vpfe_fck;
3171
3172static const char *vpfe_fck_parent_names[] = {
3173 "pclk_ck",
3174};
3175
3176static struct clk_hw_omap vpfe_fck_hw = {
3177 .hw = {
3178 .clk = &vpfe_fck,
3179 },
3180 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3181 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3182};
3183
3184DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3185
3186static struct clk vpfe_ick;
3187
3188static struct clk_hw_omap vpfe_ick_hw = {
3189 .hw = {
3190 .clk = &vpfe_ick,
3191 },
3192 .ops = &clkhwops_am35xx_ipss_module_wait,
3193 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3194 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3195 .clkdm_name = "core_l3_clkdm",
3196};
3197
3198DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3199
3200static struct clk wdt1_fck;
3201
3202DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3203DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3204
3205static struct clk wdt1_ick;
3206
3207static struct clk_hw_omap wdt1_ick_hw = {
3208 .hw = {
3209 .clk = &wdt1_ick,
3210 },
3211 .ops = &clkhwops_iclk_wait,
3212 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3213 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
3214 .clkdm_name = "wkup_clkdm",
3215};
3216
3217DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3218
3219static struct clk wdt2_fck;
3220
3221static struct clk_hw_omap wdt2_fck_hw = {
3222 .hw = {
3223 .clk = &wdt2_fck,
3224 },
3225 .ops = &clkhwops_wait,
3226 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3227 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3228 .clkdm_name = "wkup_clkdm",
3229};
3230
3231DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3232
3233static struct clk wdt2_ick;
3234
3235static struct clk_hw_omap wdt2_ick_hw = {
3236 .hw = {
3237 .clk = &wdt2_ick,
3238 },
3239 .ops = &clkhwops_iclk_wait,
3240 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3241 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3242 .clkdm_name = "wkup_clkdm",
3243};
3244
3245DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3246
3247static struct clk wdt3_fck;
3248
3249static struct clk_hw_omap wdt3_fck_hw = {
3250 .hw = {
3251 .clk = &wdt3_fck,
3252 },
3253 .ops = &clkhwops_wait,
3254 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3255 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3256 .clkdm_name = "per_clkdm",
3257};
3258
3259DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3260
3261static struct clk wdt3_ick;
3262
3263static struct clk_hw_omap wdt3_ick_hw = {
3264 .hw = {
3265 .clk = &wdt3_ick,
3266 },
3267 .ops = &clkhwops_iclk_wait,
3268 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3269 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3270 .clkdm_name = "per_clkdm",
3271};
3272
3273DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3274
3275/*
3276 * clocks specific to omap3430es1
3277 */
3278static struct omap_clk omap3430es1_clks[] = {
3279 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
3280 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
3281 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
3282 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
3283 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
3284 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
3285 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
3286 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
3287 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
3288 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
3289 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
3290 CLK(NULL, "fac_ick", &fac_ick),
3291 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
3292 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
3293 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
3294 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
3295 CLK(NULL, "dss_ick", &dss_ick_3430es1),
3296};
3297
3298/*
3299 * clocks specific to am35xx
3300 */
3301static struct omap_clk am35xx_clks[] = {
3302 CLK(NULL, "ipss_ick", &ipss_ick),
3303 CLK(NULL, "rmii_ck", &rmii_ck),
3304 CLK(NULL, "pclk_ck", &pclk_ck),
3305 CLK(NULL, "emac_ick", &emac_ick),
3306 CLK(NULL, "emac_fck", &emac_fck),
3307 CLK("davinci_emac.0", NULL, &emac_ick),
3308 CLK("davinci_mdio.0", NULL, &emac_fck),
3309 CLK("vpfe-capture", "master", &vpfe_ick),
3310 CLK("vpfe-capture", "slave", &vpfe_fck),
3311 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
3312 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
3313 CLK(NULL, "hecc_ck", &hecc_ck),
3314 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
3315 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
3316};
3317
3318/*
3319 * clocks specific to omap36xx
3320 */
3321static struct omap_clk omap36xx_clks[] = {
3322 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
3323 CLK(NULL, "uart4_fck", &uart4_fck),
3324};
3325
3326/*
3327 * clocks common to omap36xx omap34xx
3328 */
3329static struct omap_clk omap34xx_omap36xx_clks[] = {
3330 CLK(NULL, "aes1_ick", &aes1_ick),
3331 CLK("omap_rng", "ick", &rng_ick),
3332 CLK("omap3-rom-rng", "ick", &rng_ick),
3333 CLK(NULL, "sha11_ick", &sha11_ick),
3334 CLK(NULL, "des1_ick", &des1_ick),
3335 CLK(NULL, "cam_mclk", &cam_mclk),
3336 CLK(NULL, "cam_ick", &cam_ick),
3337 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
3338 CLK(NULL, "security_l3_ick", &security_l3_ick),
3339 CLK(NULL, "pka_ick", &pka_ick),
3340 CLK(NULL, "icr_ick", &icr_ick),
3341 CLK("omap-aes", "ick", &aes2_ick),
3342 CLK("omap-sham", "ick", &sha12_ick),
3343 CLK(NULL, "des2_ick", &des2_ick),
3344 CLK(NULL, "mspro_ick", &mspro_ick),
3345 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
3346 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
3347 CLK(NULL, "sr1_fck", &sr1_fck),
3348 CLK(NULL, "sr2_fck", &sr2_fck),
3349 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
3350 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
3351 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
3352 CLK(NULL, "dpll2_fck", &dpll2_fck),
3353 CLK(NULL, "iva2_ck", &iva2_ck),
3354 CLK(NULL, "modem_fck", &modem_fck),
3355 CLK(NULL, "sad2d_ick", &sad2d_ick),
3356 CLK(NULL, "mad2d_ick", &mad2d_ick),
3357 CLK(NULL, "mspro_fck", &mspro_fck),
3358 CLK(NULL, "dpll2_ck", &dpll2_ck),
3359 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
3360};
3361
3362/*
3363 * clocks common to omap36xx and omap3430es2plus
3364 */
3365static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
3366 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
3367 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
3368 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
3369 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
3370 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
3371 CLK(NULL, "usim_fck", &usim_fck),
3372 CLK(NULL, "usim_ick", &usim_ick),
3373};
3374
3375/*
3376 * clocks common to am35xx omap36xx and omap3430es2plus
3377 */
3378static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3379 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
3380 CLK(NULL, "dpll5_ck", &dpll5_ck),
3381 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
3382 CLK(NULL, "sgx_fck", &sgx_fck),
3383 CLK(NULL, "sgx_ick", &sgx_ick),
3384 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
3385 CLK(NULL, "ts_fck", &ts_fck),
3386 CLK(NULL, "usbtll_fck", &usbtll_fck),
3387 CLK(NULL, "usbtll_ick", &usbtll_ick),
3388 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
3389 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
3390 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
3391 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
3392 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
3393 CLK(NULL, "dss_ick", &dss_ick_3430es2),
3394 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
3395 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
3396 CLK(NULL, "usbhost_ick", &usbhost_ick),
3397};
3398
3399/*
3400 * common clocks
3401 */
3402static struct omap_clk omap3xxx_clks[] = {
3403 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
3404 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
3405 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
3406 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
3407 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
3408 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
3409 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
3410 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
3411 CLK("twl", "fck", &osc_sys_ck),
3412 CLK(NULL, "sys_ck", &sys_ck),
3413 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
3414 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
3415 CLK(NULL, "sys_altclk", &sys_altclk),
3416 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
3417 CLK(NULL, "sys_clkout1", &sys_clkout1),
3418 CLK(NULL, "dpll1_ck", &dpll1_ck),
3419 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
3420 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
3421 CLK(NULL, "dpll3_ck", &dpll3_ck),
3422 CLK(NULL, "core_ck", &core_ck),
3423 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
3424 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
3425 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
3426 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
3427 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
3428 CLK(NULL, "dpll4_ck", &dpll4_ck),
3429 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
3430 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
3431 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
3432 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
3433 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
3434 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
3435 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
3436 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
3437 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
3438 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
3439 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
3440 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
3441 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
3442 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
3443 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
3444 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
3445 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
3446 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
3447 CLK(NULL, "sys_clkout2", &sys_clkout2),
3448 CLK(NULL, "corex2_fck", &corex2_fck),
3449 CLK(NULL, "dpll1_fck", &dpll1_fck),
3450 CLK(NULL, "mpu_ck", &mpu_ck),
3451 CLK(NULL, "arm_fck", &arm_fck),
3452 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
3453 CLK(NULL, "l3_ick", &l3_ick),
3454 CLK(NULL, "l4_ick", &l4_ick),
3455 CLK(NULL, "rm_ick", &rm_ick),
3456 CLK(NULL, "gpt10_fck", &gpt10_fck),
3457 CLK(NULL, "gpt11_fck", &gpt11_fck),
3458 CLK(NULL, "core_96m_fck", &core_96m_fck),
3459 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
3460 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
3461 CLK(NULL, "i2c3_fck", &i2c3_fck),
3462 CLK(NULL, "i2c2_fck", &i2c2_fck),
3463 CLK(NULL, "i2c1_fck", &i2c1_fck),
3464 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
3465 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
3466 CLK(NULL, "core_48m_fck", &core_48m_fck),
3467 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
3468 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
3469 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
3470 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
3471 CLK(NULL, "uart2_fck", &uart2_fck),
3472 CLK(NULL, "uart1_fck", &uart1_fck),
3473 CLK(NULL, "core_12m_fck", &core_12m_fck),
3474 CLK("omap_hdq.0", "fck", &hdq_fck),
3475 CLK(NULL, "hdq_fck", &hdq_fck),
3476 CLK(NULL, "core_l3_ick", &core_l3_ick),
3477 CLK(NULL, "sdrc_ick", &sdrc_ick),
3478 CLK(NULL, "gpmc_fck", &gpmc_fck),
3479 CLK(NULL, "core_l4_ick", &core_l4_ick),
3480 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
3481 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
3482 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
3483 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
3484 CLK("omap_hdq.0", "ick", &hdq_ick),
3485 CLK(NULL, "hdq_ick", &hdq_ick),
3486 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
3487 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
3488 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
3489 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
3490 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
3491 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
3492 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
3493 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
3494 CLK("omap_i2c.3", "ick", &i2c3_ick),
3495 CLK("omap_i2c.2", "ick", &i2c2_ick),
3496 CLK("omap_i2c.1", "ick", &i2c1_ick),
3497 CLK(NULL, "i2c3_ick", &i2c3_ick),
3498 CLK(NULL, "i2c2_ick", &i2c2_ick),
3499 CLK(NULL, "i2c1_ick", &i2c1_ick),
3500 CLK(NULL, "uart2_ick", &uart2_ick),
3501 CLK(NULL, "uart1_ick", &uart1_ick),
3502 CLK(NULL, "gpt11_ick", &gpt11_ick),
3503 CLK(NULL, "gpt10_ick", &gpt10_ick),
3504 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
3505 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
3506 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
3507 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
3508 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
3509 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
3510 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
3511 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
3512 CLK(NULL, "init_60m_fclk", &dummy_ck),
3513 CLK(NULL, "gpt1_fck", &gpt1_fck),
3514 CLK(NULL, "aes2_ick", &aes2_ick),
3515 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
3516 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
3517 CLK(NULL, "sha12_ick", &sha12_ick),
3518 CLK(NULL, "wdt2_fck", &wdt2_fck),
3519 CLK("omap_wdt", "ick", &wdt2_ick),
3520 CLK(NULL, "wdt2_ick", &wdt2_ick),
3521 CLK(NULL, "wdt1_ick", &wdt1_ick),
3522 CLK(NULL, "gpio1_ick", &gpio1_ick),
3523 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
3524 CLK(NULL, "gpt12_ick", &gpt12_ick),
3525 CLK(NULL, "gpt1_ick", &gpt1_ick),
3526 CLK(NULL, "per_96m_fck", &per_96m_fck),
3527 CLK(NULL, "per_48m_fck", &per_48m_fck),
3528 CLK(NULL, "uart3_fck", &uart3_fck),
3529 CLK(NULL, "gpt2_fck", &gpt2_fck),
3530 CLK(NULL, "gpt3_fck", &gpt3_fck),
3531 CLK(NULL, "gpt4_fck", &gpt4_fck),
3532 CLK(NULL, "gpt5_fck", &gpt5_fck),
3533 CLK(NULL, "gpt6_fck", &gpt6_fck),
3534 CLK(NULL, "gpt7_fck", &gpt7_fck),
3535 CLK(NULL, "gpt8_fck", &gpt8_fck),
3536 CLK(NULL, "gpt9_fck", &gpt9_fck),
3537 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
3538 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
3539 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
3540 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
3541 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
3542 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
3543 CLK(NULL, "wdt3_fck", &wdt3_fck),
3544 CLK(NULL, "per_l4_ick", &per_l4_ick),
3545 CLK(NULL, "gpio6_ick", &gpio6_ick),
3546 CLK(NULL, "gpio5_ick", &gpio5_ick),
3547 CLK(NULL, "gpio4_ick", &gpio4_ick),
3548 CLK(NULL, "gpio3_ick", &gpio3_ick),
3549 CLK(NULL, "gpio2_ick", &gpio2_ick),
3550 CLK(NULL, "wdt3_ick", &wdt3_ick),
3551 CLK(NULL, "uart3_ick", &uart3_ick),
3552 CLK(NULL, "uart4_ick", &uart4_ick),
3553 CLK(NULL, "gpt9_ick", &gpt9_ick),
3554 CLK(NULL, "gpt8_ick", &gpt8_ick),
3555 CLK(NULL, "gpt7_ick", &gpt7_ick),
3556 CLK(NULL, "gpt6_ick", &gpt6_ick),
3557 CLK(NULL, "gpt5_ick", &gpt5_ick),
3558 CLK(NULL, "gpt4_ick", &gpt4_ick),
3559 CLK(NULL, "gpt3_ick", &gpt3_ick),
3560 CLK(NULL, "gpt2_ick", &gpt2_ick),
3561 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
3562 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
3563 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
3564 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
3565 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
3566 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
3567 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
3568 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
3569 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
3570 CLK("etb", "emu_src_ck", &emu_src_ck),
3571 CLK(NULL, "emu_src_ck", &emu_src_ck),
3572 CLK(NULL, "pclk_fck", &pclk_fck),
3573 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
3574 CLK(NULL, "atclk_fck", &atclk_fck),
3575 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
3576 CLK(NULL, "traceclk_fck", &traceclk_fck),
3577 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
3578 CLK(NULL, "gpt12_fck", &gpt12_fck),
3579 CLK(NULL, "wdt1_fck", &wdt1_fck),
3580 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
3581 CLK(NULL, "timer_sys_ck", &sys_ck),
3582 CLK(NULL, "cpufreq_ck", &dpll1_ck),
3583};
3584
3585static const char *enable_init_clks[] = {
3586 "sdrc_ick",
3587 "gpmc_fck",
3588 "omapctrl_ick",
3589};
3590
3591int __init omap3xxx_clk_init(void)
3592{
3593 if (omap3_has_192mhz_clk())
3594 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3595
3596 if (cpu_is_omap3630()) {
3597 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3598 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3599 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3600 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3601 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3602 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3603 }
3604
3605 /*
3606 * XXX This type of dynamic rewriting of the clock tree is
3607 * deprecated and should be revised soon.
3608 */
3609 if (cpu_is_omap3630())
3610 dpll4_dd = dpll4_dd_3630;
3611 else
3612 dpll4_dd = dpll4_dd_34xx;
3613
3614
3615 /*
3616 * 3505 must be tested before 3517, since 3517 returns true
3617 * for both AM3517 chips and AM3517 family chips, which
3618 * includes 3505. Unfortunately there's no obvious family
3619 * test for 3517/3505 :-(
3620 */
3621 if (soc_is_am35xx()) {
3622 cpu_mask = RATE_IN_34XX;
3623 omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
3624 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3625 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3626 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3627 } else if (cpu_is_omap3630()) {
3628 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3629 omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
3630 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3631 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3632 omap_clocks_register(omap34xx_omap36xx_clks,
3633 ARRAY_SIZE(omap34xx_omap36xx_clks));
3634 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3635 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3636 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3637 } else if (cpu_is_omap34xx()) {
3638 if (omap_rev() == OMAP3430_REV_ES1_0) {
3639 cpu_mask = RATE_IN_3430ES1;
3640 omap_clocks_register(omap3430es1_clks,
3641 ARRAY_SIZE(omap3430es1_clks));
3642 omap_clocks_register(omap34xx_omap36xx_clks,
3643 ARRAY_SIZE(omap34xx_omap36xx_clks));
3644 omap_clocks_register(omap3xxx_clks,
3645 ARRAY_SIZE(omap3xxx_clks));
3646 } else {
3647 /*
3648 * Assume that anything that we haven't matched yet
3649 * has 3430ES2-type clocks.
3650 */
3651 cpu_mask = RATE_IN_3430ES2PLUS;
3652 omap_clocks_register(omap34xx_omap36xx_clks,
3653 ARRAY_SIZE(omap34xx_omap36xx_clks));
3654 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3655 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3656 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3657 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3658 omap_clocks_register(omap3xxx_clks,
3659 ARRAY_SIZE(omap3xxx_clks));
3660 }
3661 } else {
3662 WARN(1, "clock: could not identify OMAP3 variant\n");
3663 }
3664
3665 omap2_clk_disable_autoidle_all();
3666
3667 omap2_clk_enable_init_clocks(enable_init_clks,
3668 ARRAY_SIZE(enable_init_clks));
3669
3670 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3671 (clk_get_rate(&osc_sys_ck) / 1000000),
3672 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3673 (clk_get_rate(&core_ck) / 1000000),
3674 (clk_get_rate(&arm_fck) / 1000000));
3675
3676 /*
3677 * Lock DPLL5 -- here only until other device init code can
3678 * handle this
3679 */
3680 if (omap_rev() >= OMAP3430_REV_ES2_0)
3681 omap3_clk_lock_dpll5();
3682
3683 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3684 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3685 arm_fck_p = clk_get(NULL, "arm_fck");
3686
3687 return 0;
3688}
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 4ae4ccebced2..6124db5c37ae 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,7 +23,6 @@
23#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26#include <linux/clk-private.h>
27#include <asm/cpu.h> 26#include <asm/cpu.h>
28 27
29#include <trace/events/power.h> 28#include <trace/events/power.h>
@@ -633,21 +632,6 @@ const struct clk_hw_omap_ops clkhwops_wait = {
633}; 632};
634 633
635/** 634/**
636 * omap_clocks_register - register an array of omap_clk
637 * @ocs: pointer to an array of omap_clk to register
638 */
639void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
640{
641 struct omap_clk *c;
642
643 for (c = oclks; c < oclks + cnt; c++) {
644 clkdev_add(&c->lk);
645 if (!__clk_init(NULL, c->lk.clk))
646 omap2_init_clk_hw_omap_clocks(c->lk.clk);
647 }
648}
649
650/**
651 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 635 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
652 * @mpurate_ck_name: clk name of the clock to change rate 636 * @mpurate_ck_name: clk name of the clock to change rate
653 * 637 *
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 1cf9dd85248a..a56742f96000 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -40,23 +40,29 @@ struct omap_clk {
40struct clockdomain; 40struct clockdomain;
41 41
42#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ 42#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
43 static struct clk _name = { \ 43 static struct clk_core _name##_core = { \
44 .name = #_name, \ 44 .name = #_name, \
45 .hw = &_name##_hw.hw, \ 45 .hw = &_name##_hw.hw, \
46 .parent_names = _parent_array_name, \ 46 .parent_names = _parent_array_name, \
47 .num_parents = ARRAY_SIZE(_parent_array_name), \ 47 .num_parents = ARRAY_SIZE(_parent_array_name), \
48 .ops = &_clkops_name, \ 48 .ops = &_clkops_name, \
49 }; \
50 static struct clk _name = { \
51 .core = &_name##_core, \
49 }; 52 };
50 53
51#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \ 54#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
52 _clkops_name, _flags) \ 55 _clkops_name, _flags) \
53 static struct clk _name = { \ 56 static struct clk_core _name##_core = { \
54 .name = #_name, \ 57 .name = #_name, \
55 .hw = &_name##_hw.hw, \ 58 .hw = &_name##_hw.hw, \
56 .parent_names = _parent_array_name, \ 59 .parent_names = _parent_array_name, \
57 .num_parents = ARRAY_SIZE(_parent_array_name), \ 60 .num_parents = ARRAY_SIZE(_parent_array_name), \
58 .ops = &_clkops_name, \ 61 .ops = &_clkops_name, \
59 .flags = _flags, \ 62 .flags = _flags, \
63 }; \
64 static struct clk _name = { \
65 .core = &_name##_core, \
60 }; 66 };
61 67
62#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ 68#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
@@ -238,7 +244,6 @@ struct ti_clk_features {
238extern struct ti_clk_features ti_clk_features; 244extern struct ti_clk_features ti_clk_features;
239 245
240extern const struct clkops clkops_omap2_dflt_wait; 246extern const struct clkops clkops_omap2_dflt_wait;
241extern const struct clkops clkops_dummy;
242extern const struct clkops clkops_omap2_dflt; 247extern const struct clkops clkops_omap2_dflt;
243 248
244extern struct clk_functions omap2_clk_functions; 249extern struct clk_functions omap2_clk_functions;
@@ -247,7 +252,6 @@ extern const struct clksel_rate gpt_32k_rates[];
247extern const struct clksel_rate gpt_sys_rates[]; 252extern const struct clksel_rate gpt_sys_rates[];
248extern const struct clksel_rate gfx_l3_rates[]; 253extern const struct clksel_rate gfx_l3_rates[];
249extern const struct clksel_rate dsp_ick_rates[]; 254extern const struct clksel_rate dsp_ick_rates[];
250extern struct clk dummy_ck;
251 255
252extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 256extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
253extern const struct clk_hw_omap_ops clkhwops_wait; 257extern const struct clk_hw_omap_ops clkhwops_wait;
@@ -272,7 +276,5 @@ extern void __iomem *clk_memmaps[];
272extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); 276extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
273extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); 277extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
274 278
275extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
276
277void __init ti_clk_init_features(void); 279void __init ti_clk_init_features(void);
278#endif 280#endif
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index ef4d21bfb964..61b60dfb14ce 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -16,7 +16,6 @@
16 * OMAP3xxx clock definition files. 16 * OMAP3xxx clock definition files.
17 */ 17 */
18 18
19#include <linux/clk-private.h>
20#include "clock.h" 19#include "clock.h"
21 20
22/* clksel_rate data common to 24xx/343x */ 21/* clksel_rate data common to 24xx/343x */
@@ -114,13 +113,3 @@ const struct clksel_rate div31_1to31_rates[] = {
114 { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, 113 { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
115 { .div = 0 }, 114 { .div = 0 },
116}; 115};
117
118/* Clocks shared between various OMAP SoCs */
119
120static struct clk_ops dummy_ck_ops = {};
121
122struct clk dummy_ck = {
123 .name = "dummy_clk",
124 .ops = &dummy_ck_ops,
125 .flags = CLK_IS_BASIC,
126};
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index c2da2a0fe5ad..44e57ec225d4 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -410,7 +410,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
410 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 410 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
411 int r; 411 int r;
412 struct dpll_data *dd; 412 struct dpll_data *dd;
413 struct clk *parent; 413 struct clk_hw *parent;
414 414
415 dd = clk->dpll_data; 415 dd = clk->dpll_data;
416 if (!dd) 416 if (!dd)
@@ -427,13 +427,13 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
427 } 427 }
428 } 428 }
429 429
430 parent = __clk_get_parent(hw->clk); 430 parent = __clk_get_hw(__clk_get_parent(hw->clk));
431 431
432 if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { 432 if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
433 WARN_ON(parent != dd->clk_bypass); 433 WARN_ON(parent != __clk_get_hw(dd->clk_bypass));
434 r = _omap3_noncore_dpll_bypass(clk); 434 r = _omap3_noncore_dpll_bypass(clk);
435 } else { 435 } else {
436 WARN_ON(parent != dd->clk_ref); 436 WARN_ON(parent != __clk_get_hw(dd->clk_ref));
437 r = _omap3_noncore_dpll_lock(clk); 437 r = _omap3_noncore_dpll_lock(clk);
438 } 438 }
439 439
@@ -473,6 +473,8 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
473 * in failure. 473 * in failure.
474 */ 474 */
475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate, 475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
476 unsigned long min_rate,
477 unsigned long max_rate,
476 unsigned long *best_parent_rate, 478 unsigned long *best_parent_rate,
477 struct clk_hw **best_parent_clk) 479 struct clk_hw **best_parent_clk)
478{ 480{
@@ -549,7 +551,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
549 if (!dd) 551 if (!dd)
550 return -EINVAL; 552 return -EINVAL;
551 553
552 if (__clk_get_parent(hw->clk) != dd->clk_ref) 554 if (__clk_get_hw(__clk_get_parent(hw->clk)) !=
555 __clk_get_hw(dd->clk_ref))
553 return -EINVAL; 556 return -EINVAL;
554 557
555 if (dd->last_rounded_rate == 0) 558 if (dd->last_rounded_rate == 0)
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index fc712240e5fd..f231be05b9a6 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -202,6 +202,8 @@ out:
202 * in failure. 202 * in failure.
203 */ 203 */
204long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, 204long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
205 unsigned long min_rate,
206 unsigned long max_rate,
205 unsigned long *best_parent_rate, 207 unsigned long *best_parent_rate,
206 struct clk_hw **best_parent_clk) 208 struct clk_hw **best_parent_clk)
207{ 209{
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e60780f05374..c4871c55bd8b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -461,7 +461,17 @@ void __init omap3_init_early(void)
461 omap3xxx_clockdomains_init(); 461 omap3xxx_clockdomains_init();
462 omap3xxx_hwmod_init(); 462 omap3xxx_hwmod_init();
463 omap_hwmod_init_postsetup(); 463 omap_hwmod_init_postsetup();
464 omap_clk_soc_init = omap3xxx_clk_init; 464 if (!of_have_populated_dt()) {
465 omap3_prcm_legacy_iomaps_init();
466 if (soc_is_am35xx())
467 omap_clk_soc_init = am35xx_clk_legacy_init;
468 else if (cpu_is_omap3630())
469 omap_clk_soc_init = omap36xx_clk_legacy_init;
470 else if (omap_rev() == OMAP3430_REV_ES1_0)
471 omap_clk_soc_init = omap3430es1_clk_legacy_init;
472 else
473 omap_clk_soc_init = omap3430_clk_legacy_init;
474 }
465} 475}
466 476
467void __init omap3430_init_early(void) 477void __init omap3430_init_early(void)
@@ -753,15 +763,17 @@ int __init omap_clk_init(void)
753 763
754 ti_clk_init_features(); 764 ti_clk_init_features();
755 765
756 ret = of_prcm_init(); 766 if (of_have_populated_dt()) {
757 if (ret) 767 ret = of_prcm_init();
758 return ret; 768 if (ret)
769 return ret;
759 770
760 of_clk_init(NULL); 771 of_clk_init(NULL);
761 772
762 ti_dt_clk_init_retry_clks(); 773 ti_dt_clk_init_retry_clks();
763 774
764 ti_dt_clockdomains_setup(); 775 ti_dt_clockdomains_setup();
776 }
765 777
766 ret = omap_clk_soc_init(); 778 ret = omap_clk_soc_init();
767 779
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 77752e49d8d4..b9061a6a2db8 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -20,6 +20,7 @@ extern void __iomem *prm_base;
20extern u16 prm_features; 20extern u16 prm_features;
21extern void omap2_set_globals_prm(void __iomem *prm); 21extern void omap2_set_globals_prm(void __iomem *prm);
22int of_prcm_init(void); 22int of_prcm_init(void);
23void omap3_prcm_legacy_iomaps_init(void);
23# endif 24# endif
24 25
25/* 26/*
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 264b5e29404d..bfaa7ba595cc 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -35,6 +35,8 @@
35#include "prm44xx.h" 35#include "prm44xx.h"
36#include "common.h" 36#include "common.h"
37#include "clock.h" 37#include "clock.h"
38#include "cm.h"
39#include "control.h"
38 40
39/* 41/*
40 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs 42 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -641,6 +643,15 @@ int __init of_prcm_init(void)
641 return 0; 643 return 0;
642} 644}
643 645
646void __init omap3_prcm_legacy_iomaps_init(void)
647{
648 ti_clk_ll_ops = &omap_clk_ll_ops;
649
650 clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
651 clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
652 clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
653}
654
644static int __init prm_late_init(void) 655static int __init prm_late_init(void)
645{ 656{
646 if (prm_ll_data->late_init) 657 if (prm_ll_data->late_init)
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-24 23:15:53 -0400