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authorTony Lindgren <tony@atomide.com>2019-03-21 14:00:21 -0400
committerTony Lindgren <tony@atomide.com>2019-04-08 13:10:59 -0400
commitfbf3b4b9f4ba0bf7ac683b32b9ece09e62a7ddf3 (patch)
tree2b620faf9825427c344d84ca4232b5ab5fed0495 /arch/arm/mach-omap2/omap_hwmod_7xx_data.c
parent19326ef5d5e9e56f41cb129bb57ff08892e144d0 (diff)
ARM: OMAP2+: Drop uart platform data for dra7
We can now drop legacy platform data one interconnect target module at a time in favor of the device tree based data that has been added earlier. Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_7xx_data.c')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c272
1 files changed, 0 insertions, 272 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index cdbab92a8799..7e85bd27ce9a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1954,188 +1954,6 @@ static struct omap_hwmod dra7xx_timer16_hwmod = {
1954 }, 1954 },
1955}; 1955};
1956 1956
1957/*
1958 * 'uart' class
1959 *
1960 */
1961
1962static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1963 .rev_offs = 0x0050,
1964 .sysc_offs = 0x0054,
1965 .syss_offs = 0x0058,
1966 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1967 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1968 SYSS_HAS_RESET_STATUS),
1969 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1970 SIDLE_SMART_WKUP),
1971 .sysc_fields = &omap_hwmod_sysc_type1,
1972};
1973
1974static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1975 .name = "uart",
1976 .sysc = &dra7xx_uart_sysc,
1977};
1978
1979/* uart1 */
1980static struct omap_hwmod dra7xx_uart1_hwmod = {
1981 .name = "uart1",
1982 .class = &dra7xx_uart_hwmod_class,
1983 .clkdm_name = "l4per_clkdm",
1984 .main_clk = "uart1_gfclk_mux",
1985 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
1986 .prcm = {
1987 .omap4 = {
1988 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1989 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1990 .modulemode = MODULEMODE_SWCTRL,
1991 },
1992 },
1993};
1994
1995/* uart2 */
1996static struct omap_hwmod dra7xx_uart2_hwmod = {
1997 .name = "uart2",
1998 .class = &dra7xx_uart_hwmod_class,
1999 .clkdm_name = "l4per_clkdm",
2000 .main_clk = "uart2_gfclk_mux",
2001 .flags = HWMOD_SWSUP_SIDLE_ACT,
2002 .prcm = {
2003 .omap4 = {
2004 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2005 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2006 .modulemode = MODULEMODE_SWCTRL,
2007 },
2008 },
2009};
2010
2011/* uart3 */
2012static struct omap_hwmod dra7xx_uart3_hwmod = {
2013 .name = "uart3",
2014 .class = &dra7xx_uart_hwmod_class,
2015 .clkdm_name = "l4per_clkdm",
2016 .main_clk = "uart3_gfclk_mux",
2017 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2018 .prcm = {
2019 .omap4 = {
2020 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2021 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2022 .modulemode = MODULEMODE_SWCTRL,
2023 },
2024 },
2025};
2026
2027/* uart4 */
2028static struct omap_hwmod dra7xx_uart4_hwmod = {
2029 .name = "uart4",
2030 .class = &dra7xx_uart_hwmod_class,
2031 .clkdm_name = "l4per_clkdm",
2032 .main_clk = "uart4_gfclk_mux",
2033 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2034 .prcm = {
2035 .omap4 = {
2036 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2037 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2038 .modulemode = MODULEMODE_SWCTRL,
2039 },
2040 },
2041};
2042
2043/* uart5 */
2044static struct omap_hwmod dra7xx_uart5_hwmod = {
2045 .name = "uart5",
2046 .class = &dra7xx_uart_hwmod_class,
2047 .clkdm_name = "l4per_clkdm",
2048 .main_clk = "uart5_gfclk_mux",
2049 .flags = HWMOD_SWSUP_SIDLE_ACT,
2050 .prcm = {
2051 .omap4 = {
2052 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2053 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2054 .modulemode = MODULEMODE_SWCTRL,
2055 },
2056 },
2057};
2058
2059/* uart6 */
2060static struct omap_hwmod dra7xx_uart6_hwmod = {
2061 .name = "uart6",
2062 .class = &dra7xx_uart_hwmod_class,
2063 .clkdm_name = "ipu_clkdm",
2064 .main_clk = "uart6_gfclk_mux",
2065 .flags = HWMOD_SWSUP_SIDLE_ACT,
2066 .prcm = {
2067 .omap4 = {
2068 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2069 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2070 .modulemode = MODULEMODE_SWCTRL,
2071 },
2072 },
2073};
2074
2075/* uart7 */
2076static struct omap_hwmod dra7xx_uart7_hwmod = {
2077 .name = "uart7",
2078 .class = &dra7xx_uart_hwmod_class,
2079 .clkdm_name = "l4per2_clkdm",
2080 .main_clk = "uart7_gfclk_mux",
2081 .flags = HWMOD_SWSUP_SIDLE_ACT,
2082 .prcm = {
2083 .omap4 = {
2084 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2085 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2086 .modulemode = MODULEMODE_SWCTRL,
2087 },
2088 },
2089};
2090
2091/* uart8 */
2092static struct omap_hwmod dra7xx_uart8_hwmod = {
2093 .name = "uart8",
2094 .class = &dra7xx_uart_hwmod_class,
2095 .clkdm_name = "l4per2_clkdm",
2096 .main_clk = "uart8_gfclk_mux",
2097 .flags = HWMOD_SWSUP_SIDLE_ACT,
2098 .prcm = {
2099 .omap4 = {
2100 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2101 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2102 .modulemode = MODULEMODE_SWCTRL,
2103 },
2104 },
2105};
2106
2107/* uart9 */
2108static struct omap_hwmod dra7xx_uart9_hwmod = {
2109 .name = "uart9",
2110 .class = &dra7xx_uart_hwmod_class,
2111 .clkdm_name = "l4per2_clkdm",
2112 .main_clk = "uart9_gfclk_mux",
2113 .flags = HWMOD_SWSUP_SIDLE_ACT,
2114 .prcm = {
2115 .omap4 = {
2116 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2117 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2118 .modulemode = MODULEMODE_SWCTRL,
2119 },
2120 },
2121};
2122
2123/* uart10 */
2124static struct omap_hwmod dra7xx_uart10_hwmod = {
2125 .name = "uart10",
2126 .class = &dra7xx_uart_hwmod_class,
2127 .clkdm_name = "wkupaon_clkdm",
2128 .main_clk = "uart10_gfclk_mux",
2129 .flags = HWMOD_SWSUP_SIDLE_ACT,
2130 .prcm = {
2131 .omap4 = {
2132 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2133 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2134 .modulemode = MODULEMODE_SWCTRL,
2135 },
2136 },
2137};
2138
2139/* DES (the 'P' (public) device) */ 1957/* DES (the 'P' (public) device) */
2140static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = { 1958static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2141 .rev_offs = 0x0030, 1959 .rev_offs = 0x0030,
@@ -3076,62 +2894,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3076 .user = OCP_USER_MPU | OCP_USER_SDMA, 2894 .user = OCP_USER_MPU | OCP_USER_SDMA,
3077}; 2895};
3078 2896
3079/* l4_per1 -> uart1 */
3080static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3081 .master = &dra7xx_l4_per1_hwmod,
3082 .slave = &dra7xx_uart1_hwmod,
3083 .clk = "l3_iclk_div",
3084 .user = OCP_USER_MPU | OCP_USER_SDMA,
3085};
3086
3087/* l4_per1 -> uart2 */
3088static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3089 .master = &dra7xx_l4_per1_hwmod,
3090 .slave = &dra7xx_uart2_hwmod,
3091 .clk = "l3_iclk_div",
3092 .user = OCP_USER_MPU | OCP_USER_SDMA,
3093};
3094
3095/* l4_per1 -> uart3 */
3096static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3097 .master = &dra7xx_l4_per1_hwmod,
3098 .slave = &dra7xx_uart3_hwmod,
3099 .clk = "l3_iclk_div",
3100 .user = OCP_USER_MPU | OCP_USER_SDMA,
3101};
3102
3103/* l4_per1 -> uart4 */
3104static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3105 .master = &dra7xx_l4_per1_hwmod,
3106 .slave = &dra7xx_uart4_hwmod,
3107 .clk = "l3_iclk_div",
3108 .user = OCP_USER_MPU | OCP_USER_SDMA,
3109};
3110
3111/* l4_per1 -> uart5 */
3112static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3113 .master = &dra7xx_l4_per1_hwmod,
3114 .slave = &dra7xx_uart5_hwmod,
3115 .clk = "l3_iclk_div",
3116 .user = OCP_USER_MPU | OCP_USER_SDMA,
3117};
3118
3119/* l4_per1 -> uart6 */
3120static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3121 .master = &dra7xx_l4_per1_hwmod,
3122 .slave = &dra7xx_uart6_hwmod,
3123 .clk = "l3_iclk_div",
3124 .user = OCP_USER_MPU | OCP_USER_SDMA,
3125};
3126
3127/* l4_per2 -> uart7 */
3128static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3129 .master = &dra7xx_l4_per2_hwmod,
3130 .slave = &dra7xx_uart7_hwmod,
3131 .clk = "l3_iclk_div",
3132 .user = OCP_USER_MPU | OCP_USER_SDMA,
3133};
3134
3135/* l4_per1 -> des */ 2897/* l4_per1 -> des */
3136static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = { 2898static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3137 .master = &dra7xx_l4_per1_hwmod, 2899 .master = &dra7xx_l4_per1_hwmod,
@@ -3140,30 +2902,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3140 .user = OCP_USER_MPU | OCP_USER_SDMA, 2902 .user = OCP_USER_MPU | OCP_USER_SDMA,
3141}; 2903};
3142 2904
3143/* l4_per2 -> uart8 */
3144static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3145 .master = &dra7xx_l4_per2_hwmod,
3146 .slave = &dra7xx_uart8_hwmod,
3147 .clk = "l3_iclk_div",
3148 .user = OCP_USER_MPU | OCP_USER_SDMA,
3149};
3150
3151/* l4_per2 -> uart9 */
3152static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3153 .master = &dra7xx_l4_per2_hwmod,
3154 .slave = &dra7xx_uart9_hwmod,
3155 .clk = "l3_iclk_div",
3156 .user = OCP_USER_MPU | OCP_USER_SDMA,
3157};
3158
3159/* l4_wkup -> uart10 */
3160static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3161 .master = &dra7xx_l4_wkup_hwmod,
3162 .slave = &dra7xx_uart10_hwmod,
3163 .clk = "wkupaon_iclk_mux",
3164 .user = OCP_USER_MPU | OCP_USER_SDMA,
3165};
3166
3167/* l4_per1 -> rng */ 2905/* l4_per1 -> rng */
3168static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = { 2906static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3169 .master = &dra7xx_l4_per1_hwmod, 2907 .master = &dra7xx_l4_per1_hwmod,
@@ -3355,16 +3093,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3355 &dra7xx_l4_per3__timer14, 3093 &dra7xx_l4_per3__timer14,
3356 &dra7xx_l4_per3__timer15, 3094 &dra7xx_l4_per3__timer15,
3357 &dra7xx_l4_per3__timer16, 3095 &dra7xx_l4_per3__timer16,
3358 &dra7xx_l4_per1__uart1,
3359 &dra7xx_l4_per1__uart2,
3360 &dra7xx_l4_per1__uart3,
3361 &dra7xx_l4_per1__uart4,
3362 &dra7xx_l4_per1__uart5,
3363 &dra7xx_l4_per1__uart6,
3364 &dra7xx_l4_per2__uart7,
3365 &dra7xx_l4_per2__uart8,
3366 &dra7xx_l4_per2__uart9,
3367 &dra7xx_l4_wkup__uart10,
3368 &dra7xx_l4_per1__des, 3096 &dra7xx_l4_per1__des,
3369 &dra7xx_l4_per3__usb_otg_ss1, 3097 &dra7xx_l4_per3__usb_otg_ss1,
3370 &dra7xx_l4_per3__usb_otg_ss2, 3098 &dra7xx_l4_per3__usb_otg_ss2,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 20:26:19 -0400