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authorPaul Walmsley <paul@pwsan.com>2012-04-19 06:04:33 -0400
committerPaul Walmsley <paul@pwsan.com>2012-04-19 06:04:33 -0400
commit844a3b632b76f5d5e85eb9b9edfbd7de41e4999f (patch)
treecbbb418055b97b7d9426fce35b11a65d17ac72b7 /arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
parent11cd4b94cb491894b8a192635abf159fc1917f4d (diff)
ARM: OMAP2+: hwmod data: remove forward declarations, reorganize
Reorganize the hwmod data to declare the IP blocks first and the interconnects second. This allows us to remove the forward declarations, which this patch also does. Saves some lines of source data. While here, take the opportunity to synchronize the order of the OMAP44xx hwmod data with the autogenerator output -- it's slightly different due to past mismerges -- and fix a few minor typos and whitespace problems in the files. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_3xxx_data.c')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c2288
1 files changed, 1101 insertions, 1187 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index a3eeff733682..7fd34b377555 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -39,116 +39,23 @@
39/* 39/*
40 * OMAP3xxx hardware module integration data 40 * OMAP3xxx hardware module integration data
41 * 41 *
42 * ALl of the data in this section should be autogeneratable from the 42 * All of the data in this section should be autogeneratable from the
43 * TI hardware database or other technical documentation. Data that 43 * TI hardware database or other technical documentation. Data that
44 * is driver-specific or driver-kernel integration-specific belongs 44 * is driver-specific or driver-kernel integration-specific belongs
45 * elsewhere. 45 * elsewhere.
46 */ 46 */
47 47
48static struct omap_hwmod omap3xxx_mpu_hwmod; 48/*
49static struct omap_hwmod omap3xxx_iva_hwmod; 49 * IP blocks
50static struct omap_hwmod omap3xxx_l3_main_hwmod; 50 */
51static struct omap_hwmod omap3xxx_l4_core_hwmod;
52static struct omap_hwmod omap3xxx_l4_per_hwmod;
53static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
54static struct omap_hwmod omap3430es1_dss_core_hwmod;
55static struct omap_hwmod omap3xxx_dss_core_hwmod;
56static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
57static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
58static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
59static struct omap_hwmod omap3xxx_dss_venc_hwmod;
60static struct omap_hwmod omap3xxx_i2c1_hwmod;
61static struct omap_hwmod omap3xxx_i2c2_hwmod;
62static struct omap_hwmod omap3xxx_i2c3_hwmod;
63static struct omap_hwmod omap3xxx_gpio1_hwmod;
64static struct omap_hwmod omap3xxx_gpio2_hwmod;
65static struct omap_hwmod omap3xxx_gpio3_hwmod;
66static struct omap_hwmod omap3xxx_gpio4_hwmod;
67static struct omap_hwmod omap3xxx_gpio5_hwmod;
68static struct omap_hwmod omap3xxx_gpio6_hwmod;
69static struct omap_hwmod omap34xx_sr1_hwmod;
70static struct omap_hwmod omap34xx_sr2_hwmod;
71static struct omap_hwmod omap34xx_mcspi1;
72static struct omap_hwmod omap34xx_mcspi2;
73static struct omap_hwmod omap34xx_mcspi3;
74static struct omap_hwmod omap34xx_mcspi4;
75static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod;
76static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod;
77static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod;
78static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod;
79static struct omap_hwmod omap3xxx_mmc3_hwmod;
80static struct omap_hwmod am35xx_usbhsotg_hwmod;
81
82static struct omap_hwmod omap3xxx_dma_system_hwmod;
83
84static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
85static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
86static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
87static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
88static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
89static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
90static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
91static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
92static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
93
94/* L3 -> L4_CORE interface */
95static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
96 .master = &omap3xxx_l3_main_hwmod,
97 .slave = &omap3xxx_l4_core_hwmod,
98 .user = OCP_USER_MPU | OCP_USER_SDMA,
99};
100
101/* L3 -> L4_PER interface */
102static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
103 .master = &omap3xxx_l3_main_hwmod,
104 .slave = &omap3xxx_l4_per_hwmod,
105 .user = OCP_USER_MPU | OCP_USER_SDMA,
106};
107 51
108/* L3 taret configuration and error log registers */ 52/* L3 */
109static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 53static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
110 { .irq = INT_34XX_L3_DBG_IRQ }, 54 { .irq = INT_34XX_L3_DBG_IRQ },
111 { .irq = INT_34XX_L3_APP_IRQ }, 55 { .irq = INT_34XX_L3_APP_IRQ },
112 { .irq = -1 } 56 { .irq = -1 }
113}; 57};
114 58
115static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
116 {
117 .pa_start = 0x68000000,
118 .pa_end = 0x6800ffff,
119 .flags = ADDR_TYPE_RT,
120 },
121 { }
122};
123
124/* MPU -> L3 interface */
125static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
126 .master = &omap3xxx_mpu_hwmod,
127 .slave = &omap3xxx_l3_main_hwmod,
128 .addr = omap3xxx_l3_main_addrs,
129 .user = OCP_USER_MPU,
130};
131
132/* DSS -> l3 */
133static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
134 .master = &omap3430es1_dss_core_hwmod,
135 .slave = &omap3xxx_l3_main_hwmod,
136 .user = OCP_USER_MPU | OCP_USER_SDMA,
137};
138
139static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
140 .master = &omap3xxx_dss_core_hwmod,
141 .slave = &omap3xxx_l3_main_hwmod,
142 .fw = {
143 .omap2 = {
144 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
145 .flags = OMAP_FIREWALL_L3,
146 }
147 },
148 .user = OCP_USER_MPU | OCP_USER_SDMA,
149};
150
151/* L3 */
152static struct omap_hwmod omap3xxx_l3_main_hwmod = { 59static struct omap_hwmod omap3xxx_l3_main_hwmod = {
153 .name = "l3_main", 60 .name = "l3_main",
154 .class = &l3_hwmod_class, 61 .class = &l3_hwmod_class,
@@ -156,326 +63,6 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
156 .flags = HWMOD_NO_IDLEST, 63 .flags = HWMOD_NO_IDLEST,
157}; 64};
158 65
159static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
160static struct omap_hwmod omap3xxx_l4_sec_hwmod;
161static struct omap_hwmod omap3xxx_uart1_hwmod;
162static struct omap_hwmod omap3xxx_uart2_hwmod;
163static struct omap_hwmod omap3xxx_uart3_hwmod;
164static struct omap_hwmod omap36xx_uart4_hwmod;
165static struct omap_hwmod am35xx_uart4_hwmod;
166static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
167
168/* l3_core -> usbhsotg interface */
169static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
170 .master = &omap3xxx_usbhsotg_hwmod,
171 .slave = &omap3xxx_l3_main_hwmod,
172 .clk = "core_l3_ick",
173 .user = OCP_USER_MPU,
174};
175
176/* l3_core -> am35xx_usbhsotg interface */
177static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
178 .master = &am35xx_usbhsotg_hwmod,
179 .slave = &omap3xxx_l3_main_hwmod,
180 .clk = "core_l3_ick",
181 .user = OCP_USER_MPU,
182};
183/* L4_CORE -> L4_WKUP interface */
184static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
185 .master = &omap3xxx_l4_core_hwmod,
186 .slave = &omap3xxx_l4_wkup_hwmod,
187 .user = OCP_USER_MPU | OCP_USER_SDMA,
188};
189
190/* L4 CORE -> MMC1 interface */
191static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
192 .master = &omap3xxx_l4_core_hwmod,
193 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
194 .clk = "mmchs1_ick",
195 .addr = omap2430_mmc1_addr_space,
196 .user = OCP_USER_MPU | OCP_USER_SDMA,
197 .flags = OMAP_FIREWALL_L4
198};
199
200static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
201 .master = &omap3xxx_l4_core_hwmod,
202 .slave = &omap3xxx_es3plus_mmc1_hwmod,
203 .clk = "mmchs1_ick",
204 .addr = omap2430_mmc1_addr_space,
205 .user = OCP_USER_MPU | OCP_USER_SDMA,
206 .flags = OMAP_FIREWALL_L4
207};
208
209/* L4 CORE -> MMC2 interface */
210static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
211 .master = &omap3xxx_l4_core_hwmod,
212 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
213 .clk = "mmchs2_ick",
214 .addr = omap2430_mmc2_addr_space,
215 .user = OCP_USER_MPU | OCP_USER_SDMA,
216 .flags = OMAP_FIREWALL_L4
217};
218
219static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
220 .master = &omap3xxx_l4_core_hwmod,
221 .slave = &omap3xxx_es3plus_mmc2_hwmod,
222 .clk = "mmchs2_ick",
223 .addr = omap2430_mmc2_addr_space,
224 .user = OCP_USER_MPU | OCP_USER_SDMA,
225 .flags = OMAP_FIREWALL_L4
226};
227
228/* L4 CORE -> MMC3 interface */
229static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
230 {
231 .pa_start = 0x480ad000,
232 .pa_end = 0x480ad1ff,
233 .flags = ADDR_TYPE_RT,
234 },
235 { }
236};
237
238static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
239 .master = &omap3xxx_l4_core_hwmod,
240 .slave = &omap3xxx_mmc3_hwmod,
241 .clk = "mmchs3_ick",
242 .addr = omap3xxx_mmc3_addr_space,
243 .user = OCP_USER_MPU | OCP_USER_SDMA,
244 .flags = OMAP_FIREWALL_L4
245};
246
247/* L4 CORE -> UART1 interface */
248static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
249 {
250 .pa_start = OMAP3_UART1_BASE,
251 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
252 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
253 },
254 { }
255};
256
257static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
258 .master = &omap3xxx_l4_core_hwmod,
259 .slave = &omap3xxx_uart1_hwmod,
260 .clk = "uart1_ick",
261 .addr = omap3xxx_uart1_addr_space,
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
263};
264
265/* L4 CORE -> UART2 interface */
266static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
267 {
268 .pa_start = OMAP3_UART2_BASE,
269 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
270 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
271 },
272 { }
273};
274
275static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
276 .master = &omap3xxx_l4_core_hwmod,
277 .slave = &omap3xxx_uart2_hwmod,
278 .clk = "uart2_ick",
279 .addr = omap3xxx_uart2_addr_space,
280 .user = OCP_USER_MPU | OCP_USER_SDMA,
281};
282
283/* L4 PER -> UART3 interface */
284static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
285 {
286 .pa_start = OMAP3_UART3_BASE,
287 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
288 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
289 },
290 { }
291};
292
293static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
294 .master = &omap3xxx_l4_per_hwmod,
295 .slave = &omap3xxx_uart3_hwmod,
296 .clk = "uart3_ick",
297 .addr = omap3xxx_uart3_addr_space,
298 .user = OCP_USER_MPU | OCP_USER_SDMA,
299};
300
301/* L4 PER -> UART4 interface */
302static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
303 {
304 .pa_start = OMAP3_UART4_BASE,
305 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
306 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
307 },
308 { }
309};
310
311static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
312 .master = &omap3xxx_l4_per_hwmod,
313 .slave = &omap36xx_uart4_hwmod,
314 .clk = "uart4_ick",
315 .addr = omap36xx_uart4_addr_space,
316 .user = OCP_USER_MPU | OCP_USER_SDMA,
317};
318
319/* AM35xx: L4 CORE -> UART4 interface */
320static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
321 {
322 .pa_start = OMAP3_UART4_AM35XX_BASE,
323 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
324 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
325 },
326};
327
328static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
329 .master = &omap3xxx_l4_core_hwmod,
330 .slave = &am35xx_uart4_hwmod,
331 .clk = "uart4_ick",
332 .addr = am35xx_uart4_addr_space,
333 .user = OCP_USER_MPU | OCP_USER_SDMA,
334};
335
336/* L4 CORE -> I2C1 interface */
337static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
338 .master = &omap3xxx_l4_core_hwmod,
339 .slave = &omap3xxx_i2c1_hwmod,
340 .clk = "i2c1_ick",
341 .addr = omap2_i2c1_addr_space,
342 .fw = {
343 .omap2 = {
344 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
345 .l4_prot_group = 7,
346 .flags = OMAP_FIREWALL_L4,
347 }
348 },
349 .user = OCP_USER_MPU | OCP_USER_SDMA,
350};
351
352/* L4 CORE -> I2C2 interface */
353static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
354 .master = &omap3xxx_l4_core_hwmod,
355 .slave = &omap3xxx_i2c2_hwmod,
356 .clk = "i2c2_ick",
357 .addr = omap2_i2c2_addr_space,
358 .fw = {
359 .omap2 = {
360 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
361 .l4_prot_group = 7,
362 .flags = OMAP_FIREWALL_L4,
363 }
364 },
365 .user = OCP_USER_MPU | OCP_USER_SDMA,
366};
367
368/* L4 CORE -> I2C3 interface */
369static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
370 {
371 .pa_start = 0x48060000,
372 .pa_end = 0x48060000 + SZ_128 - 1,
373 .flags = ADDR_TYPE_RT,
374 },
375 { }
376};
377
378static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
379 .master = &omap3xxx_l4_core_hwmod,
380 .slave = &omap3xxx_i2c3_hwmod,
381 .clk = "i2c3_ick",
382 .addr = omap3xxx_i2c3_addr_space,
383 .fw = {
384 .omap2 = {
385 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
386 .l4_prot_group = 7,
387 .flags = OMAP_FIREWALL_L4,
388 }
389 },
390 .user = OCP_USER_MPU | OCP_USER_SDMA,
391};
392
393static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
394 { .irq = 18},
395 { .irq = -1 }
396};
397
398static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
399 { .irq = 19},
400 { .irq = -1 }
401};
402
403/* L4 CORE -> SR1 interface */
404static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
405 {
406 .pa_start = OMAP34XX_SR1_BASE,
407 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
408 .flags = ADDR_TYPE_RT,
409 },
410 { }
411};
412
413static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
414 .master = &omap3xxx_l4_core_hwmod,
415 .slave = &omap34xx_sr1_hwmod,
416 .clk = "sr_l4_ick",
417 .addr = omap3_sr1_addr_space,
418 .user = OCP_USER_MPU,
419};
420
421/* L4 CORE -> SR1 interface */
422static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
423 {
424 .pa_start = OMAP34XX_SR2_BASE,
425 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
426 .flags = ADDR_TYPE_RT,
427 },
428 { }
429};
430
431static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
432 .master = &omap3xxx_l4_core_hwmod,
433 .slave = &omap34xx_sr2_hwmod,
434 .clk = "sr_l4_ick",
435 .addr = omap3_sr2_addr_space,
436 .user = OCP_USER_MPU,
437};
438
439/*
440* usbhsotg interface data
441*/
442
443static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
444 {
445 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
446 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
447 .flags = ADDR_TYPE_RT
448 },
449 { }
450};
451
452/* l4_core -> usbhsotg */
453static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
454 .master = &omap3xxx_l4_core_hwmod,
455 .slave = &omap3xxx_usbhsotg_hwmod,
456 .clk = "l4_ick",
457 .addr = omap3xxx_usbhsotg_addrs,
458 .user = OCP_USER_MPU,
459};
460
461static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
462 {
463 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
464 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
465 .flags = ADDR_TYPE_RT
466 },
467 { }
468};
469
470/* l4_core -> usbhsotg */
471static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
472 .master = &omap3xxx_l4_core_hwmod,
473 .slave = &am35xx_usbhsotg_hwmod,
474 .clk = "l4_ick",
475 .addr = am35xx_usbhsotg_addrs,
476 .user = OCP_USER_MPU,
477};
478
479/* L4 CORE */ 66/* L4 CORE */
480static struct omap_hwmod omap3xxx_l4_core_hwmod = { 67static struct omap_hwmod omap3xxx_l4_core_hwmod = {
481 .name = "l4_core", 68 .name = "l4_core",
@@ -490,13 +77,6 @@ static struct omap_hwmod omap3xxx_l4_per_hwmod = {
490 .flags = HWMOD_NO_IDLEST, 77 .flags = HWMOD_NO_IDLEST,
491}; 78};
492 79
493/* L4_WKUP -> L4_SEC interface */
494static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
495 .master = &omap3xxx_l4_wkup_hwmod,
496 .slave = &omap3xxx_l4_sec_hwmod,
497 .user = OCP_USER_MPU | OCP_USER_SDMA,
498};
499
500/* L4 WKUP */ 80/* L4 WKUP */
501static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 81static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
502 .name = "l4_wkup", 82 .name = "l4_wkup",
@@ -518,22 +98,7 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
518 .main_clk = "arm_fck", 98 .main_clk = "arm_fck",
519}; 99};
520 100
521/* 101/* IVA2 (IVA2) */
522 * IVA2_2 interface data
523 */
524
525/* IVA2 <- L3 interface */
526static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
527 .master = &omap3xxx_l3_main_hwmod,
528 .slave = &omap3xxx_iva_hwmod,
529 .clk = "iva2_ck",
530 .user = OCP_USER_MPU | OCP_USER_SDMA,
531};
532
533/*
534 * IVA2 (IVA2)
535 */
536
537static struct omap_hwmod omap3xxx_iva_hwmod = { 102static struct omap_hwmod omap3xxx_iva_hwmod = {
538 .name = "iva", 103 .name = "iva",
539 .class = &iva_hwmod_class, 104 .class = &iva_hwmod_class,
@@ -585,31 +150,10 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
585 150
586/* pwm timers dev attribute */ 151/* pwm timers dev attribute */
587static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 152static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
588 .timer_capability = OMAP_TIMER_HAS_PWM, 153 .timer_capability = OMAP_TIMER_HAS_PWM,
589}; 154};
590 155
591/* timer1 */ 156/* timer1 */
592static struct omap_hwmod omap3xxx_timer1_hwmod;
593
594static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
595 {
596 .pa_start = 0x48318000,
597 .pa_end = 0x48318000 + SZ_1K - 1,
598 .flags = ADDR_TYPE_RT
599 },
600 { }
601};
602
603/* l4_wkup -> timer1 */
604static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
605 .master = &omap3xxx_l4_wkup_hwmod,
606 .slave = &omap3xxx_timer1_hwmod,
607 .clk = "gpt1_ick",
608 .addr = omap3xxx_timer1_addrs,
609 .user = OCP_USER_MPU | OCP_USER_SDMA,
610};
611
612/* timer1 hwmod */
613static struct omap_hwmod omap3xxx_timer1_hwmod = { 157static struct omap_hwmod omap3xxx_timer1_hwmod = {
614 .name = "timer1", 158 .name = "timer1",
615 .mpu_irqs = omap2_timer1_mpu_irqs, 159 .mpu_irqs = omap2_timer1_mpu_irqs,
@@ -628,27 +172,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
628}; 172};
629 173
630/* timer2 */ 174/* timer2 */
631static struct omap_hwmod omap3xxx_timer2_hwmod;
632
633static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
634 {
635 .pa_start = 0x49032000,
636 .pa_end = 0x49032000 + SZ_1K - 1,
637 .flags = ADDR_TYPE_RT
638 },
639 { }
640};
641
642/* l4_per -> timer2 */
643static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
644 .master = &omap3xxx_l4_per_hwmod,
645 .slave = &omap3xxx_timer2_hwmod,
646 .clk = "gpt2_ick",
647 .addr = omap3xxx_timer2_addrs,
648 .user = OCP_USER_MPU | OCP_USER_SDMA,
649};
650
651/* timer2 hwmod */
652static struct omap_hwmod omap3xxx_timer2_hwmod = { 175static struct omap_hwmod omap3xxx_timer2_hwmod = {
653 .name = "timer2", 176 .name = "timer2",
654 .mpu_irqs = omap2_timer2_mpu_irqs, 177 .mpu_irqs = omap2_timer2_mpu_irqs,
@@ -667,27 +190,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
667}; 190};
668 191
669/* timer3 */ 192/* timer3 */
670static struct omap_hwmod omap3xxx_timer3_hwmod;
671
672static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
673 {
674 .pa_start = 0x49034000,
675 .pa_end = 0x49034000 + SZ_1K - 1,
676 .flags = ADDR_TYPE_RT
677 },
678 { }
679};
680
681/* l4_per -> timer3 */
682static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
683 .master = &omap3xxx_l4_per_hwmod,
684 .slave = &omap3xxx_timer3_hwmod,
685 .clk = "gpt3_ick",
686 .addr = omap3xxx_timer3_addrs,
687 .user = OCP_USER_MPU | OCP_USER_SDMA,
688};
689
690/* timer3 hwmod */
691static struct omap_hwmod omap3xxx_timer3_hwmod = { 193static struct omap_hwmod omap3xxx_timer3_hwmod = {
692 .name = "timer3", 194 .name = "timer3",
693 .mpu_irqs = omap2_timer3_mpu_irqs, 195 .mpu_irqs = omap2_timer3_mpu_irqs,
@@ -706,27 +208,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
706}; 208};
707 209
708/* timer4 */ 210/* timer4 */
709static struct omap_hwmod omap3xxx_timer4_hwmod;
710
711static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
712 {
713 .pa_start = 0x49036000,
714 .pa_end = 0x49036000 + SZ_1K - 1,
715 .flags = ADDR_TYPE_RT
716 },
717 { }
718};
719
720/* l4_per -> timer4 */
721static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
722 .master = &omap3xxx_l4_per_hwmod,
723 .slave = &omap3xxx_timer4_hwmod,
724 .clk = "gpt4_ick",
725 .addr = omap3xxx_timer4_addrs,
726 .user = OCP_USER_MPU | OCP_USER_SDMA,
727};
728
729/* timer4 hwmod */
730static struct omap_hwmod omap3xxx_timer4_hwmod = { 211static struct omap_hwmod omap3xxx_timer4_hwmod = {
731 .name = "timer4", 212 .name = "timer4",
732 .mpu_irqs = omap2_timer4_mpu_irqs, 213 .mpu_irqs = omap2_timer4_mpu_irqs,
@@ -745,27 +226,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
745}; 226};
746 227
747/* timer5 */ 228/* timer5 */
748static struct omap_hwmod omap3xxx_timer5_hwmod;
749
750static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
751 {
752 .pa_start = 0x49038000,
753 .pa_end = 0x49038000 + SZ_1K - 1,
754 .flags = ADDR_TYPE_RT
755 },
756 { }
757};
758
759/* l4_per -> timer5 */
760static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
761 .master = &omap3xxx_l4_per_hwmod,
762 .slave = &omap3xxx_timer5_hwmod,
763 .clk = "gpt5_ick",
764 .addr = omap3xxx_timer5_addrs,
765 .user = OCP_USER_MPU | OCP_USER_SDMA,
766};
767
768/* timer5 hwmod */
769static struct omap_hwmod omap3xxx_timer5_hwmod = { 229static struct omap_hwmod omap3xxx_timer5_hwmod = {
770 .name = "timer5", 230 .name = "timer5",
771 .mpu_irqs = omap2_timer5_mpu_irqs, 231 .mpu_irqs = omap2_timer5_mpu_irqs,
@@ -784,27 +244,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
784}; 244};
785 245
786/* timer6 */ 246/* timer6 */
787static struct omap_hwmod omap3xxx_timer6_hwmod;
788
789static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
790 {
791 .pa_start = 0x4903A000,
792 .pa_end = 0x4903A000 + SZ_1K - 1,
793 .flags = ADDR_TYPE_RT
794 },
795 { }
796};
797
798/* l4_per -> timer6 */
799static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
800 .master = &omap3xxx_l4_per_hwmod,
801 .slave = &omap3xxx_timer6_hwmod,
802 .clk = "gpt6_ick",
803 .addr = omap3xxx_timer6_addrs,
804 .user = OCP_USER_MPU | OCP_USER_SDMA,
805};
806
807/* timer6 hwmod */
808static struct omap_hwmod omap3xxx_timer6_hwmod = { 247static struct omap_hwmod omap3xxx_timer6_hwmod = {
809 .name = "timer6", 248 .name = "timer6",
810 .mpu_irqs = omap2_timer6_mpu_irqs, 249 .mpu_irqs = omap2_timer6_mpu_irqs,
@@ -823,27 +262,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
823}; 262};
824 263
825/* timer7 */ 264/* timer7 */
826static struct omap_hwmod omap3xxx_timer7_hwmod;
827
828static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
829 {
830 .pa_start = 0x4903C000,
831 .pa_end = 0x4903C000 + SZ_1K - 1,
832 .flags = ADDR_TYPE_RT
833 },
834 { }
835};
836
837/* l4_per -> timer7 */
838static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
839 .master = &omap3xxx_l4_per_hwmod,
840 .slave = &omap3xxx_timer7_hwmod,
841 .clk = "gpt7_ick",
842 .addr = omap3xxx_timer7_addrs,
843 .user = OCP_USER_MPU | OCP_USER_SDMA,
844};
845
846/* timer7 hwmod */
847static struct omap_hwmod omap3xxx_timer7_hwmod = { 265static struct omap_hwmod omap3xxx_timer7_hwmod = {
848 .name = "timer7", 266 .name = "timer7",
849 .mpu_irqs = omap2_timer7_mpu_irqs, 267 .mpu_irqs = omap2_timer7_mpu_irqs,
@@ -862,27 +280,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
862}; 280};
863 281
864/* timer8 */ 282/* timer8 */
865static struct omap_hwmod omap3xxx_timer8_hwmod;
866
867static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
868 {
869 .pa_start = 0x4903E000,
870 .pa_end = 0x4903E000 + SZ_1K - 1,
871 .flags = ADDR_TYPE_RT
872 },
873 { }
874};
875
876/* l4_per -> timer8 */
877static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
878 .master = &omap3xxx_l4_per_hwmod,
879 .slave = &omap3xxx_timer8_hwmod,
880 .clk = "gpt8_ick",
881 .addr = omap3xxx_timer8_addrs,
882 .user = OCP_USER_MPU | OCP_USER_SDMA,
883};
884
885/* timer8 hwmod */
886static struct omap_hwmod omap3xxx_timer8_hwmod = { 283static struct omap_hwmod omap3xxx_timer8_hwmod = {
887 .name = "timer8", 284 .name = "timer8",
888 .mpu_irqs = omap2_timer8_mpu_irqs, 285 .mpu_irqs = omap2_timer8_mpu_irqs,
@@ -901,27 +298,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
901}; 298};
902 299
903/* timer9 */ 300/* timer9 */
904static struct omap_hwmod omap3xxx_timer9_hwmod;
905
906static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
907 {
908 .pa_start = 0x49040000,
909 .pa_end = 0x49040000 + SZ_1K - 1,
910 .flags = ADDR_TYPE_RT
911 },
912 { }
913};
914
915/* l4_per -> timer9 */
916static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
917 .master = &omap3xxx_l4_per_hwmod,
918 .slave = &omap3xxx_timer9_hwmod,
919 .clk = "gpt9_ick",
920 .addr = omap3xxx_timer9_addrs,
921 .user = OCP_USER_MPU | OCP_USER_SDMA,
922};
923
924/* timer9 hwmod */
925static struct omap_hwmod omap3xxx_timer9_hwmod = { 301static struct omap_hwmod omap3xxx_timer9_hwmod = {
926 .name = "timer9", 302 .name = "timer9",
927 .mpu_irqs = omap2_timer9_mpu_irqs, 303 .mpu_irqs = omap2_timer9_mpu_irqs,
@@ -940,18 +316,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
940}; 316};
941 317
942/* timer10 */ 318/* timer10 */
943static struct omap_hwmod omap3xxx_timer10_hwmod;
944
945/* l4_core -> timer10 */
946static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
947 .master = &omap3xxx_l4_core_hwmod,
948 .slave = &omap3xxx_timer10_hwmod,
949 .clk = "gpt10_ick",
950 .addr = omap2_timer10_addrs,
951 .user = OCP_USER_MPU | OCP_USER_SDMA,
952};
953
954/* timer10 hwmod */
955static struct omap_hwmod omap3xxx_timer10_hwmod = { 319static struct omap_hwmod omap3xxx_timer10_hwmod = {
956 .name = "timer10", 320 .name = "timer10",
957 .mpu_irqs = omap2_timer10_mpu_irqs, 321 .mpu_irqs = omap2_timer10_mpu_irqs,
@@ -970,18 +334,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
970}; 334};
971 335
972/* timer11 */ 336/* timer11 */
973static struct omap_hwmod omap3xxx_timer11_hwmod;
974
975/* l4_core -> timer11 */
976static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
977 .master = &omap3xxx_l4_core_hwmod,
978 .slave = &omap3xxx_timer11_hwmod,
979 .clk = "gpt11_ick",
980 .addr = omap2_timer11_addrs,
981 .user = OCP_USER_MPU | OCP_USER_SDMA,
982};
983
984/* timer11 hwmod */
985static struct omap_hwmod omap3xxx_timer11_hwmod = { 337static struct omap_hwmod omap3xxx_timer11_hwmod = {
986 .name = "timer11", 338 .name = "timer11",
987 .mpu_irqs = omap2_timer11_mpu_irqs, 339 .mpu_irqs = omap2_timer11_mpu_irqs,
@@ -1000,31 +352,11 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
1000}; 352};
1001 353
1002/* timer12 */ 354/* timer12 */
1003static struct omap_hwmod omap3xxx_timer12_hwmod;
1004static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 355static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1005 { .irq = 95, }, 356 { .irq = 95, },
1006 { .irq = -1 } 357 { .irq = -1 }
1007}; 358};
1008 359
1009static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1010 {
1011 .pa_start = 0x48304000,
1012 .pa_end = 0x48304000 + SZ_1K - 1,
1013 .flags = ADDR_TYPE_RT
1014 },
1015 { }
1016};
1017
1018/* l4_core -> timer12 */
1019static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
1020 .master = &omap3xxx_l4_sec_hwmod,
1021 .slave = &omap3xxx_timer12_hwmod,
1022 .clk = "gpt12_ick",
1023 .addr = omap3xxx_timer12_addrs,
1024 .user = OCP_USER_MPU | OCP_USER_SDMA,
1025};
1026
1027/* timer12 hwmod */
1028static struct omap_hwmod omap3xxx_timer12_hwmod = { 360static struct omap_hwmod omap3xxx_timer12_hwmod = {
1029 .name = "timer12", 361 .name = "timer12",
1030 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 362 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
@@ -1042,24 +374,6 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
1042 .class = &omap3xxx_timer_hwmod_class, 374 .class = &omap3xxx_timer_hwmod_class,
1043}; 375};
1044 376
1045/* l4_wkup -> wd_timer2 */
1046static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1047 {
1048 .pa_start = 0x48314000,
1049 .pa_end = 0x4831407f,
1050 .flags = ADDR_TYPE_RT
1051 },
1052 { }
1053};
1054
1055static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1056 .master = &omap3xxx_l4_wkup_hwmod,
1057 .slave = &omap3xxx_wd_timer2_hwmod,
1058 .clk = "wdt2_ick",
1059 .addr = omap3xxx_wd_timer2_addrs,
1060 .user = OCP_USER_MPU | OCP_USER_SDMA,
1061};
1062
1063/* 377/*
1064 * 'wd_timer' class 378 * 'wd_timer' class
1065 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 379 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
@@ -1172,7 +486,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1172}; 486};
1173 487
1174/* UART4 */ 488/* UART4 */
1175
1176static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 489static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1177 { .irq = INT_36XX_UART4_IRQ, }, 490 { .irq = INT_36XX_UART4_IRQ, },
1178 { .irq = -1 } 491 { .irq = -1 }
@@ -1227,7 +540,6 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
1227 .class = &omap2_uart_class, 540 .class = &omap2_uart_class,
1228}; 541};
1229 542
1230
1231static struct omap_hwmod_class i2c_class = { 543static struct omap_hwmod_class i2c_class = {
1232 .name = "i2c", 544 .name = "i2c",
1233 .sysc = &i2c_sysc, 545 .sysc = &i2c_sysc,
@@ -1242,38 +554,6 @@ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1242}; 554};
1243 555
1244/* dss */ 556/* dss */
1245
1246/* l4_core -> dss */
1247static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1248 .master = &omap3xxx_l4_core_hwmod,
1249 .slave = &omap3430es1_dss_core_hwmod,
1250 .clk = "dss_ick",
1251 .addr = omap2_dss_addrs,
1252 .fw = {
1253 .omap2 = {
1254 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1255 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1256 .flags = OMAP_FIREWALL_L4,
1257 }
1258 },
1259 .user = OCP_USER_MPU | OCP_USER_SDMA,
1260};
1261
1262static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1263 .master = &omap3xxx_l4_core_hwmod,
1264 .slave = &omap3xxx_dss_core_hwmod,
1265 .clk = "dss_ick",
1266 .addr = omap2_dss_addrs,
1267 .fw = {
1268 .omap2 = {
1269 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1270 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1271 .flags = OMAP_FIREWALL_L4,
1272 }
1273 },
1274 .user = OCP_USER_MPU | OCP_USER_SDMA,
1275};
1276
1277static struct omap_hwmod_opt_clk dss_opt_clks[] = { 557static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1278 /* 558 /*
1279 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 559 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
@@ -1346,22 +626,6 @@ static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1346 .sysc = &omap3_dispc_sysc, 626 .sysc = &omap3_dispc_sysc,
1347}; 627};
1348 628
1349/* l4_core -> dss_dispc */
1350static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1351 .master = &omap3xxx_l4_core_hwmod,
1352 .slave = &omap3xxx_dss_dispc_hwmod,
1353 .clk = "dss_ick",
1354 .addr = omap2_dss_dispc_addrs,
1355 .fw = {
1356 .omap2 = {
1357 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1358 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1359 .flags = OMAP_FIREWALL_L4,
1360 }
1361 },
1362 .user = OCP_USER_MPU | OCP_USER_SDMA,
1363};
1364
1365static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 629static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1366 .name = "dss_dispc", 630 .name = "dss_dispc",
1367 .class = &omap3_dispc_hwmod_class, 631 .class = &omap3_dispc_hwmod_class,
@@ -1393,31 +657,6 @@ static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1393}; 657};
1394 658
1395/* dss_dsi1 */ 659/* dss_dsi1 */
1396static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1397 {
1398 .pa_start = 0x4804FC00,
1399 .pa_end = 0x4804FFFF,
1400 .flags = ADDR_TYPE_RT
1401 },
1402 { }
1403};
1404
1405/* l4_core -> dss_dsi1 */
1406static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1407 .master = &omap3xxx_l4_core_hwmod,
1408 .slave = &omap3xxx_dss_dsi1_hwmod,
1409 .clk = "dss_ick",
1410 .addr = omap3xxx_dss_dsi1_addrs,
1411 .fw = {
1412 .omap2 = {
1413 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1414 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1415 .flags = OMAP_FIREWALL_L4,
1416 }
1417 },
1418 .user = OCP_USER_MPU | OCP_USER_SDMA,
1419};
1420
1421static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 660static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1422 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 661 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1423}; 662};
@@ -1439,22 +678,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1439 .flags = HWMOD_NO_IDLEST, 678 .flags = HWMOD_NO_IDLEST,
1440}; 679};
1441 680
1442/* l4_core -> dss_rfbi */
1443static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1444 .master = &omap3xxx_l4_core_hwmod,
1445 .slave = &omap3xxx_dss_rfbi_hwmod,
1446 .clk = "dss_ick",
1447 .addr = omap2_dss_rfbi_addrs,
1448 .fw = {
1449 .omap2 = {
1450 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1451 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1452 .flags = OMAP_FIREWALL_L4,
1453 }
1454 },
1455 .user = OCP_USER_MPU | OCP_USER_SDMA,
1456};
1457
1458static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 681static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1459 { .role = "ick", .clk = "dss_ick" }, 682 { .role = "ick", .clk = "dss_ick" },
1460}; 683};
@@ -1475,22 +698,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1475 .flags = HWMOD_NO_IDLEST, 698 .flags = HWMOD_NO_IDLEST,
1476}; 699};
1477 700
1478/* l4_core -> dss_venc */
1479static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1480 .master = &omap3xxx_l4_core_hwmod,
1481 .slave = &omap3xxx_dss_venc_hwmod,
1482 .clk = "dss_ick",
1483 .addr = omap2_dss_venc_addrs,
1484 .fw = {
1485 .omap2 = {
1486 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1487 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1488 .flags = OMAP_FIREWALL_L4,
1489 }
1490 },
1491 .user = OCP_USER_MPU | OCP_USER_SDMA,
1492};
1493
1494static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 701static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1495 /* required only on OMAP3430 */ 702 /* required only on OMAP3430 */
1496 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 703 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
@@ -1513,7 +720,6 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1513}; 720};
1514 721
1515/* I2C1 */ 722/* I2C1 */
1516
1517static struct omap_i2c_dev_attr i2c1_dev_attr = { 723static struct omap_i2c_dev_attr i2c1_dev_attr = {
1518 .fifo_depth = 8, /* bytes */ 724 .fifo_depth = 8, /* bytes */
1519 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 725 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1541,7 +747,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1541}; 747};
1542 748
1543/* I2C2 */ 749/* I2C2 */
1544
1545static struct omap_i2c_dev_attr i2c2_dev_attr = { 750static struct omap_i2c_dev_attr i2c2_dev_attr = {
1546 .fifo_depth = 8, /* bytes */ 751 .fifo_depth = 8, /* bytes */
1547 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 752 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1569,7 +774,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1569}; 774};
1570 775
1571/* I2C3 */ 776/* I2C3 */
1572
1573static struct omap_i2c_dev_attr i2c3_dev_attr = { 777static struct omap_i2c_dev_attr i2c3_dev_attr = {
1574 .fifo_depth = 64, /* bytes */ 778 .fifo_depth = 64, /* bytes */
1575 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 779 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1607,108 +811,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1607 .dev_attr = &i2c3_dev_attr, 811 .dev_attr = &i2c3_dev_attr,
1608}; 812};
1609 813
1610/* l4_wkup -> gpio1 */
1611static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1612 {
1613 .pa_start = 0x48310000,
1614 .pa_end = 0x483101ff,
1615 .flags = ADDR_TYPE_RT
1616 },
1617 { }
1618};
1619
1620static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1621 .master = &omap3xxx_l4_wkup_hwmod,
1622 .slave = &omap3xxx_gpio1_hwmod,
1623 .addr = omap3xxx_gpio1_addrs,
1624 .user = OCP_USER_MPU | OCP_USER_SDMA,
1625};
1626
1627/* l4_per -> gpio2 */
1628static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1629 {
1630 .pa_start = 0x49050000,
1631 .pa_end = 0x490501ff,
1632 .flags = ADDR_TYPE_RT
1633 },
1634 { }
1635};
1636
1637static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1638 .master = &omap3xxx_l4_per_hwmod,
1639 .slave = &omap3xxx_gpio2_hwmod,
1640 .addr = omap3xxx_gpio2_addrs,
1641 .user = OCP_USER_MPU | OCP_USER_SDMA,
1642};
1643
1644/* l4_per -> gpio3 */
1645static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1646 {
1647 .pa_start = 0x49052000,
1648 .pa_end = 0x490521ff,
1649 .flags = ADDR_TYPE_RT
1650 },
1651 { }
1652};
1653
1654static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1655 .master = &omap3xxx_l4_per_hwmod,
1656 .slave = &omap3xxx_gpio3_hwmod,
1657 .addr = omap3xxx_gpio3_addrs,
1658 .user = OCP_USER_MPU | OCP_USER_SDMA,
1659};
1660
1661/* l4_per -> gpio4 */
1662static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1663 {
1664 .pa_start = 0x49054000,
1665 .pa_end = 0x490541ff,
1666 .flags = ADDR_TYPE_RT
1667 },
1668 { }
1669};
1670
1671static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1672 .master = &omap3xxx_l4_per_hwmod,
1673 .slave = &omap3xxx_gpio4_hwmod,
1674 .addr = omap3xxx_gpio4_addrs,
1675 .user = OCP_USER_MPU | OCP_USER_SDMA,
1676};
1677
1678/* l4_per -> gpio5 */
1679static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1680 {
1681 .pa_start = 0x49056000,
1682 .pa_end = 0x490561ff,
1683 .flags = ADDR_TYPE_RT
1684 },
1685 { }
1686};
1687
1688static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1689 .master = &omap3xxx_l4_per_hwmod,
1690 .slave = &omap3xxx_gpio5_hwmod,
1691 .addr = omap3xxx_gpio5_addrs,
1692 .user = OCP_USER_MPU | OCP_USER_SDMA,
1693};
1694
1695/* l4_per -> gpio6 */
1696static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1697 {
1698 .pa_start = 0x49058000,
1699 .pa_end = 0x490581ff,
1700 .flags = ADDR_TYPE_RT
1701 },
1702 { }
1703};
1704
1705static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1706 .master = &omap3xxx_l4_per_hwmod,
1707 .slave = &omap3xxx_gpio6_hwmod,
1708 .addr = omap3xxx_gpio6_addrs,
1709 .user = OCP_USER_MPU | OCP_USER_SDMA,
1710};
1711
1712/* 814/*
1713 * 'gpio' class 815 * 'gpio' class
1714 * general purpose io module 816 * general purpose io module
@@ -1731,7 +833,7 @@ static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1731 .rev = 1, 833 .rev = 1,
1732}; 834};
1733 835
1734/* gpio_dev_attr*/ 836/* gpio_dev_attr */
1735static struct omap_gpio_dev_attr gpio_dev_attr = { 837static struct omap_gpio_dev_attr gpio_dev_attr = {
1736 .bank_width = 32, 838 .bank_width = 32,
1737 .dbck_flag = true, 839 .dbck_flag = true,
@@ -1897,14 +999,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1897 .dev_attr = &gpio_dev_attr, 999 .dev_attr = &gpio_dev_attr,
1898}; 1000};
1899 1001
1900/* dma_system -> L3 */
1901static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
1902 .master = &omap3xxx_dma_system_hwmod,
1903 .slave = &omap3xxx_l3_main_hwmod,
1904 .clk = "core_l3_ick",
1905 .user = OCP_USER_MPU | OCP_USER_SDMA,
1906};
1907
1908/* dma attributes */ 1002/* dma attributes */
1909static struct omap_dma_dev_attr dma_dev_attr = { 1003static struct omap_dma_dev_attr dma_dev_attr = {
1910 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1004 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1931,24 +1025,6 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1931}; 1025};
1932 1026
1933/* dma_system */ 1027/* dma_system */
1934static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
1935 {
1936 .pa_start = 0x48056000,
1937 .pa_end = 0x48056fff,
1938 .flags = ADDR_TYPE_RT
1939 },
1940 { }
1941};
1942
1943/* l4_cfg -> dma_system */
1944static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
1945 .master = &omap3xxx_l4_core_hwmod,
1946 .slave = &omap3xxx_dma_system_hwmod,
1947 .clk = "core_l4_ick",
1948 .addr = omap3xxx_dma_system_addrs,
1949 .user = OCP_USER_MPU | OCP_USER_SDMA,
1950};
1951
1952static struct omap_hwmod omap3xxx_dma_system_hwmod = { 1028static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1953 .name = "dma", 1029 .name = "dma",
1954 .class = &omap3xxx_dma_hwmod_class, 1030 .class = &omap3xxx_dma_hwmod_class,
@@ -1995,25 +1071,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1995 { .irq = -1 } 1071 { .irq = -1 }
1996}; 1072};
1997 1073
1998static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
1999 {
2000 .name = "mpu",
2001 .pa_start = 0x48074000,
2002 .pa_end = 0x480740ff,
2003 .flags = ADDR_TYPE_RT
2004 },
2005 { }
2006};
2007
2008/* l4_core -> mcbsp1 */
2009static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2010 .master = &omap3xxx_l4_core_hwmod,
2011 .slave = &omap3xxx_mcbsp1_hwmod,
2012 .clk = "mcbsp1_ick",
2013 .addr = omap3xxx_mcbsp1_addrs,
2014 .user = OCP_USER_MPU | OCP_USER_SDMA,
2015};
2016
2017static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1074static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2018 .name = "mcbsp1", 1075 .name = "mcbsp1",
2019 .class = &omap3xxx_mcbsp_hwmod_class, 1076 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2039,25 +1096,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2039 { .irq = -1 } 1096 { .irq = -1 }
2040}; 1097};
2041 1098
2042static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2043 {
2044 .name = "mpu",
2045 .pa_start = 0x49022000,
2046 .pa_end = 0x490220ff,
2047 .flags = ADDR_TYPE_RT
2048 },
2049 { }
2050};
2051
2052/* l4_per -> mcbsp2 */
2053static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2054 .master = &omap3xxx_l4_per_hwmod,
2055 .slave = &omap3xxx_mcbsp2_hwmod,
2056 .clk = "mcbsp2_ick",
2057 .addr = omap3xxx_mcbsp2_addrs,
2058 .user = OCP_USER_MPU | OCP_USER_SDMA,
2059};
2060
2061static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1099static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2062 .sidetone = "mcbsp2_sidetone", 1100 .sidetone = "mcbsp2_sidetone",
2063}; 1101};
@@ -2088,25 +1126,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2088 { .irq = -1 } 1126 { .irq = -1 }
2089}; 1127};
2090 1128
2091static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2092 {
2093 .name = "mpu",
2094 .pa_start = 0x49024000,
2095 .pa_end = 0x490240ff,
2096 .flags = ADDR_TYPE_RT
2097 },
2098 { }
2099};
2100
2101/* l4_per -> mcbsp3 */
2102static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2103 .master = &omap3xxx_l4_per_hwmod,
2104 .slave = &omap3xxx_mcbsp3_hwmod,
2105 .clk = "mcbsp3_ick",
2106 .addr = omap3xxx_mcbsp3_addrs,
2107 .user = OCP_USER_MPU | OCP_USER_SDMA,
2108};
2109
2110static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1129static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2111 .sidetone = "mcbsp3_sidetone", 1130 .sidetone = "mcbsp3_sidetone",
2112}; 1131};
@@ -2143,25 +1162,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2143 { .dma_req = -1 } 1162 { .dma_req = -1 }
2144}; 1163};
2145 1164
2146static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2147 {
2148 .name = "mpu",
2149 .pa_start = 0x49026000,
2150 .pa_end = 0x490260ff,
2151 .flags = ADDR_TYPE_RT
2152 },
2153 { }
2154};
2155
2156/* l4_per -> mcbsp4 */
2157static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2158 .master = &omap3xxx_l4_per_hwmod,
2159 .slave = &omap3xxx_mcbsp4_hwmod,
2160 .clk = "mcbsp4_ick",
2161 .addr = omap3xxx_mcbsp4_addrs,
2162 .user = OCP_USER_MPU | OCP_USER_SDMA,
2163};
2164
2165static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1165static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2166 .name = "mcbsp4", 1166 .name = "mcbsp4",
2167 .class = &omap3xxx_mcbsp_hwmod_class, 1167 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2193,25 +1193,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2193 { .dma_req = -1 } 1193 { .dma_req = -1 }
2194}; 1194};
2195 1195
2196static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2197 {
2198 .name = "mpu",
2199 .pa_start = 0x48096000,
2200 .pa_end = 0x480960ff,
2201 .flags = ADDR_TYPE_RT
2202 },
2203 { }
2204};
2205
2206/* l4_core -> mcbsp5 */
2207static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2208 .master = &omap3xxx_l4_core_hwmod,
2209 .slave = &omap3xxx_mcbsp5_hwmod,
2210 .clk = "mcbsp5_ick",
2211 .addr = omap3xxx_mcbsp5_addrs,
2212 .user = OCP_USER_MPU | OCP_USER_SDMA,
2213};
2214
2215static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1196static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2216 .name = "mcbsp5", 1197 .name = "mcbsp5",
2217 .class = &omap3xxx_mcbsp_hwmod_class, 1198 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2228,8 +1209,8 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2228 }, 1209 },
2229 }, 1210 },
2230}; 1211};
2231/* 'mcbsp sidetone' class */
2232 1212
1213/* 'mcbsp sidetone' class */
2233static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 1214static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2234 .sysc_offs = 0x0010, 1215 .sysc_offs = 0x0010,
2235 .sysc_flags = SYSC_HAS_AUTOIDLE, 1216 .sysc_flags = SYSC_HAS_AUTOIDLE,
@@ -2247,25 +1228,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2247 { .irq = -1 } 1228 { .irq = -1 }
2248}; 1229};
2249 1230
2250static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2251 {
2252 .name = "sidetone",
2253 .pa_start = 0x49028000,
2254 .pa_end = 0x490280ff,
2255 .flags = ADDR_TYPE_RT
2256 },
2257 { }
2258};
2259
2260/* l4_per -> mcbsp2_sidetone */
2261static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2262 .master = &omap3xxx_l4_per_hwmod,
2263 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2264 .clk = "mcbsp2_ick",
2265 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2266 .user = OCP_USER_MPU,
2267};
2268
2269static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1231static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2270 .name = "mcbsp2_sidetone", 1232 .name = "mcbsp2_sidetone",
2271 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1233 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2288,25 +1250,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2288 { .irq = -1 } 1250 { .irq = -1 }
2289}; 1251};
2290 1252
2291static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2292 {
2293 .name = "sidetone",
2294 .pa_start = 0x4902A000,
2295 .pa_end = 0x4902A0ff,
2296 .flags = ADDR_TYPE_RT
2297 },
2298 { }
2299};
2300
2301/* l4_per -> mcbsp3_sidetone */
2302static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2303 .master = &omap3xxx_l4_per_hwmod,
2304 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2305 .clk = "mcbsp3_ick",
2306 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2307 .user = OCP_USER_MPU,
2308};
2309
2310static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1253static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2311 .name = "mcbsp3_sidetone", 1254 .name = "mcbsp3_sidetone",
2312 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1255 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2323,7 +1266,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2323 }, 1266 },
2324}; 1267};
2325 1268
2326
2327/* SR common */ 1269/* SR common */
2328static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 1270static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2329 .clkact_shift = 20, 1271 .clkact_shift = 20,
@@ -2344,7 +1286,7 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2344 1286
2345static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { 1287static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2346 .sidle_shift = 24, 1288 .sidle_shift = 24,
2347 .enwkup_shift = 26 1289 .enwkup_shift = 26,
2348}; 1290};
2349 1291
2350static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 1292static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
@@ -2366,6 +1308,11 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2366 .sensor_voltdm_name = "mpu_iva", 1308 .sensor_voltdm_name = "mpu_iva",
2367}; 1309};
2368 1310
1311static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1312 { .irq = 18 },
1313 { .irq = -1 }
1314};
1315
2369static struct omap_hwmod omap34xx_sr1_hwmod = { 1316static struct omap_hwmod omap34xx_sr1_hwmod = {
2370 .name = "sr1", 1317 .name = "sr1",
2371 .class = &omap34xx_smartreflex_hwmod_class, 1318 .class = &omap34xx_smartreflex_hwmod_class,
@@ -2406,6 +1353,11 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2406 .sensor_voltdm_name = "core", 1353 .sensor_voltdm_name = "core",
2407}; 1354};
2408 1355
1356static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1357 { .irq = 19 },
1358 { .irq = -1 }
1359};
1360
2409static struct omap_hwmod omap34xx_sr2_hwmod = { 1361static struct omap_hwmod omap34xx_sr2_hwmod = {
2410 .name = "sr2", 1362 .name = "sr2",
2411 .class = &omap34xx_smartreflex_hwmod_class, 1363 .class = &omap34xx_smartreflex_hwmod_class,
@@ -2462,29 +1414,11 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2462 .sysc = &omap3xxx_mailbox_sysc, 1414 .sysc = &omap3xxx_mailbox_sysc,
2463}; 1415};
2464 1416
2465static struct omap_hwmod omap3xxx_mailbox_hwmod;
2466static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 1417static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2467 { .irq = 26 }, 1418 { .irq = 26 },
2468 { .irq = -1 } 1419 { .irq = -1 }
2469}; 1420};
2470 1421
2471static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2472 {
2473 .pa_start = 0x48094000,
2474 .pa_end = 0x480941ff,
2475 .flags = ADDR_TYPE_RT,
2476 },
2477 { }
2478};
2479
2480/* l4_core -> mailbox */
2481static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2482 .master = &omap3xxx_l4_core_hwmod,
2483 .slave = &omap3xxx_mailbox_hwmod,
2484 .addr = omap3xxx_mailbox_addrs,
2485 .user = OCP_USER_MPU | OCP_USER_SDMA,
2486};
2487
2488static struct omap_hwmod omap3xxx_mailbox_hwmod = { 1422static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2489 .name = "mailbox", 1423 .name = "mailbox",
2490 .class = &omap3xxx_mailbox_hwmod_class, 1424 .class = &omap3xxx_mailbox_hwmod_class,
@@ -2501,51 +1435,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2501 }, 1435 },
2502}; 1436};
2503 1437
2504/* l4 core -> mcspi1 interface */
2505static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2506 .master = &omap3xxx_l4_core_hwmod,
2507 .slave = &omap34xx_mcspi1,
2508 .clk = "mcspi1_ick",
2509 .addr = omap2_mcspi1_addr_space,
2510 .user = OCP_USER_MPU | OCP_USER_SDMA,
2511};
2512
2513/* l4 core -> mcspi2 interface */
2514static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2515 .master = &omap3xxx_l4_core_hwmod,
2516 .slave = &omap34xx_mcspi2,
2517 .clk = "mcspi2_ick",
2518 .addr = omap2_mcspi2_addr_space,
2519 .user = OCP_USER_MPU | OCP_USER_SDMA,
2520};
2521
2522/* l4 core -> mcspi3 interface */
2523static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2524 .master = &omap3xxx_l4_core_hwmod,
2525 .slave = &omap34xx_mcspi3,
2526 .clk = "mcspi3_ick",
2527 .addr = omap2430_mcspi3_addr_space,
2528 .user = OCP_USER_MPU | OCP_USER_SDMA,
2529};
2530
2531/* l4 core -> mcspi4 interface */
2532static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2533 {
2534 .pa_start = 0x480ba000,
2535 .pa_end = 0x480ba0ff,
2536 .flags = ADDR_TYPE_RT,
2537 },
2538 { }
2539};
2540
2541static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2542 .master = &omap3xxx_l4_core_hwmod,
2543 .slave = &omap34xx_mcspi4,
2544 .clk = "mcspi4_ick",
2545 .addr = omap34xx_mcspi4_addr_space,
2546 .user = OCP_USER_MPU | OCP_USER_SDMA,
2547};
2548
2549/* 1438/*
2550 * 'mcspi' class 1439 * 'mcspi' class
2551 * multichannel serial port interface (mcspi) / master/slave synchronous serial 1440 * multichannel serial port interface (mcspi) / master/slave synchronous serial
@@ -2651,7 +1540,7 @@ static struct omap_hwmod omap34xx_mcspi3 = {
2651 .dev_attr = &omap_mcspi3_dev_attr, 1540 .dev_attr = &omap_mcspi3_dev_attr,
2652}; 1541};
2653 1542
2654/* SPI4 */ 1543/* mcspi4 */
2655static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 1544static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2656 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ 1545 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2657 { .irq = -1 } 1546 { .irq = -1 }
@@ -2685,9 +1574,7 @@ static struct omap_hwmod omap34xx_mcspi4 = {
2685 .dev_attr = &omap_mcspi4_dev_attr, 1574 .dev_attr = &omap_mcspi4_dev_attr,
2686}; 1575};
2687 1576
2688/* 1577/* usbhsotg */
2689 * usbhsotg
2690 */
2691static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { 1578static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2692 .rev_offs = 0x0400, 1579 .rev_offs = 0x0400,
2693 .sysc_offs = 0x0404, 1580 .sysc_offs = 0x0404,
@@ -2704,6 +1591,7 @@ static struct omap_hwmod_class usbotg_class = {
2704 .name = "usbotg", 1591 .name = "usbotg",
2705 .sysc = &omap3xxx_usbhsotg_sysc, 1592 .sysc = &omap3xxx_usbhsotg_sysc,
2706}; 1593};
1594
2707/* usb_otg_hs */ 1595/* usb_otg_hs */
2708static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { 1596static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2709 1597
@@ -2761,7 +1649,6 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
2761}; 1649};
2762 1650
2763/* MMC/SD/SDIO common */ 1651/* MMC/SD/SDIO common */
2764
2765static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 1652static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
2766 .rev_offs = 0x1fc, 1653 .rev_offs = 0x1fc,
2767 .sysc_offs = 0x10, 1654 .sysc_offs = 0x10,
@@ -2945,12 +1832,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
2945 * 'usb_host_hs' class 1832 * 'usb_host_hs' class
2946 * high-speed multi-port usb host controller 1833 * high-speed multi-port usb host controller
2947 */ 1834 */
2948static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2949 .master = &omap3xxx_usb_host_hs_hwmod,
2950 .slave = &omap3xxx_l3_main_hwmod,
2951 .clk = "core_l3_ick",
2952 .user = OCP_USER_MPU,
2953};
2954 1835
2955static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 1836static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
2956 .rev_offs = 0x0000, 1837 .rev_offs = 0x0000,
@@ -2969,34 +1850,6 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
2969 .sysc = &omap3xxx_usb_host_hs_sysc, 1850 .sysc = &omap3xxx_usb_host_hs_sysc,
2970}; 1851};
2971 1852
2972static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
2973 {
2974 .name = "uhh",
2975 .pa_start = 0x48064000,
2976 .pa_end = 0x480643ff,
2977 .flags = ADDR_TYPE_RT
2978 },
2979 {
2980 .name = "ohci",
2981 .pa_start = 0x48064400,
2982 .pa_end = 0x480647ff,
2983 },
2984 {
2985 .name = "ehci",
2986 .pa_start = 0x48064800,
2987 .pa_end = 0x48064cff,
2988 },
2989 {}
2990};
2991
2992static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2993 .master = &omap3xxx_l4_core_hwmod,
2994 .slave = &omap3xxx_usb_host_hs_hwmod,
2995 .clk = "usbhost_ick",
2996 .addr = omap3xxx_usb_host_hs_addrs,
2997 .user = OCP_USER_MPU | OCP_USER_SDMA,
2998};
2999
3000static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { 1853static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
3001 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, 1854 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
3002}; 1855};
@@ -3100,6 +1953,1084 @@ static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
3100 { .irq = -1 } 1953 { .irq = -1 }
3101}; 1954};
3102 1955
1956static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1957 .name = "usb_tll_hs",
1958 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1959 .clkdm_name = "l3_init_clkdm",
1960 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
1961 .main_clk = "usbtll_fck",
1962 .prcm = {
1963 .omap2 = {
1964 .module_offs = CORE_MOD,
1965 .prcm_reg_id = 3,
1966 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1967 .idlest_reg_id = 3,
1968 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1969 },
1970 },
1971};
1972
1973/*
1974 * interfaces
1975 */
1976
1977/* L3 -> L4_CORE interface */
1978static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1979 .master = &omap3xxx_l3_main_hwmod,
1980 .slave = &omap3xxx_l4_core_hwmod,
1981 .user = OCP_USER_MPU | OCP_USER_SDMA,
1982};
1983
1984/* L3 -> L4_PER interface */
1985static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1986 .master = &omap3xxx_l3_main_hwmod,
1987 .slave = &omap3xxx_l4_per_hwmod,
1988 .user = OCP_USER_MPU | OCP_USER_SDMA,
1989};
1990
1991static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
1992 {
1993 .pa_start = 0x68000000,
1994 .pa_end = 0x6800ffff,
1995 .flags = ADDR_TYPE_RT,
1996 },
1997 { }
1998};
1999
2000/* MPU -> L3 interface */
2001static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2002 .master = &omap3xxx_mpu_hwmod,
2003 .slave = &omap3xxx_l3_main_hwmod,
2004 .addr = omap3xxx_l3_main_addrs,
2005 .user = OCP_USER_MPU,
2006};
2007
2008/* DSS -> l3 */
2009static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2010 .master = &omap3430es1_dss_core_hwmod,
2011 .slave = &omap3xxx_l3_main_hwmod,
2012 .user = OCP_USER_MPU | OCP_USER_SDMA,
2013};
2014
2015static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2016 .master = &omap3xxx_dss_core_hwmod,
2017 .slave = &omap3xxx_l3_main_hwmod,
2018 .fw = {
2019 .omap2 = {
2020 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2021 .flags = OMAP_FIREWALL_L3,
2022 }
2023 },
2024 .user = OCP_USER_MPU | OCP_USER_SDMA,
2025};
2026
2027/* l3_core -> usbhsotg interface */
2028static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2029 .master = &omap3xxx_usbhsotg_hwmod,
2030 .slave = &omap3xxx_l3_main_hwmod,
2031 .clk = "core_l3_ick",
2032 .user = OCP_USER_MPU,
2033};
2034
2035/* l3_core -> am35xx_usbhsotg interface */
2036static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2037 .master = &am35xx_usbhsotg_hwmod,
2038 .slave = &omap3xxx_l3_main_hwmod,
2039 .clk = "core_l3_ick",
2040 .user = OCP_USER_MPU,
2041};
2042/* L4_CORE -> L4_WKUP interface */
2043static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2044 .master = &omap3xxx_l4_core_hwmod,
2045 .slave = &omap3xxx_l4_wkup_hwmod,
2046 .user = OCP_USER_MPU | OCP_USER_SDMA,
2047};
2048
2049/* L4 CORE -> MMC1 interface */
2050static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2051 .master = &omap3xxx_l4_core_hwmod,
2052 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2053 .clk = "mmchs1_ick",
2054 .addr = omap2430_mmc1_addr_space,
2055 .user = OCP_USER_MPU | OCP_USER_SDMA,
2056 .flags = OMAP_FIREWALL_L4
2057};
2058
2059static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2060 .master = &omap3xxx_l4_core_hwmod,
2061 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2062 .clk = "mmchs1_ick",
2063 .addr = omap2430_mmc1_addr_space,
2064 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065 .flags = OMAP_FIREWALL_L4
2066};
2067
2068/* L4 CORE -> MMC2 interface */
2069static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2070 .master = &omap3xxx_l4_core_hwmod,
2071 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2072 .clk = "mmchs2_ick",
2073 .addr = omap2430_mmc2_addr_space,
2074 .user = OCP_USER_MPU | OCP_USER_SDMA,
2075 .flags = OMAP_FIREWALL_L4
2076};
2077
2078static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2079 .master = &omap3xxx_l4_core_hwmod,
2080 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2081 .clk = "mmchs2_ick",
2082 .addr = omap2430_mmc2_addr_space,
2083 .user = OCP_USER_MPU | OCP_USER_SDMA,
2084 .flags = OMAP_FIREWALL_L4
2085};
2086
2087/* L4 CORE -> MMC3 interface */
2088static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2089 {
2090 .pa_start = 0x480ad000,
2091 .pa_end = 0x480ad1ff,
2092 .flags = ADDR_TYPE_RT,
2093 },
2094 { }
2095};
2096
2097static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2098 .master = &omap3xxx_l4_core_hwmod,
2099 .slave = &omap3xxx_mmc3_hwmod,
2100 .clk = "mmchs3_ick",
2101 .addr = omap3xxx_mmc3_addr_space,
2102 .user = OCP_USER_MPU | OCP_USER_SDMA,
2103 .flags = OMAP_FIREWALL_L4
2104};
2105
2106/* L4 CORE -> UART1 interface */
2107static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2108 {
2109 .pa_start = OMAP3_UART1_BASE,
2110 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2111 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2112 },
2113 { }
2114};
2115
2116static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2117 .master = &omap3xxx_l4_core_hwmod,
2118 .slave = &omap3xxx_uart1_hwmod,
2119 .clk = "uart1_ick",
2120 .addr = omap3xxx_uart1_addr_space,
2121 .user = OCP_USER_MPU | OCP_USER_SDMA,
2122};
2123
2124/* L4 CORE -> UART2 interface */
2125static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2126 {
2127 .pa_start = OMAP3_UART2_BASE,
2128 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2129 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2130 },
2131 { }
2132};
2133
2134static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2135 .master = &omap3xxx_l4_core_hwmod,
2136 .slave = &omap3xxx_uart2_hwmod,
2137 .clk = "uart2_ick",
2138 .addr = omap3xxx_uart2_addr_space,
2139 .user = OCP_USER_MPU | OCP_USER_SDMA,
2140};
2141
2142/* L4 PER -> UART3 interface */
2143static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2144 {
2145 .pa_start = OMAP3_UART3_BASE,
2146 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2147 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2148 },
2149 { }
2150};
2151
2152static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2153 .master = &omap3xxx_l4_per_hwmod,
2154 .slave = &omap3xxx_uart3_hwmod,
2155 .clk = "uart3_ick",
2156 .addr = omap3xxx_uart3_addr_space,
2157 .user = OCP_USER_MPU | OCP_USER_SDMA,
2158};
2159
2160/* L4 PER -> UART4 interface */
2161static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2162 {
2163 .pa_start = OMAP3_UART4_BASE,
2164 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2165 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2166 },
2167 { }
2168};
2169
2170static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2171 .master = &omap3xxx_l4_per_hwmod,
2172 .slave = &omap36xx_uart4_hwmod,
2173 .clk = "uart4_ick",
2174 .addr = omap36xx_uart4_addr_space,
2175 .user = OCP_USER_MPU | OCP_USER_SDMA,
2176};
2177
2178/* AM35xx: L4 CORE -> UART4 interface */
2179static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2180 {
2181 .pa_start = OMAP3_UART4_AM35XX_BASE,
2182 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2183 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2184 },
2185};
2186
2187static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2188 .master = &omap3xxx_l4_core_hwmod,
2189 .slave = &am35xx_uart4_hwmod,
2190 .clk = "uart4_ick",
2191 .addr = am35xx_uart4_addr_space,
2192 .user = OCP_USER_MPU | OCP_USER_SDMA,
2193};
2194
2195/* L4 CORE -> I2C1 interface */
2196static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2197 .master = &omap3xxx_l4_core_hwmod,
2198 .slave = &omap3xxx_i2c1_hwmod,
2199 .clk = "i2c1_ick",
2200 .addr = omap2_i2c1_addr_space,
2201 .fw = {
2202 .omap2 = {
2203 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2204 .l4_prot_group = 7,
2205 .flags = OMAP_FIREWALL_L4,
2206 }
2207 },
2208 .user = OCP_USER_MPU | OCP_USER_SDMA,
2209};
2210
2211/* L4 CORE -> I2C2 interface */
2212static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2213 .master = &omap3xxx_l4_core_hwmod,
2214 .slave = &omap3xxx_i2c2_hwmod,
2215 .clk = "i2c2_ick",
2216 .addr = omap2_i2c2_addr_space,
2217 .fw = {
2218 .omap2 = {
2219 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2220 .l4_prot_group = 7,
2221 .flags = OMAP_FIREWALL_L4,
2222 }
2223 },
2224 .user = OCP_USER_MPU | OCP_USER_SDMA,
2225};
2226
2227/* L4 CORE -> I2C3 interface */
2228static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2229 {
2230 .pa_start = 0x48060000,
2231 .pa_end = 0x48060000 + SZ_128 - 1,
2232 .flags = ADDR_TYPE_RT,
2233 },
2234 { }
2235};
2236
2237static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2238 .master = &omap3xxx_l4_core_hwmod,
2239 .slave = &omap3xxx_i2c3_hwmod,
2240 .clk = "i2c3_ick",
2241 .addr = omap3xxx_i2c3_addr_space,
2242 .fw = {
2243 .omap2 = {
2244 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2245 .l4_prot_group = 7,
2246 .flags = OMAP_FIREWALL_L4,
2247 }
2248 },
2249 .user = OCP_USER_MPU | OCP_USER_SDMA,
2250};
2251
2252/* L4 CORE -> SR1 interface */
2253static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2254 {
2255 .pa_start = OMAP34XX_SR1_BASE,
2256 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2257 .flags = ADDR_TYPE_RT,
2258 },
2259 { }
2260};
2261
2262static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2263 .master = &omap3xxx_l4_core_hwmod,
2264 .slave = &omap34xx_sr1_hwmod,
2265 .clk = "sr_l4_ick",
2266 .addr = omap3_sr1_addr_space,
2267 .user = OCP_USER_MPU,
2268};
2269
2270static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2271 .master = &omap3xxx_l4_core_hwmod,
2272 .slave = &omap36xx_sr1_hwmod,
2273 .clk = "sr_l4_ick",
2274 .addr = omap3_sr1_addr_space,
2275 .user = OCP_USER_MPU,
2276};
2277
2278/* L4 CORE -> SR1 interface */
2279static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2280 {
2281 .pa_start = OMAP34XX_SR2_BASE,
2282 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2283 .flags = ADDR_TYPE_RT,
2284 },
2285 { }
2286};
2287
2288static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2289 .master = &omap3xxx_l4_core_hwmod,
2290 .slave = &omap34xx_sr2_hwmod,
2291 .clk = "sr_l4_ick",
2292 .addr = omap3_sr2_addr_space,
2293 .user = OCP_USER_MPU,
2294};
2295
2296static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2297 .master = &omap3xxx_l4_core_hwmod,
2298 .slave = &omap36xx_sr2_hwmod,
2299 .clk = "sr_l4_ick",
2300 .addr = omap3_sr2_addr_space,
2301 .user = OCP_USER_MPU,
2302};
2303
2304static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2305 {
2306 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2307 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2308 .flags = ADDR_TYPE_RT
2309 },
2310 { }
2311};
2312
2313/* l4_core -> usbhsotg */
2314static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2315 .master = &omap3xxx_l4_core_hwmod,
2316 .slave = &omap3xxx_usbhsotg_hwmod,
2317 .clk = "l4_ick",
2318 .addr = omap3xxx_usbhsotg_addrs,
2319 .user = OCP_USER_MPU,
2320};
2321
2322static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2323 {
2324 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2325 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2326 .flags = ADDR_TYPE_RT
2327 },
2328 { }
2329};
2330
2331/* l4_core -> usbhsotg */
2332static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2333 .master = &omap3xxx_l4_core_hwmod,
2334 .slave = &am35xx_usbhsotg_hwmod,
2335 .clk = "l4_ick",
2336 .addr = am35xx_usbhsotg_addrs,
2337 .user = OCP_USER_MPU,
2338};
2339
2340/* L4_WKUP -> L4_SEC interface */
2341static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2342 .master = &omap3xxx_l4_wkup_hwmod,
2343 .slave = &omap3xxx_l4_sec_hwmod,
2344 .user = OCP_USER_MPU | OCP_USER_SDMA,
2345};
2346
2347/* IVA2 <- L3 interface */
2348static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2349 .master = &omap3xxx_l3_main_hwmod,
2350 .slave = &omap3xxx_iva_hwmod,
2351 .clk = "iva2_ck",
2352 .user = OCP_USER_MPU | OCP_USER_SDMA,
2353};
2354
2355static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2356 {
2357 .pa_start = 0x48318000,
2358 .pa_end = 0x48318000 + SZ_1K - 1,
2359 .flags = ADDR_TYPE_RT
2360 },
2361 { }
2362};
2363
2364/* l4_wkup -> timer1 */
2365static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2366 .master = &omap3xxx_l4_wkup_hwmod,
2367 .slave = &omap3xxx_timer1_hwmod,
2368 .clk = "gpt1_ick",
2369 .addr = omap3xxx_timer1_addrs,
2370 .user = OCP_USER_MPU | OCP_USER_SDMA,
2371};
2372
2373static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2374 {
2375 .pa_start = 0x49032000,
2376 .pa_end = 0x49032000 + SZ_1K - 1,
2377 .flags = ADDR_TYPE_RT
2378 },
2379 { }
2380};
2381
2382/* l4_per -> timer2 */
2383static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2384 .master = &omap3xxx_l4_per_hwmod,
2385 .slave = &omap3xxx_timer2_hwmod,
2386 .clk = "gpt2_ick",
2387 .addr = omap3xxx_timer2_addrs,
2388 .user = OCP_USER_MPU | OCP_USER_SDMA,
2389};
2390
2391static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2392 {
2393 .pa_start = 0x49034000,
2394 .pa_end = 0x49034000 + SZ_1K - 1,
2395 .flags = ADDR_TYPE_RT
2396 },
2397 { }
2398};
2399
2400/* l4_per -> timer3 */
2401static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2402 .master = &omap3xxx_l4_per_hwmod,
2403 .slave = &omap3xxx_timer3_hwmod,
2404 .clk = "gpt3_ick",
2405 .addr = omap3xxx_timer3_addrs,
2406 .user = OCP_USER_MPU | OCP_USER_SDMA,
2407};
2408
2409static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2410 {
2411 .pa_start = 0x49036000,
2412 .pa_end = 0x49036000 + SZ_1K - 1,
2413 .flags = ADDR_TYPE_RT
2414 },
2415 { }
2416};
2417
2418/* l4_per -> timer4 */
2419static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2420 .master = &omap3xxx_l4_per_hwmod,
2421 .slave = &omap3xxx_timer4_hwmod,
2422 .clk = "gpt4_ick",
2423 .addr = omap3xxx_timer4_addrs,
2424 .user = OCP_USER_MPU | OCP_USER_SDMA,
2425};
2426
2427static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2428 {
2429 .pa_start = 0x49038000,
2430 .pa_end = 0x49038000 + SZ_1K - 1,
2431 .flags = ADDR_TYPE_RT
2432 },
2433 { }
2434};
2435
2436/* l4_per -> timer5 */
2437static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2438 .master = &omap3xxx_l4_per_hwmod,
2439 .slave = &omap3xxx_timer5_hwmod,
2440 .clk = "gpt5_ick",
2441 .addr = omap3xxx_timer5_addrs,
2442 .user = OCP_USER_MPU | OCP_USER_SDMA,
2443};
2444
2445static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2446 {
2447 .pa_start = 0x4903A000,
2448 .pa_end = 0x4903A000 + SZ_1K - 1,
2449 .flags = ADDR_TYPE_RT
2450 },
2451 { }
2452};
2453
2454/* l4_per -> timer6 */
2455static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2456 .master = &omap3xxx_l4_per_hwmod,
2457 .slave = &omap3xxx_timer6_hwmod,
2458 .clk = "gpt6_ick",
2459 .addr = omap3xxx_timer6_addrs,
2460 .user = OCP_USER_MPU | OCP_USER_SDMA,
2461};
2462
2463static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2464 {
2465 .pa_start = 0x4903C000,
2466 .pa_end = 0x4903C000 + SZ_1K - 1,
2467 .flags = ADDR_TYPE_RT
2468 },
2469 { }
2470};
2471
2472/* l4_per -> timer7 */
2473static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2474 .master = &omap3xxx_l4_per_hwmod,
2475 .slave = &omap3xxx_timer7_hwmod,
2476 .clk = "gpt7_ick",
2477 .addr = omap3xxx_timer7_addrs,
2478 .user = OCP_USER_MPU | OCP_USER_SDMA,
2479};
2480
2481static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2482 {
2483 .pa_start = 0x4903E000,
2484 .pa_end = 0x4903E000 + SZ_1K - 1,
2485 .flags = ADDR_TYPE_RT
2486 },
2487 { }
2488};
2489
2490/* l4_per -> timer8 */
2491static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2492 .master = &omap3xxx_l4_per_hwmod,
2493 .slave = &omap3xxx_timer8_hwmod,
2494 .clk = "gpt8_ick",
2495 .addr = omap3xxx_timer8_addrs,
2496 .user = OCP_USER_MPU | OCP_USER_SDMA,
2497};
2498
2499static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2500 {
2501 .pa_start = 0x49040000,
2502 .pa_end = 0x49040000 + SZ_1K - 1,
2503 .flags = ADDR_TYPE_RT
2504 },
2505 { }
2506};
2507
2508/* l4_per -> timer9 */
2509static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2510 .master = &omap3xxx_l4_per_hwmod,
2511 .slave = &omap3xxx_timer9_hwmod,
2512 .clk = "gpt9_ick",
2513 .addr = omap3xxx_timer9_addrs,
2514 .user = OCP_USER_MPU | OCP_USER_SDMA,
2515};
2516
2517/* l4_core -> timer10 */
2518static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2519 .master = &omap3xxx_l4_core_hwmod,
2520 .slave = &omap3xxx_timer10_hwmod,
2521 .clk = "gpt10_ick",
2522 .addr = omap2_timer10_addrs,
2523 .user = OCP_USER_MPU | OCP_USER_SDMA,
2524};
2525
2526/* l4_core -> timer11 */
2527static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2528 .master = &omap3xxx_l4_core_hwmod,
2529 .slave = &omap3xxx_timer11_hwmod,
2530 .clk = "gpt11_ick",
2531 .addr = omap2_timer11_addrs,
2532 .user = OCP_USER_MPU | OCP_USER_SDMA,
2533};
2534
2535static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2536 {
2537 .pa_start = 0x48304000,
2538 .pa_end = 0x48304000 + SZ_1K - 1,
2539 .flags = ADDR_TYPE_RT
2540 },
2541 { }
2542};
2543
2544/* l4_core -> timer12 */
2545static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2546 .master = &omap3xxx_l4_sec_hwmod,
2547 .slave = &omap3xxx_timer12_hwmod,
2548 .clk = "gpt12_ick",
2549 .addr = omap3xxx_timer12_addrs,
2550 .user = OCP_USER_MPU | OCP_USER_SDMA,
2551};
2552
2553/* l4_wkup -> wd_timer2 */
2554static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2555 {
2556 .pa_start = 0x48314000,
2557 .pa_end = 0x4831407f,
2558 .flags = ADDR_TYPE_RT
2559 },
2560 { }
2561};
2562
2563static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2564 .master = &omap3xxx_l4_wkup_hwmod,
2565 .slave = &omap3xxx_wd_timer2_hwmod,
2566 .clk = "wdt2_ick",
2567 .addr = omap3xxx_wd_timer2_addrs,
2568 .user = OCP_USER_MPU | OCP_USER_SDMA,
2569};
2570
2571/* l4_core -> dss */
2572static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2573 .master = &omap3xxx_l4_core_hwmod,
2574 .slave = &omap3430es1_dss_core_hwmod,
2575 .clk = "dss_ick",
2576 .addr = omap2_dss_addrs,
2577 .fw = {
2578 .omap2 = {
2579 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2580 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2581 .flags = OMAP_FIREWALL_L4,
2582 }
2583 },
2584 .user = OCP_USER_MPU | OCP_USER_SDMA,
2585};
2586
2587static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2588 .master = &omap3xxx_l4_core_hwmod,
2589 .slave = &omap3xxx_dss_core_hwmod,
2590 .clk = "dss_ick",
2591 .addr = omap2_dss_addrs,
2592 .fw = {
2593 .omap2 = {
2594 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2595 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2596 .flags = OMAP_FIREWALL_L4,
2597 }
2598 },
2599 .user = OCP_USER_MPU | OCP_USER_SDMA,
2600};
2601
2602/* l4_core -> dss_dispc */
2603static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2604 .master = &omap3xxx_l4_core_hwmod,
2605 .slave = &omap3xxx_dss_dispc_hwmod,
2606 .clk = "dss_ick",
2607 .addr = omap2_dss_dispc_addrs,
2608 .fw = {
2609 .omap2 = {
2610 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2611 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2612 .flags = OMAP_FIREWALL_L4,
2613 }
2614 },
2615 .user = OCP_USER_MPU | OCP_USER_SDMA,
2616};
2617
2618static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2619 {
2620 .pa_start = 0x4804FC00,
2621 .pa_end = 0x4804FFFF,
2622 .flags = ADDR_TYPE_RT
2623 },
2624 { }
2625};
2626
2627/* l4_core -> dss_dsi1 */
2628static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2629 .master = &omap3xxx_l4_core_hwmod,
2630 .slave = &omap3xxx_dss_dsi1_hwmod,
2631 .clk = "dss_ick",
2632 .addr = omap3xxx_dss_dsi1_addrs,
2633 .fw = {
2634 .omap2 = {
2635 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2636 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2637 .flags = OMAP_FIREWALL_L4,
2638 }
2639 },
2640 .user = OCP_USER_MPU | OCP_USER_SDMA,
2641};
2642
2643/* l4_core -> dss_rfbi */
2644static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2645 .master = &omap3xxx_l4_core_hwmod,
2646 .slave = &omap3xxx_dss_rfbi_hwmod,
2647 .clk = "dss_ick",
2648 .addr = omap2_dss_rfbi_addrs,
2649 .fw = {
2650 .omap2 = {
2651 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2652 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2653 .flags = OMAP_FIREWALL_L4,
2654 }
2655 },
2656 .user = OCP_USER_MPU | OCP_USER_SDMA,
2657};
2658
2659/* l4_core -> dss_venc */
2660static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2661 .master = &omap3xxx_l4_core_hwmod,
2662 .slave = &omap3xxx_dss_venc_hwmod,
2663 .clk = "dss_ick",
2664 .addr = omap2_dss_venc_addrs,
2665 .fw = {
2666 .omap2 = {
2667 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2668 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2669 .flags = OMAP_FIREWALL_L4,
2670 }
2671 },
2672 .flags = OCPIF_SWSUP_IDLE,
2673 .user = OCP_USER_MPU | OCP_USER_SDMA,
2674};
2675
2676/* l4_wkup -> gpio1 */
2677static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2678 {
2679 .pa_start = 0x48310000,
2680 .pa_end = 0x483101ff,
2681 .flags = ADDR_TYPE_RT
2682 },
2683 { }
2684};
2685
2686static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2687 .master = &omap3xxx_l4_wkup_hwmod,
2688 .slave = &omap3xxx_gpio1_hwmod,
2689 .addr = omap3xxx_gpio1_addrs,
2690 .user = OCP_USER_MPU | OCP_USER_SDMA,
2691};
2692
2693/* l4_per -> gpio2 */
2694static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2695 {
2696 .pa_start = 0x49050000,
2697 .pa_end = 0x490501ff,
2698 .flags = ADDR_TYPE_RT
2699 },
2700 { }
2701};
2702
2703static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2704 .master = &omap3xxx_l4_per_hwmod,
2705 .slave = &omap3xxx_gpio2_hwmod,
2706 .addr = omap3xxx_gpio2_addrs,
2707 .user = OCP_USER_MPU | OCP_USER_SDMA,
2708};
2709
2710/* l4_per -> gpio3 */
2711static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2712 {
2713 .pa_start = 0x49052000,
2714 .pa_end = 0x490521ff,
2715 .flags = ADDR_TYPE_RT
2716 },
2717 { }
2718};
2719
2720static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2721 .master = &omap3xxx_l4_per_hwmod,
2722 .slave = &omap3xxx_gpio3_hwmod,
2723 .addr = omap3xxx_gpio3_addrs,
2724 .user = OCP_USER_MPU | OCP_USER_SDMA,
2725};
2726
2727/* l4_per -> gpio4 */
2728static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2729 {
2730 .pa_start = 0x49054000,
2731 .pa_end = 0x490541ff,
2732 .flags = ADDR_TYPE_RT
2733 },
2734 { }
2735};
2736
2737static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2738 .master = &omap3xxx_l4_per_hwmod,
2739 .slave = &omap3xxx_gpio4_hwmod,
2740 .addr = omap3xxx_gpio4_addrs,
2741 .user = OCP_USER_MPU | OCP_USER_SDMA,
2742};
2743
2744/* l4_per -> gpio5 */
2745static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2746 {
2747 .pa_start = 0x49056000,
2748 .pa_end = 0x490561ff,
2749 .flags = ADDR_TYPE_RT
2750 },
2751 { }
2752};
2753
2754static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2755 .master = &omap3xxx_l4_per_hwmod,
2756 .slave = &omap3xxx_gpio5_hwmod,
2757 .addr = omap3xxx_gpio5_addrs,
2758 .user = OCP_USER_MPU | OCP_USER_SDMA,
2759};
2760
2761/* l4_per -> gpio6 */
2762static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2763 {
2764 .pa_start = 0x49058000,
2765 .pa_end = 0x490581ff,
2766 .flags = ADDR_TYPE_RT
2767 },
2768 { }
2769};
2770
2771static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2772 .master = &omap3xxx_l4_per_hwmod,
2773 .slave = &omap3xxx_gpio6_hwmod,
2774 .addr = omap3xxx_gpio6_addrs,
2775 .user = OCP_USER_MPU | OCP_USER_SDMA,
2776};
2777
2778/* dma_system -> L3 */
2779static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2780 .master = &omap3xxx_dma_system_hwmod,
2781 .slave = &omap3xxx_l3_main_hwmod,
2782 .clk = "core_l3_ick",
2783 .user = OCP_USER_MPU | OCP_USER_SDMA,
2784};
2785
2786static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2787 {
2788 .pa_start = 0x48056000,
2789 .pa_end = 0x48056fff,
2790 .flags = ADDR_TYPE_RT
2791 },
2792 { }
2793};
2794
2795/* l4_cfg -> dma_system */
2796static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2797 .master = &omap3xxx_l4_core_hwmod,
2798 .slave = &omap3xxx_dma_system_hwmod,
2799 .clk = "core_l4_ick",
2800 .addr = omap3xxx_dma_system_addrs,
2801 .user = OCP_USER_MPU | OCP_USER_SDMA,
2802};
2803
2804static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2805 {
2806 .name = "mpu",
2807 .pa_start = 0x48074000,
2808 .pa_end = 0x480740ff,
2809 .flags = ADDR_TYPE_RT
2810 },
2811 { }
2812};
2813
2814/* l4_core -> mcbsp1 */
2815static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2816 .master = &omap3xxx_l4_core_hwmod,
2817 .slave = &omap3xxx_mcbsp1_hwmod,
2818 .clk = "mcbsp1_ick",
2819 .addr = omap3xxx_mcbsp1_addrs,
2820 .user = OCP_USER_MPU | OCP_USER_SDMA,
2821};
2822
2823static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2824 {
2825 .name = "mpu",
2826 .pa_start = 0x49022000,
2827 .pa_end = 0x490220ff,
2828 .flags = ADDR_TYPE_RT
2829 },
2830 { }
2831};
2832
2833/* l4_per -> mcbsp2 */
2834static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2835 .master = &omap3xxx_l4_per_hwmod,
2836 .slave = &omap3xxx_mcbsp2_hwmod,
2837 .clk = "mcbsp2_ick",
2838 .addr = omap3xxx_mcbsp2_addrs,
2839 .user = OCP_USER_MPU | OCP_USER_SDMA,
2840};
2841
2842static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2843 {
2844 .name = "mpu",
2845 .pa_start = 0x49024000,
2846 .pa_end = 0x490240ff,
2847 .flags = ADDR_TYPE_RT
2848 },
2849 { }
2850};
2851
2852/* l4_per -> mcbsp3 */
2853static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2854 .master = &omap3xxx_l4_per_hwmod,
2855 .slave = &omap3xxx_mcbsp3_hwmod,
2856 .clk = "mcbsp3_ick",
2857 .addr = omap3xxx_mcbsp3_addrs,
2858 .user = OCP_USER_MPU | OCP_USER_SDMA,
2859};
2860
2861static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2862 {
2863 .name = "mpu",
2864 .pa_start = 0x49026000,
2865 .pa_end = 0x490260ff,
2866 .flags = ADDR_TYPE_RT
2867 },
2868 { }
2869};
2870
2871/* l4_per -> mcbsp4 */
2872static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2873 .master = &omap3xxx_l4_per_hwmod,
2874 .slave = &omap3xxx_mcbsp4_hwmod,
2875 .clk = "mcbsp4_ick",
2876 .addr = omap3xxx_mcbsp4_addrs,
2877 .user = OCP_USER_MPU | OCP_USER_SDMA,
2878};
2879
2880static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2881 {
2882 .name = "mpu",
2883 .pa_start = 0x48096000,
2884 .pa_end = 0x480960ff,
2885 .flags = ADDR_TYPE_RT
2886 },
2887 { }
2888};
2889
2890/* l4_core -> mcbsp5 */
2891static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2892 .master = &omap3xxx_l4_core_hwmod,
2893 .slave = &omap3xxx_mcbsp5_hwmod,
2894 .clk = "mcbsp5_ick",
2895 .addr = omap3xxx_mcbsp5_addrs,
2896 .user = OCP_USER_MPU | OCP_USER_SDMA,
2897};
2898
2899static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2900 {
2901 .name = "sidetone",
2902 .pa_start = 0x49028000,
2903 .pa_end = 0x490280ff,
2904 .flags = ADDR_TYPE_RT
2905 },
2906 { }
2907};
2908
2909/* l4_per -> mcbsp2_sidetone */
2910static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2911 .master = &omap3xxx_l4_per_hwmod,
2912 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2913 .clk = "mcbsp2_ick",
2914 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2915 .user = OCP_USER_MPU,
2916};
2917
2918static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2919 {
2920 .name = "sidetone",
2921 .pa_start = 0x4902A000,
2922 .pa_end = 0x4902A0ff,
2923 .flags = ADDR_TYPE_RT
2924 },
2925 { }
2926};
2927
2928/* l4_per -> mcbsp3_sidetone */
2929static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2930 .master = &omap3xxx_l4_per_hwmod,
2931 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2932 .clk = "mcbsp3_ick",
2933 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2934 .user = OCP_USER_MPU,
2935};
2936
2937static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2938 {
2939 .pa_start = 0x48094000,
2940 .pa_end = 0x480941ff,
2941 .flags = ADDR_TYPE_RT,
2942 },
2943 { }
2944};
2945
2946/* l4_core -> mailbox */
2947static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2948 .master = &omap3xxx_l4_core_hwmod,
2949 .slave = &omap3xxx_mailbox_hwmod,
2950 .addr = omap3xxx_mailbox_addrs,
2951 .user = OCP_USER_MPU | OCP_USER_SDMA,
2952};
2953
2954/* l4 core -> mcspi1 interface */
2955static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2956 .master = &omap3xxx_l4_core_hwmod,
2957 .slave = &omap34xx_mcspi1,
2958 .clk = "mcspi1_ick",
2959 .addr = omap2_mcspi1_addr_space,
2960 .user = OCP_USER_MPU | OCP_USER_SDMA,
2961};
2962
2963/* l4 core -> mcspi2 interface */
2964static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2965 .master = &omap3xxx_l4_core_hwmod,
2966 .slave = &omap34xx_mcspi2,
2967 .clk = "mcspi2_ick",
2968 .addr = omap2_mcspi2_addr_space,
2969 .user = OCP_USER_MPU | OCP_USER_SDMA,
2970};
2971
2972/* l4 core -> mcspi3 interface */
2973static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2974 .master = &omap3xxx_l4_core_hwmod,
2975 .slave = &omap34xx_mcspi3,
2976 .clk = "mcspi3_ick",
2977 .addr = omap2430_mcspi3_addr_space,
2978 .user = OCP_USER_MPU | OCP_USER_SDMA,
2979};
2980
2981/* l4 core -> mcspi4 interface */
2982static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2983 {
2984 .pa_start = 0x480ba000,
2985 .pa_end = 0x480ba0ff,
2986 .flags = ADDR_TYPE_RT,
2987 },
2988 { }
2989};
2990
2991static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2992 .master = &omap3xxx_l4_core_hwmod,
2993 .slave = &omap34xx_mcspi4,
2994 .clk = "mcspi4_ick",
2995 .addr = omap34xx_mcspi4_addr_space,
2996 .user = OCP_USER_MPU | OCP_USER_SDMA,
2997};
2998
2999static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3000 .master = &omap3xxx_usb_host_hs_hwmod,
3001 .slave = &omap3xxx_l3_main_hwmod,
3002 .clk = "core_l3_ick",
3003 .user = OCP_USER_MPU,
3004};
3005
3006static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3007 {
3008 .name = "uhh",
3009 .pa_start = 0x48064000,
3010 .pa_end = 0x480643ff,
3011 .flags = ADDR_TYPE_RT
3012 },
3013 {
3014 .name = "ohci",
3015 .pa_start = 0x48064400,
3016 .pa_end = 0x480647ff,
3017 },
3018 {
3019 .name = "ehci",
3020 .pa_start = 0x48064800,
3021 .pa_end = 0x48064cff,
3022 },
3023 {}
3024};
3025
3026static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3027 .master = &omap3xxx_l4_core_hwmod,
3028 .slave = &omap3xxx_usb_host_hs_hwmod,
3029 .clk = "usbhost_ick",
3030 .addr = omap3xxx_usb_host_hs_addrs,
3031 .user = OCP_USER_MPU | OCP_USER_SDMA,
3032};
3033
3103static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { 3034static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3104 { 3035 {
3105 .name = "tll", 3036 .name = "tll",
@@ -3118,23 +3049,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3118 .user = OCP_USER_MPU | OCP_USER_SDMA, 3049 .user = OCP_USER_MPU | OCP_USER_SDMA,
3119}; 3050};
3120 3051
3121static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
3122 .name = "usb_tll_hs",
3123 .class = &omap3xxx_usb_tll_hs_hwmod_class,
3124 .clkdm_name = "l3_init_clkdm",
3125 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
3126 .main_clk = "usbtll_fck",
3127 .prcm = {
3128 .omap2 = {
3129 .module_offs = CORE_MOD,
3130 .prcm_reg_id = 3,
3131 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3132 .idlest_reg_id = 3,
3133 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
3134 },
3135 },
3136};
3137
3138static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { 3052static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3139 &omap3xxx_l3_main__l4_core, 3053 &omap3xxx_l3_main__l4_core,
3140 &omap3xxx_l3_main__l4_per, 3054 &omap3xxx_l3_main__l4_per,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 16:37:28 -0500