Merge tag 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

New feature development

This adds support for new features, and contains stuff from most
platforms. A number of these patches could have fit into other
branches, too, but were small enough not to cause too much
confusion here.

* tag 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
  mfd/db8500-prcmu: remove support for early silicon revisions
  ARM: ux500: fix the smp_twd clock calculation
  ARM: ux500: remove support for early silicon revisions
  ARM: ux500: update register files
  ARM: ux500: register DB5500 PMU dynamically
  ARM: ux500: update ASIC detection for U5500
  ARM: ux500: support DB8520
  ARM: picoxcell: implement watchdog restart
  ARM: OMAP3+: hwmod data: Add the default clockactivity for I2C
  ARM: OMAP3: hwmod data: disable multiblock reads on MMC1/2 on OMAP34xx/35xx <= ES2.1
  ARM: OMAP: USB: EHCI and OHCI hwmod structures for OMAP4
  ARM: OMAP: USB: EHCI and OHCI hwmod structures for OMAP3
  ARM: OMAP: hwmod data: Add support for AM35xx UART4/ttyO3
  ARM: Orion: Remove address map info from all platform data structures
  ARM: Orion: Get address map from plat-orion instead of via platform_data
  ARM: Orion: mbus_dram_info consolidation
  ARM: Orion: Consolidate the address map setup
  ARM: Kirkwood: Add configuration for MPP12 as GPIO
  ARM: Kirkwood: Recognize A1 revision of 6282 chip
  ARM: ux500: update the MOP500 GPIO assignments
  ...

5 files changed, 30 insertions, 100 deletions

diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 311d5b0e9bc7..62b53d710efd 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -12,12 +12,12 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*
  * Generic Address Decode Windows bit settings
  */
-#define TARGET_DDR              0
 #define TARGET_DEV_BUS          1
 #define TARGET_PCIE0            4
 #define TARGET_PCIE1            8
@@ -32,23 +32,10 @@
 #define ATTR_PCIE_MEM(l)        (0xf8 & ~(0x10 << (l)))
 
 /*
- * Helpers to get DDR bank info
- */
-#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
-#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
-
-/*
  * CPU Address Decode Windows registers
  */
 #define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
 #define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
-#define WIN_CTRL_OFF            0x0000
-#define WIN_BASE_OFF            0x0004
-#define WIN_REMAP_LO_OFF        0x0008
-#define WIN_REMAP_HI_OFF        0x000c
-
-
-struct mbus_dram_target_info mv78xx0_mbus_dram_info;
 
 static void __init __iomem *win_cfg_base(int win)
 {
@@ -63,94 +50,43 @@ static void __init __iomem *win_cfg_base(int win)
         return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
 }
 
-static int __init cpu_win_can_remap(int win)
-{
-        if (win < 8)
-                return 1;
-
-        return 0;
-}
-
-static void __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        void __iomem *addr = win_cfg_base(win);
-        u32 ctrl;
-
-        base &= 0xffff0000;
-        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
-
-        writel(base, addr + WIN_BASE_OFF);
-        writel(ctrl, addr + WIN_CTRL_OFF);
-        if (cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-
-                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
-                writel(0, addr + WIN_REMAP_HI_OFF);
-        }
-}
+/*
+ * Description of the windows needed by the platform code
+ */
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 14,
+        .remappable_wins = 8,
+        .win_cfg_base = win_cfg_base,
+};
 
 void __init mv78xx0_setup_cpu_mbus(void)
 {
-        void __iomem *addr;
-        int i;
-        int cs;
-
         /*
-         * First, disable and clear windows.
+         * Disable, clear and configure windows.
          */
-        for (i = 0; i < 14; i++) {
-                addr = win_cfg_base(i);
-
-                writel(0, addr + WIN_BASE_OFF);
-                writel(0, addr + WIN_CTRL_OFF);
-                if (cpu_win_can_remap(i)) {
-                        writel(0, addr + WIN_REMAP_LO_OFF);
-                        writel(0, addr + WIN_REMAP_HI_OFF);
-                }
-        }
+        orion_config_wins(&addr_map_cfg, NULL);
 
         /*
          * Setup MBUS dram target info.
          */
-        mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-
         if (mv78xx0_core_index() == 0)
-                addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
+                orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                            DDR_WINDOW_CPU0_BASE);
         else
-                addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
-
-        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
-
-                /*
-                 * Chip select enabled?
-                 */
-                if (size & 1) {
-                        struct mbus_dram_window *w;
-
-                        w = &mv78xx0_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xffff0000;
-                        w->size = (size | 0x0000ffff) + 1;
-                }
-        }
-        mv78xx0_mbus_dram_info.num_cs = cs;
+                orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                            DDR_WINDOW_CPU1_BASE);
 }
 
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
                                       int maj, int min)
 {
-        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
-                      ATTR_PCIE_IO(min), -1);
+        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
+                            TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
 }
 
 void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
                                        int maj, int min)
 {
-        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
-                      ATTR_PCIE_MEM(min), -1);
+        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
+                            TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
 }
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 5b9632b01169..0cdd41004ad0 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -12,7 +12,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
-#include <linux/mbus.h>
 #include <linux/ata_platform.h>
 #include <linux/ethtool.h>
 #include <asm/mach/map.h>
@@ -23,6 +22,7 @@
 #include <plat/orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 static int get_tclk(void);
@@ -169,8 +169,7 @@ void __init mv78xx0_map_io(void)
  ****************************************************************************/
 void __init mv78xx0_ehci0_init(void)
 {
-        orion_ehci_init(&mv78xx0_mbus_dram_info,
-                        USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
+        orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
 }
 
 
@@ -179,8 +178,7 @@ void __init mv78xx0_ehci0_init(void)
  ****************************************************************************/
 void __init mv78xx0_ehci1_init(void)
 {
-        orion_ehci_1_init(&mv78xx0_mbus_dram_info,
-                          USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
+        orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
 }
 
 
@@ -189,8 +187,7 @@ void __init mv78xx0_ehci1_init(void)
  ****************************************************************************/
 void __init mv78xx0_ehci2_init(void)
 {
-        orion_ehci_2_init(&mv78xx0_mbus_dram_info,
-                          USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
+        orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
 }
 
 
@@ -199,7 +196,7 @@ void __init mv78xx0_ehci2_init(void)
  ****************************************************************************/
 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge00_init(eth_data,
                         GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
                         IRQ_MV78XX0_GE_ERR, get_tclk());
 }
@@ -210,7 +207,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
  ****************************************************************************/
 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge01_init(eth_data,
                         GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
                         NO_IRQ, get_tclk());
 }
@@ -234,7 +231,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
                 eth_data->duplex = DUPLEX_FULL;
         }
 
-        orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge10_init(eth_data,
                         GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
                         NO_IRQ, get_tclk());
 }
@@ -258,7 +255,7 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
                 eth_data->duplex = DUPLEX_FULL;
         }
 
-        orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge11_init(eth_data,
                         GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
                         NO_IRQ, get_tclk());
 }
@@ -277,8 +274,7 @@ void __init mv78xx0_i2c_init(void)
  ****************************************************************************/
 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
-                        SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
+        orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
 }
 
 
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 07d5f8f6be7d..507c767d49e0 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -23,7 +23,6 @@ void mv78xx0_init(void);
 void mv78xx0_init_early(void);
 void mv78xx0_init_irq(void);
 
-extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
 void mv78xx0_setup_cpu_mbus(void);
 void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
                                int maj, int min);
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index cf4e494d44bf..df50342179e2 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -10,7 +10,6 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mbus.h>
 #include <linux/io.h>
 #include <plat/mpp.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index c51af1cac300..12fcb108b0e1 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -10,11 +10,11 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
-#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 struct pcie_port {
@@ -153,7 +153,7 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
          * Generic PCIe unit setup.
          */
         orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
-        orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info);
+        orion_pcie_setup(pp->base);
 
         sys->resource[0] = &pp->res[0];
         sys->resource[1] = &pp->res[1];