diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-09-27 15:07:26 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-01-27 09:18:09 -0500 |
commit | 208d7baf8085ed639ec896274f1679d4718f2ff3 (patch) | |
tree | ad5ec8c11c35d27f9beca7e602e3ccb921cd9d63 /arch/arm/mach-imx | |
parent | d8ec26d7f8287f5788a494f56e8814210f0e64be (diff) |
ARM: imx: initial SolidRun HummingBoard support
Add support for the SolidRun HummingBoard. This commit adds support for
the following interfaces on this board:
- Consumer Ir receiver
- S/PDIF output
- Both USB interfaces
- Gigabit Ethernet using AR8035
- UART port
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r-- | arch/arm/mach-imx/mach-imx6q.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index d0cfb225ec9a..cb6fa3d61243 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c | |||
@@ -103,6 +103,39 @@ static int ar8031_phy_fixup(struct phy_device *dev) | |||
103 | 103 | ||
104 | #define PHY_ID_AR8031 0x004dd074 | 104 | #define PHY_ID_AR8031 0x004dd074 |
105 | 105 | ||
106 | static int ar8035_phy_fixup(struct phy_device *dev) | ||
107 | { | ||
108 | u16 val; | ||
109 | |||
110 | /* Ar803x phy SmartEEE feature cause link status generates glitch, | ||
111 | * which cause ethernet link down/up issue, so disable SmartEEE | ||
112 | */ | ||
113 | phy_write(dev, 0xd, 0x3); | ||
114 | phy_write(dev, 0xe, 0x805d); | ||
115 | phy_write(dev, 0xd, 0x4003); | ||
116 | |||
117 | val = phy_read(dev, 0xe); | ||
118 | phy_write(dev, 0xe, val & ~(1 << 8)); | ||
119 | |||
120 | /* | ||
121 | * Enable 125MHz clock from CLK_25M on the AR8031. This | ||
122 | * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad. | ||
123 | * Also, introduce a tx clock delay. | ||
124 | * | ||
125 | * This is the same as is the AR8031 fixup. | ||
126 | */ | ||
127 | ar8031_phy_fixup(dev); | ||
128 | |||
129 | /*check phy power*/ | ||
130 | val = phy_read(dev, 0x0); | ||
131 | if (val & BMCR_PDOWN) | ||
132 | phy_write(dev, 0x0, val & ~BMCR_PDOWN); | ||
133 | |||
134 | return 0; | ||
135 | } | ||
136 | |||
137 | #define PHY_ID_AR8035 0x004dd072 | ||
138 | |||
106 | static void __init imx6q_enet_phy_init(void) | 139 | static void __init imx6q_enet_phy_init(void) |
107 | { | 140 | { |
108 | if (IS_BUILTIN(CONFIG_PHYLIB)) { | 141 | if (IS_BUILTIN(CONFIG_PHYLIB)) { |
@@ -112,6 +145,8 @@ static void __init imx6q_enet_phy_init(void) | |||
112 | ksz9031rn_phy_fixup); | 145 | ksz9031rn_phy_fixup); |
113 | phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, | 146 | phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, |
114 | ar8031_phy_fixup); | 147 | ar8031_phy_fixup); |
148 | phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef, | ||
149 | ar8035_phy_fixup); | ||
115 | } | 150 | } |
116 | } | 151 | } |
117 | 152 | ||