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authorStefan Agner <stefan@agner.ch>2014-07-29 10:20:28 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-09-15 22:06:44 -0400
commit3b18dd7a86f925951c8543339f8137a80fa40891 (patch)
tree3d965ec2c8d99298aeca339ec5a12f4376ecc4f9 /arch/arm/mach-imx/clk-vf610.c
parent24980dc810f2c41929a50277946737e25ab3c0cd (diff)
ARM: imx: clk-vf610: introduce clks_init_on
At the end of the boot process, the clock framework might disable required main PLL's. So far, this was no issue since drivers requested clocks, which are descended of the main PLL's (e.g. pll1_pfd1, which provides the system clock). To archive the full 500MHz system clock, DDR clock need to be a descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The bootloader sets up the clocks accordingly before making use of DDR at all. However, in Linux, there is no driver using PLL2, which lead to PLL2 being disabled by the clock framework. With this patch, we make sure that the main system clock and the DDR clock are initially enabled and are kept enabled. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/clk-vf610.c')
-rw-r--r--arch/arm/mach-imx/clk-vf610.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index f60d6d569ce3..a41ed73219da 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -98,9 +98,15 @@ static struct clk_div_table pll4_main_div_table[] = {
98static struct clk *clk[VF610_CLK_END]; 98static struct clk *clk[VF610_CLK_END];
99static struct clk_onecell_data clk_data; 99static struct clk_onecell_data clk_data;
100 100
101static unsigned int const clks_init_on[] __initconst = {
102 VF610_CLK_SYS_BUS,
103 VF610_CLK_DDR_SEL,
104};
105
101static void __init vf610_clocks_init(struct device_node *ccm_node) 106static void __init vf610_clocks_init(struct device_node *ccm_node)
102{ 107{
103 struct device_node *np; 108 struct device_node *np;
109 int i;
104 110
105 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 111 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
106 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); 112 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
@@ -322,6 +328,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
322 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); 328 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
323 clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); 329 clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
324 330
331 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
332 clk_prepare_enable(clk[clks_init_on[i]]);
333
325 /* Add the clocks to provider list */ 334 /* Add the clocks to provider list */
326 clk_data.clks = clk; 335 clk_data.clks = clk;
327 clk_data.clk_num = ARRAY_SIZE(clk); 336 clk_data.clk_num = ARRAY_SIZE(clk);