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authorKukjin Kim <kgene.kim@samsung.com>2011-11-06 00:54:56 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-11-06 00:54:56 -0400
commit830145796a5c8f1ca3f87ea619063c1d99a57df5 (patch)
treee72a0ecacfcce228c46d93c946cfd65a44cc1fd3 /arch/arm/mach-exynos/include/mach
parente700e41d9abfbf9fee01e979a41b185695132c19 (diff)
ARM: EXYNOS: Add ARCH_EXYNOS and reorganize arch/arm/mach-exynos
The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has made for plaforms based on EXYNOS4 SoCs. But since upcoming Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most codes in current mach-exynos4, one mach-exynos directory will be used for them. This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos) but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to avoid changing in driver side. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/include/mach')
-rw-r--r--arch/arm/mach-exynos/include/mach/debug-macro.S35
-rw-r--r--arch/arm/mach-exynos/include/mach/dma.h26
-rw-r--r--arch/arm/mach-exynos/include/mach/dwmci.h20
-rw-r--r--arch/arm/mach-exynos/include/mach/entry-macro.S91
-rw-r--r--arch/arm/mach-exynos/include/mach/exynos4-clock.h43
-rw-r--r--arch/arm/mach-exynos/include/mach/gpio.h149
-rw-r--r--arch/arm/mach-exynos/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-exynos/include/mach/io.h26
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h169
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h197
-rw-r--r--arch/arm/mach-exynos/include/mach/memory.h22
-rw-r--r--arch/arm/mach-exynos/include/mach/pm-core.h65
-rw-r--r--arch/arm/mach-exynos/include/mach/pmu.h32
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-audss.h18
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h210
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-gpio.h42
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-irq.h19
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-mct.h53
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-mem.h23
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h220
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-sysmmu.h28
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-usb-phy.h64
-rw-r--r--arch/arm/mach-exynos/include/mach/sysmmu.h46
-rw-r--r--arch/arm/mach-exynos/include/mach/system.h22
-rw-r--r--arch/arm/mach-exynos/include/mach/timex.h29
-rw-r--r--arch/arm/mach-exynos/include/mach/uncompress.h30
-rw-r--r--arch/arm/mach-exynos/include/mach/vmalloc.h22
27 files changed, 1719 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
new file mode 100644
index 000000000000..6cacf16a67a6
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -0,0 +1,35 @@
1/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* pull in the relevant register and map files. */
14
15#include <mach/map.h>
16
17 /* note, for the boot process to work we have to keep the UART
18 * virtual address aligned to an 1MiB boundary for the L1
19 * mapping the head code makes. We keep the UART virtual address
20 * aligned and add in the offset when we load the value here.
21 */
22
23 .macro addruart, rp, rv, tmp
24 ldr \rp, = S3C_PA_UART
25 ldr \rv, = S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0
27 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
29#endif
30 .endm
31
32#define fifo_full fifo_full_s5pv210
33#define fifo_level fifo_level_s5pv210
34
35#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-exynos/include/mach/dma.h b/arch/arm/mach-exynos/include/mach/dma.h
new file mode 100644
index 000000000000..201842a3769e
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/dma.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common DMA API driver for PL330 */
24#include <plat/dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-exynos/include/mach/dwmci.h b/arch/arm/mach-exynos/include/mach/dwmci.h
new file mode 100644
index 000000000000..7ce657459cc0
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/dwmci.h
@@ -0,0 +1,20 @@
1/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Synopsys DesignWare Mobile Storage for EXYNOS4210
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARM_ARCH_DWMCI_H
14#define __ASM_ARM_ARCH_DWMCI_H __FILE__
15
16#include <linux/mmc/dw_mmc.h>
17
18extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
19
20#endif /* __ASM_ARM_ARCH_DWMCI_H */
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
new file mode 100644
index 000000000000..f5e9fd8e37b4
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/entry-macro.S
@@ -0,0 +1,91 @@
1/* arch/arm/mach-exynos4/include/mach/entry-macro.S
2 *
3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
4 *
5 * Low-level IRQ helper macros for EXYNOS4 platforms
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10*/
11
12#include <mach/hardware.h>
13#include <mach/map.h>
14#include <asm/hardware/gic.h>
15
16 .macro disable_fiq
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 mov \tmp, #0
21
22 mrc p15, 0, \base, c0, c0, 5
23 and \base, \base, #3
24 cmp \base, #0
25 beq 1f
26
27 ldr \tmp, =gic_bank_offset
28 ldr \tmp, [\tmp]
29 cmp \base, #1
30 beq 1f
31
32 cmp \base, #2
33 addeq \tmp, \tmp, \tmp
34 addne \tmp, \tmp, \tmp, LSL #1
35
361: ldr \base, =gic_cpu_base_addr
37 ldr \base, [\base]
38 add \base, \base, \tmp
39 .endm
40
41 .macro arch_ret_to_user, tmp1, tmp2
42 .endm
43
44 /*
45 * The interrupt numbering scheme is defined in the
46 * interrupt controller spec. To wit:
47 *
48 * Interrupts 0-15 are IPI
49 * 16-28 are reserved
50 * 29-31 are local. We allow 30 to be used for the watchdog.
51 * 32-1020 are global
52 * 1021-1022 are reserved
53 * 1023 is "spurious" (no interrupt)
54 *
55 * For now, we ignore all local interrupts so only return an interrupt if it's
56 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
57 *
58 * A simple read from the controller will tell us the number of the highest
59 * priority enabled interrupt. We then just need to check whether it is in the
60 * valid range for an IRQ (30-1020 inclusive).
61 */
62
63 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
64
65 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
66
67 ldr \tmp, =1021
68
69 bic \irqnr, \irqstat, #0x1c00
70
71 cmp \irqnr, #15
72 cmpcc \irqnr, \irqnr
73 cmpne \irqnr, \tmp
74 cmpcs \irqnr, \irqnr
75 addne \irqnr, \irqnr, #32
76
77 .endm
78
79 /* We assume that irqstat (the raw value of the IRQ acknowledge
80 * register) is preserved from the macro above.
81 * If there is an IPI, we immediately signal end of interrupt on the
82 * controller, since this requires the original irqstat value which
83 * we won't easily be able to recreate later.
84 */
85
86 .macro test_for_ipi, irqnr, irqstat, base, tmp
87 bic \irqnr, \irqstat, #0x1c00
88 cmp \irqnr, #16
89 strcc \irqstat, [\base, #GIC_CPU_EOI]
90 cmpcs \irqnr, \irqnr
91 .endm
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
new file mode 100644
index 000000000000..a07fcbf55251
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
@@ -0,0 +1,43 @@
1/*
2 * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Header file for exynos4 clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_CLOCK_H
15#define __ASM_ARCH_CLOCK_H __FILE__
16
17#include <linux/clk.h>
18
19extern struct clk clk_sclk_hdmi27m;
20extern struct clk clk_sclk_usbphy0;
21extern struct clk clk_sclk_usbphy1;
22extern struct clk clk_sclk_hdmiphy;
23
24extern struct clksrc_clk clk_sclk_apll;
25extern struct clksrc_clk clk_mout_mpll;
26extern struct clksrc_clk clk_aclk_133;
27extern struct clksrc_clk clk_mout_epll;
28extern struct clksrc_clk clk_sclk_vpll;
29
30extern struct clk *clkset_corebus_list[];
31extern struct clksrc_sources clkset_mout_corebus;
32
33extern struct clk *clkset_aclk_top_list[];
34extern struct clksrc_sources clkset_aclk;
35
36extern struct clk *clkset_group_list[];
37extern struct clksrc_sources clkset_group;
38
39extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
40extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
41extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
42
43#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
new file mode 100644
index 000000000000..80523ca9bb49
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -0,0 +1,149 @@
1/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16/* Practically, GPIO banks up to GPZ are the configurable gpio banks */
17
18/* GPIO bank sizes */
19#define EXYNOS4_GPIO_A0_NR (8)
20#define EXYNOS4_GPIO_A1_NR (6)
21#define EXYNOS4_GPIO_B_NR (8)
22#define EXYNOS4_GPIO_C0_NR (5)
23#define EXYNOS4_GPIO_C1_NR (5)
24#define EXYNOS4_GPIO_D0_NR (4)
25#define EXYNOS4_GPIO_D1_NR (4)
26#define EXYNOS4_GPIO_E0_NR (5)
27#define EXYNOS4_GPIO_E1_NR (8)
28#define EXYNOS4_GPIO_E2_NR (6)
29#define EXYNOS4_GPIO_E3_NR (8)
30#define EXYNOS4_GPIO_E4_NR (8)
31#define EXYNOS4_GPIO_F0_NR (8)
32#define EXYNOS4_GPIO_F1_NR (8)
33#define EXYNOS4_GPIO_F2_NR (8)
34#define EXYNOS4_GPIO_F3_NR (6)
35#define EXYNOS4_GPIO_J0_NR (8)
36#define EXYNOS4_GPIO_J1_NR (5)
37#define EXYNOS4_GPIO_K0_NR (7)
38#define EXYNOS4_GPIO_K1_NR (7)
39#define EXYNOS4_GPIO_K2_NR (7)
40#define EXYNOS4_GPIO_K3_NR (7)
41#define EXYNOS4_GPIO_L0_NR (8)
42#define EXYNOS4_GPIO_L1_NR (3)
43#define EXYNOS4_GPIO_L2_NR (8)
44#define EXYNOS4_GPIO_X0_NR (8)
45#define EXYNOS4_GPIO_X1_NR (8)
46#define EXYNOS4_GPIO_X2_NR (8)
47#define EXYNOS4_GPIO_X3_NR (8)
48#define EXYNOS4_GPIO_Y0_NR (6)
49#define EXYNOS4_GPIO_Y1_NR (4)
50#define EXYNOS4_GPIO_Y2_NR (6)
51#define EXYNOS4_GPIO_Y3_NR (8)
52#define EXYNOS4_GPIO_Y4_NR (8)
53#define EXYNOS4_GPIO_Y5_NR (8)
54#define EXYNOS4_GPIO_Y6_NR (8)
55#define EXYNOS4_GPIO_Z_NR (7)
56
57/* GPIO bank numbers */
58
59#define EXYNOS4_GPIO_NEXT(__gpio) \
60 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
61
62enum s5p_gpio_number {
63 EXYNOS4_GPIO_A0_START = 0,
64 EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
65 EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
66 EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
67 EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
68 EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
69 EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
70 EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
71 EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
72 EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
73 EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
74 EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
75 EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
76 EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
77 EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
78 EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
79 EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
80 EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
81 EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
82 EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
83 EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
84 EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
85 EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
86 EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
87 EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
88 EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
89 EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
90 EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
91 EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
92 EXYNOS4_GPIO_Y0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
93 EXYNOS4_GPIO_Y1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),
94 EXYNOS4_GPIO_Y2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),
95 EXYNOS4_GPIO_Y3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),
96 EXYNOS4_GPIO_Y4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),
97 EXYNOS4_GPIO_Y5_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),
98 EXYNOS4_GPIO_Y6_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),
99 EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),
100};
101
102/* EXYNOS4 GPIO number definitions */
103#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
104#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
105#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
106#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
107#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
108#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
109#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
110#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
111#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
112#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
113#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
114#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
115#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
116#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
117#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
118#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
119#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
120#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
121#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
122#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
123#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
124#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
125#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
126#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
127#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
128#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
129#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
130#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
131#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
132#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr))
133#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr))
134#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr))
135#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr))
136#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr))
137#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr))
138#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr))
139#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
140
141/* the end of the EXYNOS4 specific gpios */
142#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
143#define S3C_GPIO_END EXYNOS4_GPIO_END
144
145/* define the number of gpios we need to the one after the GPZ() range */
146#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \
147 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
148
149#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/hardware.h b/arch/arm/mach-exynos/include/mach/hardware.h
new file mode 100644
index 000000000000..5109eb232f23
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/hardware.h
@@ -0,0 +1,18 @@
1/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-exynos/include/mach/io.h b/arch/arm/mach-exynos/include/mach/io.h
new file mode 100644
index 000000000000..d5478d247535
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/io.h
@@ -0,0 +1,26 @@
1/* linux/arch/arm/mach-exynos4/include/mach/io.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
7 *
8 * Based on arch/arm/mach-s5p6442/include/mach/io.h
9 *
10 * Default IO routines for EXYNOS4
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17#ifndef __ASM_ARM_ARCH_IO_H
18#define __ASM_ARM_ARCH_IO_H __FILE__
19
20/* No current ISA/PCI bus support. */
21#define __io(a) __typesafe_io(a)
22#define __mem_pci(a) (a)
23
24#define IO_SPACE_LIMIT (0xFFFFFFFF)
25
26#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
new file mode 100644
index 000000000000..dfd4b7eecb90
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -0,0 +1,169 @@
1/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* PPI: Private Peripheral Interrupt */
19
20#define IRQ_PPI(x) S5P_IRQ(x+16)
21
22#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
23
24/* SPI: Shared Peripheral Interrupt */
25
26#define IRQ_SPI(x) S5P_IRQ(x+32)
27
28#define IRQ_EINT0 IRQ_SPI(16)
29#define IRQ_EINT1 IRQ_SPI(17)
30#define IRQ_EINT2 IRQ_SPI(18)
31#define IRQ_EINT3 IRQ_SPI(19)
32#define IRQ_EINT4 IRQ_SPI(20)
33#define IRQ_EINT5 IRQ_SPI(21)
34#define IRQ_EINT6 IRQ_SPI(22)
35#define IRQ_EINT7 IRQ_SPI(23)
36#define IRQ_EINT8 IRQ_SPI(24)
37#define IRQ_EINT9 IRQ_SPI(25)
38#define IRQ_EINT10 IRQ_SPI(26)
39#define IRQ_EINT11 IRQ_SPI(27)
40#define IRQ_EINT12 IRQ_SPI(28)
41#define IRQ_EINT13 IRQ_SPI(29)
42#define IRQ_EINT14 IRQ_SPI(30)
43#define IRQ_EINT15 IRQ_SPI(31)
44#define IRQ_EINT16_31 IRQ_SPI(32)
45
46#define IRQ_PDMA0 IRQ_SPI(35)
47#define IRQ_PDMA1 IRQ_SPI(36)
48#define IRQ_TIMER0_VIC IRQ_SPI(37)
49#define IRQ_TIMER1_VIC IRQ_SPI(38)
50#define IRQ_TIMER2_VIC IRQ_SPI(39)
51#define IRQ_TIMER3_VIC IRQ_SPI(40)
52#define IRQ_TIMER4_VIC IRQ_SPI(41)
53#define IRQ_MCT_L0 IRQ_SPI(42)
54#define IRQ_WDT IRQ_SPI(43)
55#define IRQ_RTC_ALARM IRQ_SPI(44)
56#define IRQ_RTC_TIC IRQ_SPI(45)
57#define IRQ_GPIO_XB IRQ_SPI(46)
58#define IRQ_GPIO_XA IRQ_SPI(47)
59#define IRQ_MCT_L1 IRQ_SPI(48)
60
61#define IRQ_UART0 IRQ_SPI(52)
62#define IRQ_UART1 IRQ_SPI(53)
63#define IRQ_UART2 IRQ_SPI(54)
64#define IRQ_UART3 IRQ_SPI(55)
65#define IRQ_UART4 IRQ_SPI(56)
66#define IRQ_MCT_G0 IRQ_SPI(57)
67#define IRQ_IIC IRQ_SPI(58)
68#define IRQ_IIC1 IRQ_SPI(59)
69#define IRQ_IIC2 IRQ_SPI(60)
70#define IRQ_IIC3 IRQ_SPI(61)
71#define IRQ_IIC4 IRQ_SPI(62)
72#define IRQ_IIC5 IRQ_SPI(63)
73#define IRQ_IIC6 IRQ_SPI(64)
74#define IRQ_IIC7 IRQ_SPI(65)
75
76#define IRQ_USB_HOST IRQ_SPI(70)
77#define IRQ_USB_HSOTG IRQ_SPI(71)
78#define IRQ_MODEM_IF IRQ_SPI(72)
79#define IRQ_HSMMC0 IRQ_SPI(73)
80#define IRQ_HSMMC1 IRQ_SPI(74)
81#define IRQ_HSMMC2 IRQ_SPI(75)
82#define IRQ_HSMMC3 IRQ_SPI(76)
83#define IRQ_DWMCI IRQ_SPI(77)
84
85#define IRQ_MIPI_CSIS0 IRQ_SPI(78)
86#define IRQ_MIPI_CSIS1 IRQ_SPI(80)
87
88#define IRQ_ONENAND_AUDI IRQ_SPI(82)
89#define IRQ_ROTATOR IRQ_SPI(83)
90#define IRQ_FIMC0 IRQ_SPI(84)
91#define IRQ_FIMC1 IRQ_SPI(85)
92#define IRQ_FIMC2 IRQ_SPI(86)
93#define IRQ_FIMC3 IRQ_SPI(87)
94#define IRQ_JPEG IRQ_SPI(88)
95#define IRQ_2D IRQ_SPI(89)
96#define IRQ_PCIE IRQ_SPI(90)
97
98#define IRQ_MIXER IRQ_SPI(91)
99#define IRQ_HDMI IRQ_SPI(92)
100#define IRQ_IIC_HDMIPHY IRQ_SPI(93)
101#define IRQ_MFC IRQ_SPI(94)
102#define IRQ_SDO IRQ_SPI(95)
103
104#define IRQ_AUDIO_SS IRQ_SPI(96)
105#define IRQ_I2S0 IRQ_SPI(97)
106#define IRQ_I2S1 IRQ_SPI(98)
107#define IRQ_I2S2 IRQ_SPI(99)
108#define IRQ_AC97 IRQ_SPI(100)
109
110#define IRQ_SPDIF IRQ_SPI(104)
111#define IRQ_ADC0 IRQ_SPI(105)
112#define IRQ_PEN0 IRQ_SPI(106)
113#define IRQ_ADC1 IRQ_SPI(107)
114#define IRQ_PEN1 IRQ_SPI(108)
115#define IRQ_KEYPAD IRQ_SPI(109)
116#define IRQ_PMU IRQ_SPI(110)
117#define IRQ_GPS IRQ_SPI(111)
118#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
119#define IRQ_SLIMBUS IRQ_SPI(113)
120
121#define IRQ_TSI IRQ_SPI(115)
122#define IRQ_SATA IRQ_SPI(116)
123
124#define MAX_IRQ_IN_COMBINER 8
125#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
126#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
127
128#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
129#define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
130#define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
131#define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
132#define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
133#define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
134#define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
135#define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
136
137#define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
138#define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
139#define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
140#define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
141#define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
142#define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
143#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
144#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
145
146#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
147#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
148#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
149
150#define MAX_COMBINER_NR 16
151
152#define IRQ_ADC IRQ_ADC0
153#define IRQ_TC IRQ_PEN0
154
155#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
156
157#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
158#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16)
159
160/* optional GPIO interrupts */
161#define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32)
162#define IRQ_GPIO1_NR_GROUPS 16
163#define IRQ_GPIO2_NR_GROUPS 9
164#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
165
166/* Set the default NR_IRQS */
167#define NR_IRQS (IRQ_GPIO_END + 64)
168
169#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
new file mode 100644
index 000000000000..058541d45af0
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -0,0 +1,197 @@
1/* linux/arch/arm/mach-exynos/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
26#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000
28
29#define EXYNOS4_PA_FIMC0 0x11800000
30#define EXYNOS4_PA_FIMC1 0x11810000
31#define EXYNOS4_PA_FIMC2 0x11820000
32#define EXYNOS4_PA_FIMC3 0x11830000
33
34#define EXYNOS4_PA_I2S0 0x03830000
35#define EXYNOS4_PA_I2S1 0xE3100000
36#define EXYNOS4_PA_I2S2 0xE2A00000
37
38#define EXYNOS4_PA_PCM0 0x03840000
39#define EXYNOS4_PA_PCM1 0x13980000
40#define EXYNOS4_PA_PCM2 0x13990000
41
42#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
43
44#define EXYNOS4_PA_ONENAND 0x0C000000
45#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
46
47#define EXYNOS4_PA_CHIPID 0x10000000
48
49#define EXYNOS4_PA_SYSCON 0x10010000
50#define EXYNOS4_PA_PMU 0x10020000
51#define EXYNOS4_PA_CMU 0x10030000
52
53#define EXYNOS4_PA_SYSTIMER 0x10050000
54#define EXYNOS4_PA_WATCHDOG 0x10060000
55#define EXYNOS4_PA_RTC 0x10070000
56
57#define EXYNOS4_PA_KEYPAD 0x100A0000
58
59#define EXYNOS4_PA_DMC0 0x10400000
60
61#define EXYNOS4_PA_COMBINER 0x10440000
62
63#define EXYNOS4_PA_GIC_CPU 0x10480000
64#define EXYNOS4_PA_GIC_DIST 0x10490000
65
66#define EXYNOS4_PA_COREPERI 0x10500000
67#define EXYNOS4_PA_TWD 0x10500600
68#define EXYNOS4_PA_L2CC 0x10502000
69
70#define EXYNOS4_PA_MDMA 0x10810000
71#define EXYNOS4_PA_PDMA0 0x12680000
72#define EXYNOS4_PA_PDMA1 0x12690000
73
74#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
75#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
76#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
77#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
78#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
79#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
80#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
81#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
82#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
83#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
84#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
85#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
86#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
87#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
88#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
89#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
90
91#define EXYNOS4_PA_GPIO1 0x11400000
92#define EXYNOS4_PA_GPIO2 0x11000000
93#define EXYNOS4_PA_GPIO3 0x03860000
94
95#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
96#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
97
98#define EXYNOS4_PA_FIMD0 0x11C00000
99
100#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
101#define EXYNOS4_PA_DWMCI 0x12550000
102
103#define EXYNOS4_PA_SATA 0x12560000
104#define EXYNOS4_PA_SATAPHY 0x125D0000
105#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
106
107#define EXYNOS4_PA_SROMC 0x12570000
108
109#define EXYNOS4_PA_EHCI 0x12580000
110#define EXYNOS4_PA_HSPHY 0x125B0000
111#define EXYNOS4_PA_MFC 0x13400000
112
113#define EXYNOS4_PA_UART 0x13800000
114
115#define EXYNOS4_PA_VP 0x12C00000
116#define EXYNOS4_PA_MIXER 0x12C10000
117#define EXYNOS4_PA_SDO 0x12C20000
118#define EXYNOS4_PA_HDMI 0x12D00000
119#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
120
121#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
122
123#define EXYNOS4_PA_ADC 0x13910000
124#define EXYNOS4_PA_ADC1 0x13911000
125
126#define EXYNOS4_PA_AC97 0x139A0000
127
128#define EXYNOS4_PA_SPDIF 0x139B0000
129
130#define EXYNOS4_PA_TIMER 0x139D0000
131
132#define EXYNOS4_PA_SDRAM 0x40000000
133
134/* Compatibiltiy Defines */
135
136#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
137#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
138#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
139#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
140#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
141#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
142#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
143#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
144#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
145#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
146#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
147#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
148#define S3C_PA_RTC EXYNOS4_PA_RTC
149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
150#define S3C_PA_UART EXYNOS4_PA_UART
151
152#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
153#define S5P_PA_EHCI EXYNOS4_PA_EHCI
154#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
155#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
156#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
157#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
158#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
159#define S5P_PA_HDMI EXYNOS4_PA_HDMI
160#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
161#define S5P_PA_MFC EXYNOS4_PA_MFC
162#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
163#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
164#define S5P_PA_MIXER EXYNOS4_PA_MIXER
165#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
166#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
167#define S5P_PA_SDO EXYNOS4_PA_SDO
168#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
169#define S5P_PA_SROMC EXYNOS4_PA_SROMC
170#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
171#define S5P_PA_TIMER EXYNOS4_PA_TIMER
172#define S5P_PA_VP EXYNOS4_PA_VP
173
174#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
175#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
176#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
177
178#define EXYNOS_PA_COMBINER EXYNOS4_PA_COMBINER
179#define EXYNOS_PA_GIC_CPU EXYNOS4_PA_GIC_CPU
180#define EXYNOS_PA_GIC_DIST EXYNOS4_PA_GIC_DIST
181#define EXYNOS_PA_PMU EXYNOS4_PA_PMU
182#define EXYNOS_PA_SYSTIMER EXYNOS4_PA_SYSTIMER
183
184/* Compatibility UART */
185
186#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
187
188#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
189#define S5P_PA_UART0 S5P_PA_UART(0)
190#define S5P_PA_UART1 S5P_PA_UART(1)
191#define S5P_PA_UART2 S5P_PA_UART(2)
192#define S5P_PA_UART3 S5P_PA_UART(3)
193#define S5P_PA_UART4 S5P_PA_UART(4)
194
195#define S5P_SZ_UART SZ_256
196
197#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
new file mode 100644
index 000000000000..374ef2cf7152
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/memory.h
@@ -0,0 +1,22 @@
1/* linux/arch/arm/mach-exynos4/include/mach/memory.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Memory definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H __FILE__
15
16#define PLAT_PHYS_OFFSET UL(0x40000000)
17
18/* Maximum of 256MiB in one bank */
19#define MAX_PHYSMEM_BITS 32
20#define SECTION_SIZE_BITS 28
21
22#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
new file mode 100644
index 000000000000..9d8da51e35ca
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -0,0 +1,65 @@
1/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#ifndef __ASM_ARCH_PM_CORE_H
19#define __ASM_ARCH_PM_CORE_H __FILE__
20
21#include <mach/regs-pmu.h>
22
23static inline void s3c_pm_debug_init_uart(void)
24{
25 /* nothing here yet */
26}
27
28static inline void s3c_pm_arch_prepare_irqs(void)
29{
30 unsigned int tmp;
31 tmp = __raw_readl(S5P_WAKEUP_MASK);
32 tmp &= ~(1 << 31);
33 __raw_writel(tmp, S5P_WAKEUP_MASK);
34
35 __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
36 __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
37}
38
39static inline void s3c_pm_arch_stop_clocks(void)
40{
41 /* nothing here yet */
42}
43
44static inline void s3c_pm_arch_show_resume_irqs(void)
45{
46 /* nothing here yet */
47}
48
49static inline void s3c_pm_arch_update_uart(void __iomem *regs,
50 struct pm_uart_save *save)
51{
52 /* nothing here yet */
53}
54
55static inline void s3c_pm_restored_gpios(void)
56{
57 /* nothing here yet */
58}
59
60static inline void samsung_pm_saved_gpios(void)
61{
62 /* nothing here yet */
63}
64
65#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
new file mode 100644
index 000000000000..632dd5630138
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/pmu.h
@@ -0,0 +1,32 @@
1/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4210 - PMU(Power Management Unit) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_PMU_H
14#define __ASM_ARCH_PMU_H __FILE__
15
16#define PMU_TABLE_END NULL
17
18enum sys_powerdown {
19 SYS_AFTR,
20 SYS_LPA,
21 SYS_SLEEP,
22 NUM_SYS_POWERDOWN,
23};
24
25struct exynos4_pmu_conf {
26 void __iomem *reg;
27 unsigned int val[NUM_SYS_POWERDOWN];
28};
29
30extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
31
32#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-audss.h b/arch/arm/mach-exynos/include/mach/regs-audss.h
new file mode 100644
index 000000000000..ca5a8b64218a
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-audss.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-exynos4/include/mach/regs-audss.h
2 *
3 * Copyright (c) 2011 Samsung Electronics
4 * http://www.samsung.com
5 *
6 * Exynos4 Audio SubSystem clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_REGS_AUDSS_H
14#define __PLAT_REGS_AUDSS_H __FILE__
15
16#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
17
18#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
new file mode 100644
index 000000000000..6c37ebe94829
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -0,0 +1,210 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <plat/cpu.h>
17#include <mach/map.h>
18
19#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
20
21#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
22#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
23#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800)
24
25#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
26#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
27#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
28
29#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
30#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
31
32#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
33#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
34#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
35#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
36
37#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
38#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
39#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
40#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
41#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
42#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
43#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
44#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
45#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
46#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
47#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
48#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
49
50#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
51#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
52#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
53#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
54#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
55#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
56#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
57#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
58
59#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
60#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
61#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
62#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528)
63#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
64#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
65#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
66#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
67#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
68#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
69#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
70#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
71#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
72#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
73#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
74#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
75#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
76#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
77#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
78
79#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
80
81#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
82#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
83#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
84#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
85#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
86#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
87 S5P_CLKREG(0x0C930) : \
88 S5P_CLKREG(0x04930))
89#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930)
90#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930)
91#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
92#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
93#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
94#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
95#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
96 S5P_CLKREG(0x0C960) : \
97 S5P_CLKREG(0x08960))
98#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960)
99#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960)
100#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
101
102#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
103#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
104#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
105#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504)
106#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
107#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
108
109#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
110#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \
111 S5P_CLKREG(0x14004) : \
112 S5P_CLKREG(0x10008))
113#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
114#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
115#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \
116 S5P_CLKREG(0x14108) : \
117 S5P_CLKREG(0x10108))
118#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \
119 S5P_CLKREG(0x1410C) : \
120 S5P_CLKREG(0x1010C))
121
122#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
123#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
124
125#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
126#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
127#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
128#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
129
130#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
131#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900)
132
133#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
134
135#define S5P_APLLCON0_ENABLE_SHIFT (31)
136#define S5P_APLLCON0_LOCKED_SHIFT (29)
137#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
138#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
139
140#define S5P_EPLLCON0_ENABLE_SHIFT (31)
141#define S5P_EPLLCON0_LOCKED_SHIFT (29)
142
143#define S5P_VPLLCON0_ENABLE_SHIFT (31)
144#define S5P_VPLLCON0_LOCKED_SHIFT (29)
145
146#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
147#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
148
149#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
150#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
151#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
152#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
153#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8)
154#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
155#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12)
156#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
157#define S5P_CLKDIV_CPU0_ATB_SHIFT (16)
158#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
159#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
160#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
161#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
162#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
163
164#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
165#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
166#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
167#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
168#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8)
169#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
170#define S5P_CLKDIV_DMC0_DMC_SHIFT (12)
171#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
172#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16)
173#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
174#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20)
175#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
176#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24)
177#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
178#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
179#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
180
181#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
182#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
183#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
184#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
185#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8)
186#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
187#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12)
188#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
189#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
190#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
191
192#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
193#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
194#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
195#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
196
197/* Only for EXYNOS4210 */
198
199#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
200#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
201#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
202#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
203
204/* Compatibility defines and inclusion */
205
206#include <mach/regs-pmu.h>
207
208#define S5P_EPLL_CON S5P_EPLL_CON0
209
210#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..1401b21663a5
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -0,0 +1,42 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
21
22#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
23#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
24
25#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
26#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
27
28#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
30
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
38#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
39#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
40#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-irq.h b/arch/arm/mach-exynos/include/mach/regs-irq.h
new file mode 100644
index 000000000000..9c7b4bfd546f
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-irq.h
@@ -0,0 +1,19 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <asm/hardware/gic.h>
17#include <mach/map.h>
18
19#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
new file mode 100644
index 000000000000..80dd02ad6d61
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-mct.h
@@ -0,0 +1,53 @@
1/* arch/arm/mach-exynos4/include/mach/regs-mct.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT configutation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_MCT_H
14#define __ASM_ARCH_REGS_MCT_H __FILE__
15
16#include <mach/map.h>
17
18#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
19
20#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
21#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
22#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
23
24#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
25#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
26#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
27
28#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
29
30#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
31#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
32#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
33
34#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
35#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
36#define EXYNOS4_MCT_L_MASK (0xffffff00)
37
38#define MCT_L_TCNTB_OFFSET (0x00)
39#define MCT_L_ICNTB_OFFSET (0x08)
40#define MCT_L_TCON_OFFSET (0x20)
41#define MCT_L_INT_CSTAT_OFFSET (0x30)
42#define MCT_L_INT_ENB_OFFSET (0x34)
43#define MCT_L_WSTAT_OFFSET (0x40)
44
45#define MCT_G_TCON_START (1 << 8)
46#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
47#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
48
49#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
50#define MCT_L_TCON_INT_START (1 << 1)
51#define MCT_L_TCON_TIMER_START (1 << 0)
52
53#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-mem.h b/arch/arm/mach-exynos/include/mach/regs-mem.h
new file mode 100644
index 000000000000..0368b5a27252
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-mem.h
@@ -0,0 +1,23 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - SROMC and DMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_MEM_H
14#define __ASM_ARCH_REGS_MEM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_DMC0_MEMCON_OFFSET 0x04
19
20#define S5P_DMC0_MEMTYPE_SHIFT 8
21#define S5P_DMC0_MEMTYPE_MASK 0xF
22
23#endif /* __ASM_ARCH_REGS_MEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
new file mode 100644
index 000000000000..4fff8e938fec
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -0,0 +1,220 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Power management unit definition
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_PMU_H
14#define __ASM_ARCH_REGS_PMU_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19
20#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
21
22#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
23
24#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
25
26#define S5P_USE_STANDBY_WFI0 (1 << 16)
27#define S5P_USE_STANDBY_WFI1 (1 << 17)
28#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18)
29#define S5P_USE_STANDBY_WFE0 (1 << 24)
30#define S5P_USE_STANDBY_WFE1 (1 << 25)
31#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
32
33#define S5P_SWRESET S5P_PMUREG(0x0400)
34
35#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
36#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
37#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
38
39#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
40#define S5P_HDMI_PHY_ENABLE (1 << 0)
41
42#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
43#define S5P_DAC_PHY_ENABLE (1 << 0)
44
45#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
46#define S5P_MIPI_DPHY_ENABLE (1 << 0)
47#define S5P_MIPI_DPHY_SRESETN (1 << 1)
48#define S5P_MIPI_DPHY_MRESETN (1 << 2)
49
50#define S5P_INFORM0 S5P_PMUREG(0x0800)
51#define S5P_INFORM1 S5P_PMUREG(0x0804)
52#define S5P_INFORM2 S5P_PMUREG(0x0808)
53#define S5P_INFORM3 S5P_PMUREG(0x080C)
54#define S5P_INFORM4 S5P_PMUREG(0x0810)
55#define S5P_INFORM5 S5P_PMUREG(0x0814)
56#define S5P_INFORM6 S5P_PMUREG(0x0818)
57#define S5P_INFORM7 S5P_PMUREG(0x081C)
58
59#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
60#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
61#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
62#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
63#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
64#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
65#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
66#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
67#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
68#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
69#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
70#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
71#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
72#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
73#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
74#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
75#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
76#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
77#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
78#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
79#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
80#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
81#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
82#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
83#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
84#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
85#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
86#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
87#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
88#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
89#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
90#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
91#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
92#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
93#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
94#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
95#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
96#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
97#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
98#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
99#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
100#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
101#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
102#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
103#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
104#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
105#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
106#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
107#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
108#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
109#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
110#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
111#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
112#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
113#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
114#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
115#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
116#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
117#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
118#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
119#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
120#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
121#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
122#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
123#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
124
125#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
126#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
127#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
128#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
129#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
130
131#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
132#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
133#define S5P_CAM_OPTION S5P_PMUREG(0x3C08)
134#define S5P_TV_OPTION S5P_PMUREG(0x3C28)
135#define S5P_MFC_OPTION S5P_PMUREG(0x3C48)
136#define S5P_G3D_OPTION S5P_PMUREG(0x3C68)
137#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88)
138#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8)
139#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8)
140#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8)
141#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08)
142
143#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
144#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
145#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
146#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
147#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
148#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
149#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
150
151#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
152#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
153#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
154#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
155#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
156#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
157
158#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
159#define S5P_CORE_LOCAL_PWR_EN 0x3
160#define S5P_INT_LOCAL_PWR_EN 0x7
161
162#define S5P_CHECK_SLEEP 0x00000BAD
163
164/* Only for EXYNOS4210 */
165#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
166#define S5P_USBHOST_PHY_ENABLE (1 << 0)
167
168#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
169
170#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
171#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
172#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
173#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
174#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
175#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
176
177#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
178
179/* Only for EXYNOS4212 */
180#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
181#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
182#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
183#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
184#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
185#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
186#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
187#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
188#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
189#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
190#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
191#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
192#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
193#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
194#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
195#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
196#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
197#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
198#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
199#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
200#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
201#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
202#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
203#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
204#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
205#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
206#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
207#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
208
209#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
210#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
211#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
212#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
213#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
214#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
215#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
216#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
217#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
218#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
219
220#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
new file mode 100644
index 000000000000..68ff6ad08a2b
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
@@ -0,0 +1,28 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - System MMU register
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_SYSMMU_H
14#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
15
16#define S5P_MMU_CTRL 0x000
17#define S5P_MMU_CFG 0x004
18#define S5P_MMU_STATUS 0x008
19#define S5P_MMU_FLUSH 0x00C
20#define S5P_PT_BASE_ADDR 0x014
21#define S5P_INT_STATUS 0x018
22#define S5P_INT_CLEAR 0x01C
23#define S5P_PAGE_FAULT_ADDR 0x024
24#define S5P_AW_FAULT_ADDR 0x028
25#define S5P_AR_FAULT_ADDR 0x02C
26#define S5P_DEFAULT_SLAVE_ADDR 0x030
27
28#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
new file mode 100644
index 000000000000..c337cf3a71bf
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __PLAT_S5P_REGS_USB_PHY_H
12#define __PLAT_S5P_REGS_USB_PHY_H
13
14#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
15
16#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
17#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
18#define PHY1_HSIC1_SLEEP (1 << 12)
19#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11)
20#define PHY1_HSIC0_SLEEP (1 << 10)
21#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9)
22
23#define PHY1_STD_NORMAL_MASK (0x7 << 6)
24#define PHY1_STD_SLEEP (1 << 8)
25#define PHY1_STD_ANALOG_POWERDOWN (1 << 7)
26#define PHY1_STD_FORCE_SUSPEND (1 << 6)
27
28#define PHY0_NORMAL_MASK (0x39 << 0)
29#define PHY0_SLEEP (1 << 5)
30#define PHY0_OTG_DISABLE (1 << 4)
31#define PHY0_ANALOG_POWERDOWN (1 << 3)
32#define PHY0_FORCE_SUSPEND (1 << 0)
33
34#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04)
35#define PHY1_COMMON_ON_N (1 << 7)
36#define PHY0_COMMON_ON_N (1 << 4)
37#define PHY0_ID_PULLUP (1 << 2)
38#define CLKSEL_MASK (0x3 << 0)
39#define CLKSEL_SHIFT (0)
40#define CLKSEL_48M (0x0 << 0)
41#define CLKSEL_12M (0x2 << 0)
42#define CLKSEL_24M (0x3 << 0)
43
44#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
45#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
46#define HOST_LINK_PORT2_SWRST (1 << 9)
47#define HOST_LINK_PORT1_SWRST (1 << 8)
48#define HOST_LINK_PORT0_SWRST (1 << 7)
49#define HOST_LINK_ALL_SWRST (1 << 6)
50
51#define PHY1_SWRST_MASK (0x7 << 3)
52#define PHY1_HSIC_SWRST (1 << 5)
53#define PHY1_STD_SWRST (1 << 4)
54#define PHY1_ALL_SWRST (1 << 3)
55
56#define PHY0_SWRST_MASK (0x7 << 0)
57#define PHY0_PHYLINK_SWRST (1 << 2)
58#define PHY0_HLINK_SWRST (1 << 1)
59#define PHY0_SWRST (1 << 0)
60
61#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
62#define FPENABLEN (1 << 0)
63
64#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
new file mode 100644
index 000000000000..6a5fbb534e82
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/sysmmu.h
@@ -0,0 +1,46 @@
1/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung sysmmu driver for EXYNOS4
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARM_ARCH_SYSMMU_H
14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
15
16enum exynos4_sysmmu_ips {
17 SYSMMU_MDMA,
18 SYSMMU_SSS,
19 SYSMMU_FIMC0,
20 SYSMMU_FIMC1,
21 SYSMMU_FIMC2,
22 SYSMMU_FIMC3,
23 SYSMMU_JPEG,
24 SYSMMU_FIMD0,
25 SYSMMU_FIMD1,
26 SYSMMU_PCIe,
27 SYSMMU_G2D,
28 SYSMMU_ROTATOR,
29 SYSMMU_MDMA2,
30 SYSMMU_TV,
31 SYSMMU_MFC_L,
32 SYSMMU_MFC_R,
33 EXYNOS4_SYSMMU_TOTAL_IPNUM,
34};
35
36#define S5P_SYSMMU_TOTAL_IPNUM EXYNOS4_SYSMMU_TOTAL_IPNUM
37
38extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
39
40typedef enum exynos4_sysmmu_ips sysmmu_ips;
41
42void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
43void sysmmu_clk_enable(sysmmu_ips ips);
44void sysmmu_clk_disable(sysmmu_ips ips);
45
46#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
new file mode 100644
index 000000000000..5e3220c18fc7
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -0,0 +1,22 @@
1/* linux/arch/arm/mach-exynos4/include/mach/system.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - system support header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__
15
16#include <plat/system-reset.h>
17
18static void arch_idle(void)
19{
20 /* nothing here yet */
21}
22#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/timex.h b/arch/arm/mach-exynos/include/mach/timex.h
new file mode 100644
index 000000000000..6d138750a708
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/timex.h
@@ -0,0 +1,29 @@
1/* linux/arch/arm/mach-exynos4/include/mach/timex.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (c) 2003-2010 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 *
9 * Based on arch/arm/mach-s5p6442/include/mach/timex.h
10 *
11 * EXYNOS4 - time parameters
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#ifndef __ASM_ARCH_TIMEX_H
19#define __ASM_ARCH_TIMEX_H __FILE__
20
21/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
22 * a variable is useless. It seems as long as we make our timers an
23 * exact multiple of HZ, any value that makes a 1->1 correspondence
24 * for the time conversion functions to/from jiffies is acceptable.
25*/
26
27#define CLOCK_TICK_RATE 12000000
28
29#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
new file mode 100644
index 000000000000..21d97bcd9acb
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -0,0 +1,30 @@
1/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H __FILE__
15
16#include <mach/map.h>
17#include <plat/uncompress.h>
18
19static void arch_detect_cpu(void)
20{
21 /* we do not need to do any cpu detection here at the moment. */
22
23 /*
24 * For preventing FIFO overrun or infinite loop of UART console,
25 * fifo_max should be the minimum fifo size of all of the UART channels
26 */
27 fifo_mask = S5PV210_UFSTAT_TXMASK;
28 fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT;
29}
30#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-exynos/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h
new file mode 100644
index 000000000000..284330e571d2
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/vmalloc.h
@@ -0,0 +1,22 @@
1/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
7 *
8 * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * EXYNOS4 vmalloc definition
15*/
16
17#ifndef __ASM_ARCH_VMALLOC_H
18#define __ASM_ARCH_VMALLOC_H __FILE__
19
20#define VMALLOC_END 0xF6000000UL
21
22#endif /* __ASM_ARCH_VMALLOC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 09:42:04 -0500