ARM: 8604/1: V7M: Add support for reading the CTR with read_cpuid_cachetype()

With the addition of caches to the V7M Architecture a new Cache Type
Register (CTR) is defined at 0xE000ED7C. This register serves the same
purpose as the V7A/R version and accessed via the read_cpuid_cachetype.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Andras Szemzo <sza@esh.hu>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 5 insertions, 4 deletions

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d7568808eb7b..34e3f3c45634 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -312,11 +312,12 @@ static void __init cacheid_init(void)
 {
         unsigned int arch = cpu_architecture();
 
-        if (arch == CPU_ARCH_ARMv7M) {
-                cacheid = 0;
-        } else if (arch >= CPU_ARCH_ARMv6) {
+        if (arch >= CPU_ARCH_ARMv6) {
                 unsigned int cachetype = read_cpuid_cachetype();
-                if ((cachetype & (7 << 29)) == 4 << 29) {
+
+                if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
+                        cacheid = 0;
+                } else if ((cachetype & (7 << 29)) == 4 << 29) {
                         /* ARMv7 register format */
                         arch = CPU_ARCH_ARMv7;
                         cacheid = CACHEID_VIPT_NONALIASING;