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authorLinus Torvalds <torvalds@linux-foundation.org>2013-11-13 18:51:29 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-11-13 18:51:29 -0500
commitf47671e2d861a2093179cd64dda22016664b2015 (patch)
treef77cb8e7d875f442e2cf0bdc8fbe478ec8ff8181 /arch/arm/kernel/module.c
parent8ceafbfa91ffbdbb2afaea5c24ccb519ffb8b587 (diff)
parent42cbe8271ca6562b4ad4b2e6a9895084b16eef5e (diff)
Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM updates from Russell King: "Included in this series are: 1. BE8 (modern big endian) changes for ARM from Ben Dooks 2. big.Little support from Nicolas Pitre and Dave Martin 3. support for LPAE systems with all system memory above 4GB 4. Perf updates from Will Deacon 5. Additional prefetching and other performance improvements from Will. 6. Neon-optimised AES implementation fro Ard. 7. A number of smaller fixes scattered around the place. There is a rather horrid merge conflict in tools/perf - I was never notified of the conflict because it originally occurred between Will's tree and other stuff. Consequently I have a resolution which Will forwarded me, which I'll forward on immediately after sending this mail. The other notable thing is I'm expecting some build breakage in the crypto stuff on ARM only with Ard's AES patches. These were merged into a stable git branch which others had already pulled, so there's little I can do about this. The problem is caused because these patches have a dependency on some code in the crypto git tree - I tried requesting a branch I can pull to resolve these, and all I got each time from the crypto people was "we'll revert our patches then" which would only make things worse since I still don't have the dependent patches. I've no idea what's going on there or how to resolve that, and since I can't split these patches from the rest of this pull request, I'm rather stuck with pushing this as-is or reverting Ard's patches. Since it should "come out in the wash" I've left them in - the only build problems they seem to cause at the moment are with randconfigs, and since it's a new feature anyway. However, if by -rc1 the dependencies aren't in, I think it'd be best to revert Ard's patches" I resolved the perf conflict roughly as per the patch sent by Russell, but there may be some differences. Any errors are likely mine. Let's see how the crypto issues work out.. * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (110 commits) ARM: 7868/1: arm/arm64: remove atomic_clear_mask() in "include/asm/atomic.h" ARM: 7867/1: include: asm: use 'int' instead of 'unsigned long' for 'oldval' in atomic_cmpxchg(). ARM: 7866/1: include: asm: use 'long long' instead of 'u64' within atomic.h ARM: 7871/1: amba: Extend number of IRQS ARM: 7887/1: Don't smp_cross_call() on UP devices in arch_irq_work_raise() ARM: 7872/1: Support arch_irq_work_raise() via self IPIs ARM: 7880/1: Clear the IT state independent of the Thumb-2 mode ARM: 7878/1: nommu: Implement dummy early_paging_init() ARM: 7876/1: clear Thumb-2 IT state on exception handling ARM: 7874/2: bL_switcher: Remove cpu_hotplug_driver_{lock,unlock}() ARM: footbridge: fix build warnings for netwinder ARM: 7873/1: vfp: clear vfp_current_hw_state for dying cpu ARM: fix misplaced arch_virt_to_idmap() ARM: 7848/1: mcpm: Implement cpu_kill() to synchronise on powerdown ARM: 7847/1: mcpm: Factor out logical-to-physical CPU translation ARM: 7869/1: remove unused XSCALE_PMU Kconfig param ARM: 7864/1: Handle 64-bit memory in case of 32-bit phys_addr_t ARM: 7863/1: Let arm_add_memory() always use 64-bit arguments ARM: 7862/1: pcpu: replace __get_cpu_var_uses ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling code ...
Diffstat (limited to 'arch/arm/kernel/module.c')
-rw-r--r--arch/arm/kernel/module.c57
1 files changed, 34 insertions, 23 deletions
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index c9dfff3b8008..45e478157278 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -24,6 +24,7 @@
24#include <asm/sections.h> 24#include <asm/sections.h>
25#include <asm/smp_plat.h> 25#include <asm/smp_plat.h>
26#include <asm/unwind.h> 26#include <asm/unwind.h>
27#include <asm/opcodes.h>
27 28
28#ifdef CONFIG_XIP_KERNEL 29#ifdef CONFIG_XIP_KERNEL
29/* 30/*
@@ -60,6 +61,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
60 Elf32_Sym *sym; 61 Elf32_Sym *sym;
61 const char *symname; 62 const char *symname;
62 s32 offset; 63 s32 offset;
64 u32 tmp;
63#ifdef CONFIG_THUMB2_KERNEL 65#ifdef CONFIG_THUMB2_KERNEL
64 u32 upper, lower, sign, j1, j2; 66 u32 upper, lower, sign, j1, j2;
65#endif 67#endif
@@ -95,7 +97,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
95 case R_ARM_PC24: 97 case R_ARM_PC24:
96 case R_ARM_CALL: 98 case R_ARM_CALL:
97 case R_ARM_JUMP24: 99 case R_ARM_JUMP24:
98 offset = (*(u32 *)loc & 0x00ffffff) << 2; 100 offset = __mem_to_opcode_arm(*(u32 *)loc);
101 offset = (offset & 0x00ffffff) << 2;
99 if (offset & 0x02000000) 102 if (offset & 0x02000000)
100 offset -= 0x04000000; 103 offset -= 0x04000000;
101 104
@@ -111,9 +114,10 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
111 } 114 }
112 115
113 offset >>= 2; 116 offset >>= 2;
117 offset &= 0x00ffffff;
114 118
115 *(u32 *)loc &= 0xff000000; 119 *(u32 *)loc &= __opcode_to_mem_arm(0xff000000);
116 *(u32 *)loc |= offset & 0x00ffffff; 120 *(u32 *)loc |= __opcode_to_mem_arm(offset);
117 break; 121 break;
118 122
119 case R_ARM_V4BX: 123 case R_ARM_V4BX:
@@ -121,8 +125,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
121 * other bits to re-code instruction as 125 * other bits to re-code instruction as
122 * MOV PC,Rm. 126 * MOV PC,Rm.
123 */ 127 */
124 *(u32 *)loc &= 0xf000000f; 128 *(u32 *)loc &= __opcode_to_mem_arm(0xf000000f);
125 *(u32 *)loc |= 0x01a0f000; 129 *(u32 *)loc |= __opcode_to_mem_arm(0x01a0f000);
126 break; 130 break;
127 131
128 case R_ARM_PREL31: 132 case R_ARM_PREL31:
@@ -132,7 +136,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
132 136
133 case R_ARM_MOVW_ABS_NC: 137 case R_ARM_MOVW_ABS_NC:
134 case R_ARM_MOVT_ABS: 138 case R_ARM_MOVT_ABS:
135 offset = *(u32 *)loc; 139 offset = tmp = __mem_to_opcode_arm(*(u32 *)loc);
136 offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff); 140 offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
137 offset = (offset ^ 0x8000) - 0x8000; 141 offset = (offset ^ 0x8000) - 0x8000;
138 142
@@ -140,16 +144,18 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
140 if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS) 144 if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS)
141 offset >>= 16; 145 offset >>= 16;
142 146
143 *(u32 *)loc &= 0xfff0f000; 147 tmp &= 0xfff0f000;
144 *(u32 *)loc |= ((offset & 0xf000) << 4) | 148 tmp |= ((offset & 0xf000) << 4) |
145 (offset & 0x0fff); 149 (offset & 0x0fff);
150
151 *(u32 *)loc = __opcode_to_mem_arm(tmp);
146 break; 152 break;
147 153
148#ifdef CONFIG_THUMB2_KERNEL 154#ifdef CONFIG_THUMB2_KERNEL
149 case R_ARM_THM_CALL: 155 case R_ARM_THM_CALL:
150 case R_ARM_THM_JUMP24: 156 case R_ARM_THM_JUMP24:
151 upper = *(u16 *)loc; 157 upper = __mem_to_opcode_thumb16(*(u16 *)loc);
152 lower = *(u16 *)(loc + 2); 158 lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2));
153 159
154 /* 160 /*
155 * 25 bit signed address range (Thumb-2 BL and B.W 161 * 25 bit signed address range (Thumb-2 BL and B.W
@@ -198,17 +204,20 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
198 sign = (offset >> 24) & 1; 204 sign = (offset >> 24) & 1;
199 j1 = sign ^ (~(offset >> 23) & 1); 205 j1 = sign ^ (~(offset >> 23) & 1);
200 j2 = sign ^ (~(offset >> 22) & 1); 206 j2 = sign ^ (~(offset >> 22) & 1);
201 *(u16 *)loc = (u16)((upper & 0xf800) | (sign << 10) | 207 upper = (u16)((upper & 0xf800) | (sign << 10) |
202 ((offset >> 12) & 0x03ff)); 208 ((offset >> 12) & 0x03ff));
203 *(u16 *)(loc + 2) = (u16)((lower & 0xd000) | 209 lower = (u16)((lower & 0xd000) |
204 (j1 << 13) | (j2 << 11) | 210 (j1 << 13) | (j2 << 11) |
205 ((offset >> 1) & 0x07ff)); 211 ((offset >> 1) & 0x07ff));
212
213 *(u16 *)loc = __opcode_to_mem_thumb16(upper);
214 *(u16 *)(loc + 2) = __opcode_to_mem_thumb16(lower);
206 break; 215 break;
207 216
208 case R_ARM_THM_MOVW_ABS_NC: 217 case R_ARM_THM_MOVW_ABS_NC:
209 case R_ARM_THM_MOVT_ABS: 218 case R_ARM_THM_MOVT_ABS:
210 upper = *(u16 *)loc; 219 upper = __mem_to_opcode_thumb16(*(u16 *)loc);
211 lower = *(u16 *)(loc + 2); 220 lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2));
212 221
213 /* 222 /*
214 * MOVT/MOVW instructions encoding in Thumb-2: 223 * MOVT/MOVW instructions encoding in Thumb-2:
@@ -229,12 +238,14 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
229 if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS) 238 if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
230 offset >>= 16; 239 offset >>= 16;
231 240
232 *(u16 *)loc = (u16)((upper & 0xfbf0) | 241 upper = (u16)((upper & 0xfbf0) |
233 ((offset & 0xf000) >> 12) | 242 ((offset & 0xf000) >> 12) |
234 ((offset & 0x0800) >> 1)); 243 ((offset & 0x0800) >> 1));
235 *(u16 *)(loc + 2) = (u16)((lower & 0x8f00) | 244 lower = (u16)((lower & 0x8f00) |
236 ((offset & 0x0700) << 4) | 245 ((offset & 0x0700) << 4) |
237 (offset & 0x00ff)); 246 (offset & 0x00ff));
247 *(u16 *)loc = __opcode_to_mem_thumb16(upper);
248 *(u16 *)(loc + 2) = __opcode_to_mem_thumb16(lower);
238 break; 249 break;
239#endif 250#endif
240 251