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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-03-15 12:47:49 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-29 19:47:41 -0400
commit14b882cfa3f9db3430037dca6038e161eda953a1 (patch)
treeeed503cb7e2cd572d1055dec4916e6439372bb04 /arch/arm/include/asm/hardware
parent83841fe1fb0c4316af89ab85d3528702724a33f4 (diff)
ARM: l2c: add and use L2C revision constants
The revision namespace is specific to the L2 cache part, so don't name these with generic identifiers, use a part specific identifier. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/hardware')
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h22
1 files changed, 16 insertions, 6 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 6795ff743b3d..3af45734b514 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -68,14 +68,24 @@
68/* Registers shifts and masks */ 68/* Registers shifts and masks */
69#define L2X0_CACHE_ID_PART_MASK (0xf << 6) 69#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
70#define L2X0_CACHE_ID_PART_L210 (1 << 6) 70#define L2X0_CACHE_ID_PART_L210 (1 << 6)
71#define L2X0_CACHE_ID_PART_L220 (2 << 6)
71#define L2X0_CACHE_ID_PART_L310 (3 << 6) 72#define L2X0_CACHE_ID_PART_L310 (3 << 6)
72#define L2X0_CACHE_ID_RTL_MASK 0x3f 73#define L2X0_CACHE_ID_RTL_MASK 0x3f
73#define L2X0_CACHE_ID_RTL_R0P0 0x0 74#define L210_CACHE_ID_RTL_R0P2_02 0x00
74#define L2X0_CACHE_ID_RTL_R1P0 0x2 75#define L210_CACHE_ID_RTL_R0P1 0x01
75#define L2X0_CACHE_ID_RTL_R2P0 0x4 76#define L210_CACHE_ID_RTL_R0P2_01 0x02
76#define L2X0_CACHE_ID_RTL_R3P0 0x5 77#define L210_CACHE_ID_RTL_R0P3 0x03
77#define L2X0_CACHE_ID_RTL_R3P1 0x6 78#define L210_CACHE_ID_RTL_R0P4 0x0b
78#define L2X0_CACHE_ID_RTL_R3P2 0x8 79#define L210_CACHE_ID_RTL_R0P5 0x0f
80#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06
81#define L310_CACHE_ID_RTL_R0P0 0x00
82#define L310_CACHE_ID_RTL_R1P0 0x02
83#define L310_CACHE_ID_RTL_R2P0 0x04
84#define L310_CACHE_ID_RTL_R3P0 0x05
85#define L310_CACHE_ID_RTL_R3P1 0x06
86#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07
87#define L310_CACHE_ID_RTL_R3P2 0x08
88#define L310_CACHE_ID_RTL_R3P3 0x09
79 89
80#define L2X0_AUX_CTRL_MASK 0xc0000fff 90#define L2X0_AUX_CTRL_MASK 0xc0000fff
81#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 91#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0