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authorLinus Torvalds <torvalds@linux-foundation.org>2013-09-09 19:35:29 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-09-09 19:35:29 -0400
commit640414171818c6293c23e74a28d1c69b2a1a7fe5 (patch)
treecb3b10578f0ae39eac2930ce3b2c8a1616f5ba70 /arch/arm/boot
parentfa91515cbf2375a64c8bd0a033a05b0859dff591 (diff)
parenta2bdc32a527e817fdfa6c56eaa6c70f217da6c6c (diff)
Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Kevin Hilman: "These are changes that arrived a little late before the merge window, or had dependencies on previous branches. Highlights: - ux500: misc. cleanup, fixup I2C devices - exynos: DT updates for RTC; PM updates - at91: DT updates for NAND; new platforms added to generic defconfig - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks - highbank: LPAE fixes, select necessary ARM errata - omap: PM fixes and improvements; OMAP5 mailbox support - omap: basic support for new DRA7xx SoCs" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits) ARM: dts: vexpress: Add CCI node to TC2 device-tree ARM: EXYNOS: Skip C1 cpuidle state for exynos5440 ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 ARM: highbank: clean-up some unused includes ARM: sun7i: Enable the A20 clocks in the DTSI ARM: sun6i: Enable clock support in the DTSI ARM: sun5i: dt: Use the A10s gates in the DTSI ARM: at91: at91_dt_defconfig: enable rm9200 support ARM: dts: add ADC device tree node for exynos5420/5250 ARM: dts: Add RTC DT node to Exynos5420 SoC ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC ARM: dts: Fix the RTC DT node name for Exynos5250 irqchip: mmp: avoid to include irqs head file ARM: mmp: avoid to include head file in mach-mmp irqchip: mmp: support irqchip irqchip: move mmp irq driver ARM: OMAP: AM33xx: clock: Add RNG clock data ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX ARM: OMAP4: clock: Lock PLLs in the right sequence ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS ...
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/exynos5.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi14
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi17
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi19
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi2
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi36
-rw-r--r--arch/arm/boot/dts/sun6i-a31-colombus.dts2
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi161
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts53
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts27
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi157
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts25
15 files changed, 467 insertions, 57 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e02f1b6c8a2..cc0f1fb61753 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -231,6 +231,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
231 sun5i-a10s-olinuxino-micro.dtb \ 231 sun5i-a10s-olinuxino-micro.dtb \
232 sun5i-a13-olinuxino.dtb \ 232 sun5i-a13-olinuxino.dtb \
233 sun6i-a31-colombus.dtb \ 233 sun6i-a31-colombus.dtb \
234 sun7i-a20-cubieboard2.dtb \
234 sun7i-a20-olinuxino-micro.dtb 235 sun7i-a20-olinuxino-micro.dtb
235dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 236dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
236 tegra20-iris-512.dtb \ 237 tegra20-iris-512.dtb \
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 6afa57d2fecc..074739d39e2d 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -95,7 +95,7 @@
95 interrupts = <0 54 0>; 95 interrupts = <0 54 0>;
96 }; 96 };
97 97
98 rtc { 98 rtc@101E0000 {
99 compatible = "samsung,s3c6410-rtc"; 99 compatible = "samsung,s3c6410-rtc";
100 reg = <0x101E0000 0x100>; 100 reg = <0x101E0000 0x100>;
101 interrupts = <0 43 0>, <0 44 0>; 101 interrupts = <0 43 0>, <0 44 0>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 452d0b04d273..cee55fa33731 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -538,10 +538,6 @@
538 }; 538 };
539 }; 539 };
540 540
541 rtc {
542 status = "okay";
543 };
544
545 usb_hub_bus { 541 usb_hub_bus {
546 compatible = "simple-bus"; 542 compatible = "simple-bus";
547 #address-cells = <1>; 543 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index e79331dba12d..fd711e245e8d 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -171,10 +171,6 @@
171 }; 171 };
172 }; 172 };
173 173
174 rtc {
175 status = "okay";
176 };
177
178 /* 174 /*
179 * On Snow we've got SIP WiFi and so can keep drive strengths low to 175 * On Snow we've got SIP WiFi and so can keep drive strengths low to
180 * reduce EMI. 176 * reduce EMI.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index f7e2d3493f82..7d7cc777ff7b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -180,9 +180,10 @@
180 clock-names = "mfc"; 180 clock-names = "mfc";
181 }; 181 };
182 182
183 rtc { 183 rtc@101E0000 {
184 clocks = <&clock 337>; 184 clocks = <&clock 337>;
185 clock-names = "rtc"; 185 clock-names = "rtc";
186 status = "okay";
186 }; 187 };
187 188
188 tmu@10060000 { 189 tmu@10060000 {
@@ -638,4 +639,15 @@
638 clocks = <&clock 133>, <&clock 339>; 639 clocks = <&clock 133>, <&clock 339>;
639 clock-names = "sclk_fimd", "fimd"; 640 clock-names = "sclk_fimd", "fimd";
640 }; 641 };
642
643 adc: adc@12D10000 {
644 compatible = "samsung,exynos-adc-v1";
645 reg = <0x12D10000 0x100>, <0x10040718 0x4>;
646 interrupts = <0 106 0>;
647 clocks = <&clock 303>;
648 clock-names = "adc";
649 #io-channel-cells = <1>;
650 io-channel-ranges;
651 status = "disabled";
652 };
641}; 653};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5353e32897a4..d537cd704e19 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -180,6 +180,12 @@
180 interrupts = <0 47 0>; 180 interrupts = <0 47 0>;
181 }; 181 };
182 182
183 rtc@101E0000 {
184 clocks = <&clock 317>;
185 clock-names = "rtc";
186 status = "okay";
187 };
188
183 serial@12C00000 { 189 serial@12C00000 {
184 clocks = <&clock 257>, <&clock 128>; 190 clocks = <&clock 257>, <&clock 128>;
185 clock-names = "uart", "clk_uart_baud0"; 191 clock-names = "uart", "clk_uart_baud0";
@@ -218,4 +224,15 @@
218 clocks = <&clock 147>, <&clock 421>; 224 clocks = <&clock 147>, <&clock 421>;
219 clock-names = "sclk_fimd", "fimd"; 225 clock-names = "sclk_fimd", "fimd";
220 }; 226 };
227
228 adc: adc@12D10000 {
229 compatible = "samsung,exynos-adc-v2";
230 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
231 interrupts = <0 106 0>;
232 clocks = <&clock 270>;
233 clock-names = "adc";
234 #io-channel-cells = <1>;
235 io-channel-ranges;
236 status = "disabled";
237 };
221}; 238};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index ff63fbbd18ab..b7f49615120d 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1034,21 +1034,30 @@
1034 compatible = "atmel,at91rm9200-nand"; 1034 compatible = "atmel,at91rm9200-nand";
1035 #address-cells = <1>; 1035 #address-cells = <1>;
1036 #size-cells = <1>; 1036 #size-cells = <1>;
1037 ranges;
1037 reg = < 0x60000000 0x01000000 /* EBI CS3 */ 1038 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1038 0xffffc070 0x00000490 /* SMC PMECC regs */ 1039 0xffffc070 0x00000490 /* SMC PMECC regs */
1039 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ 1040 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1040 0x00100000 0x00100000 /* ROM code */ 1041 0x00110000 0x00018000 /* ROM code */
1041 0x70000000 0x10000000 /* NFC Command Registers */
1042 0xffffc000 0x00000070 /* NFC HSMC regs */
1043 0x00200000 0x00100000 /* NFC SRAM banks */
1044 >; 1042 >;
1045 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; 1043 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1046 atmel,nand-addr-offset = <21>; 1044 atmel,nand-addr-offset = <21>;
1047 atmel,nand-cmd-offset = <22>; 1045 atmel,nand-cmd-offset = <22>;
1048 pinctrl-names = "default"; 1046 pinctrl-names = "default";
1049 pinctrl-0 = <&pinctrl_nand0_ale_cle>; 1047 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1050 atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; 1048 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1051 status = "disabled"; 1049 status = "disabled";
1050
1051 nfc@70000000 {
1052 compatible = "atmel,sama5d3-nfc";
1053 #address-cells = <1>;
1054 #size-cells = <1>;
1055 reg = <
1056 0x70000000 0x10000000 /* NFC Command Registers */
1057 0xffffc000 0x00000070 /* NFC HSMC regs */
1058 0x00200000 0x00100000 /* NFC SRAM banks */
1059 >;
1060 };
1052 }; 1061 };
1053 }; 1062 };
1054}; 1063};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 1f8050813a54..31ed9e3bb649 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -47,8 +47,6 @@
47 atmel,has-pmecc; 47 atmel,has-pmecc;
48 atmel,pmecc-cap = <4>; 48 atmel,pmecc-cap = <4>;
49 atmel,pmecc-sector-size = <512>; 49 atmel,pmecc-sector-size = <512>;
50 atmel,has-nfc;
51 atmel,use-nfc-sram;
52 nand-on-flash-bbt; 50 nand-on-flash-bbt;
53 status = "okay"; 51 status = "okay";
54 52
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ee0ff9ba1bca..3b4a0574f068 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -95,20 +95,16 @@
95 95
96 ahb_gates: ahb_gates@01c20060 { 96 ahb_gates: ahb_gates@01c20060 {
97 #clock-cells = <1>; 97 #clock-cells = <1>;
98 compatible = "allwinner,sun4i-ahb-gates-clk"; 98 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
99 reg = <0x01c20060 0x8>; 99 reg = <0x01c20060 0x8>;
100 clocks = <&ahb>; 100 clocks = <&ahb>;
101 clock-output-names = "ahb_usb0", "ahb_ehci0", 101 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
102 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", 102 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
103 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", 103 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
104 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", 104 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
105 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", 105 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
106 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", 106 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
107 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", 107 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
108 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
109 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
110 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
111 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
112 }; 108 };
113 109
114 apb0: apb0@01c20054 { 110 apb0: apb0@01c20054 {
@@ -120,12 +116,11 @@
120 116
121 apb0_gates: apb0_gates@01c20068 { 117 apb0_gates: apb0_gates@01c20068 {
122 #clock-cells = <1>; 118 #clock-cells = <1>;
123 compatible = "allwinner,sun4i-apb0-gates-clk"; 119 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
124 reg = <0x01c20068 0x4>; 120 reg = <0x01c20068 0x4>;
125 clocks = <&apb0>; 121 clocks = <&apb0>;
126 clock-output-names = "apb0_codec", "apb0_spdif", 122 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
127 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", 123 "apb0_ir", "apb0_keypad";
128 "apb0_ir1", "apb0_keypad";
129 }; 124 };
130 125
131 /* dummy is pll62 */ 126 /* dummy is pll62 */
@@ -145,15 +140,12 @@
145 140
146 apb1_gates: apb1_gates@01c2006c { 141 apb1_gates: apb1_gates@01c2006c {
147 #clock-cells = <1>; 142 #clock-cells = <1>;
148 compatible = "allwinner,sun4i-apb1-gates-clk"; 143 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
149 reg = <0x01c2006c 0x4>; 144 reg = <0x01c2006c 0x4>;
150 clocks = <&apb1>; 145 clocks = <&apb1>;
151 clock-output-names = "apb1_i2c0", "apb1_i2c1", 146 clock-output-names = "apb1_i2c0", "apb1_i2c1",
152 "apb1_i2c2", "apb1_can", "apb1_scr", 147 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
153 "apb1_ps20", "apb1_ps21", "apb1_uart0", 148 "apb1_uart2", "apb1_uart3";
154 "apb1_uart1", "apb1_uart2", "apb1_uart3",
155 "apb1_uart4", "apb1_uart5", "apb1_uart6",
156 "apb1_uart7";
157 }; 149 };
158 }; 150 };
159 151
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 99c4b1847cab..e5adae30899b 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -24,6 +24,8 @@
24 24
25 soc@01c00000 { 25 soc@01c00000 {
26 uart0: serial@01c28000 { 26 uart0: serial@01c28000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pins_a>;
27 status = "okay"; 29 status = "okay";
28 }; 30 };
29 }; 31 };
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 4d076ec24885..f244f5f02365 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -51,13 +51,137 @@
51 51
52 clocks { 52 clocks {
53 #address-cells = <1>; 53 #address-cells = <1>;
54 #size-cells = <0>; 54 #size-cells = <1>;
55 ranges;
55 56
56 osc: oscillator { 57 osc24M: osc24M {
57 #clock-cells = <0>; 58 #clock-cells = <0>;
58 compatible = "fixed-clock"; 59 compatible = "fixed-clock";
59 clock-frequency = <24000000>; 60 clock-frequency = <24000000>;
60 }; 61 };
62
63 osc32k: osc32k {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 };
68
69 pll1: pll1@01c20000 {
70 #clock-cells = <0>;
71 compatible = "allwinner,sun6i-a31-pll1-clk";
72 reg = <0x01c20000 0x4>;
73 clocks = <&osc24M>;
74 };
75
76 /*
77 * This is a dummy clock, to be used as placeholder on
78 * other mux clocks when a specific parent clock is not
79 * yet implemented. It should be dropped when the driver
80 * is complete.
81 */
82 pll6: pll6 {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-frequency = <0>;
86 };
87
88 cpu: cpu@01c20050 {
89 #clock-cells = <0>;
90 compatible = "allwinner,sun4i-cpu-clk";
91 reg = <0x01c20050 0x4>;
92
93 /*
94 * PLL1 is listed twice here.
95 * While it looks suspicious, it's actually documented
96 * that way both in the datasheet and in the code from
97 * Allwinner.
98 */
99 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
100 };
101
102 axi: axi@01c20050 {
103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-axi-clk";
105 reg = <0x01c20050 0x4>;
106 clocks = <&cpu>;
107 };
108
109 ahb1_mux: ahb1_mux@01c20054 {
110 #clock-cells = <0>;
111 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
114 };
115
116 ahb1: ahb1@01c20054 {
117 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk";
119 reg = <0x01c20054 0x4>;
120 clocks = <&ahb1_mux>;
121 };
122
123 ahb1_gates: ahb1_gates@01c20060 {
124 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
126 reg = <0x01c20060 0x8>;
127 clocks = <&ahb1>;
128 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
129 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
130 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
131 "ahb1_nand0", "ahb1_sdram",
132 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
133 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
134 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
135 "ahb1_ehci1", "ahb1_ohci0",
136 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
137 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
138 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
139 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
140 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
141 "ahb1_drc0", "ahb1_drc1";
142 };
143
144 apb1: apb1@01c20054 {
145 #clock-cells = <0>;
146 compatible = "allwinner,sun4i-apb0-clk";
147 reg = <0x01c20054 0x4>;
148 clocks = <&ahb1>;
149 };
150
151 apb1_gates: apb1_gates@01c20060 {
152 #clock-cells = <1>;
153 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
154 reg = <0x01c20068 0x4>;
155 clocks = <&apb1>;
156 clock-output-names = "apb1_codec", "apb1_digital_mic",
157 "apb1_pio", "apb1_daudio0",
158 "apb1_daudio1";
159 };
160
161 apb2_mux: apb2_mux@01c20058 {
162 #clock-cells = <0>;
163 compatible = "allwinner,sun4i-apb1-mux-clk";
164 reg = <0x01c20058 0x4>;
165 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
166 };
167
168 apb2: apb2@01c20058 {
169 #clock-cells = <0>;
170 compatible = "allwinner,sun6i-a31-apb2-div-clk";
171 reg = <0x01c20058 0x4>;
172 clocks = <&apb2_mux>;
173 };
174
175 apb2_gates: apb2_gates@01c2006c {
176 #clock-cells = <1>;
177 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
178 reg = <0x01c2006c 0x8>;
179 clocks = <&apb2>;
180 clock-output-names = "apb2_i2c0", "apb2_i2c1",
181 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
182 "apb2_uart1", "apb2_uart2", "apb2_uart3",
183 "apb2_uart4", "apb2_uart5";
184 };
61 }; 185 };
62 186
63 soc@01c00000 { 187 soc@01c00000 {
@@ -66,6 +190,25 @@
66 #size-cells = <1>; 190 #size-cells = <1>;
67 ranges; 191 ranges;
68 192
193 pio: pinctrl@01c20800 {
194 compatible = "allwinner,sun6i-a31-pinctrl";
195 reg = <0x01c20800 0x400>;
196 interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
197 clocks = <&apb1_gates 5>;
198 gpio-controller;
199 interrupt-controller;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 #gpio-cells = <3>;
203
204 uart0_pins_a: uart0@0 {
205 allwinner,pins = "PH20", "PH21";
206 allwinner,function = "uart0";
207 allwinner,drive = <0>;
208 allwinner,pull = <0>;
209 };
210 };
211
69 timer@01c20c00 { 212 timer@01c20c00 {
70 compatible = "allwinner,sun4i-timer"; 213 compatible = "allwinner,sun4i-timer";
71 reg = <0x01c20c00 0xa0>; 214 reg = <0x01c20c00 0xa0>;
@@ -74,7 +217,7 @@
74 <0 20 1>, 217 <0 20 1>,
75 <0 21 1>, 218 <0 21 1>,
76 <0 22 1>; 219 <0 22 1>;
77 clocks = <&osc>; 220 clocks = <&osc24M>;
78 }; 221 };
79 222
80 wdt1: watchdog@01c20ca0 { 223 wdt1: watchdog@01c20ca0 {
@@ -88,7 +231,7 @@
88 interrupts = <0 0 1>; 231 interrupts = <0 0 1>;
89 reg-shift = <2>; 232 reg-shift = <2>;
90 reg-io-width = <4>; 233 reg-io-width = <4>;
91 clocks = <&osc>; 234 clocks = <&apb2_gates 16>;
92 status = "disabled"; 235 status = "disabled";
93 }; 236 };
94 237
@@ -98,7 +241,7 @@
98 interrupts = <0 1 1>; 241 interrupts = <0 1 1>;
99 reg-shift = <2>; 242 reg-shift = <2>;
100 reg-io-width = <4>; 243 reg-io-width = <4>;
101 clocks = <&osc>; 244 clocks = <&apb2_gates 17>;
102 status = "disabled"; 245 status = "disabled";
103 }; 246 };
104 247
@@ -108,7 +251,7 @@
108 interrupts = <0 2 1>; 251 interrupts = <0 2 1>;
109 reg-shift = <2>; 252 reg-shift = <2>;
110 reg-io-width = <4>; 253 reg-io-width = <4>;
111 clocks = <&osc>; 254 clocks = <&apb2_gates 18>;
112 status = "disabled"; 255 status = "disabled";
113 }; 256 };
114 257
@@ -118,7 +261,7 @@
118 interrupts = <0 3 1>; 261 interrupts = <0 3 1>;
119 reg-shift = <2>; 262 reg-shift = <2>;
120 reg-io-width = <4>; 263 reg-io-width = <4>;
121 clocks = <&osc>; 264 clocks = <&apb2_gates 19>;
122 status = "disabled"; 265 status = "disabled";
123 }; 266 };
124 267
@@ -128,7 +271,7 @@
128 interrupts = <0 4 1>; 271 interrupts = <0 4 1>;
129 reg-shift = <2>; 272 reg-shift = <2>;
130 reg-io-width = <4>; 273 reg-io-width = <4>;
131 clocks = <&osc>; 274 clocks = <&apb2_gates 20>;
132 status = "disabled"; 275 status = "disabled";
133 }; 276 };
134 277
@@ -138,7 +281,7 @@
138 interrupts = <0 5 1>; 281 interrupts = <0 5 1>;
139 reg-shift = <2>; 282 reg-shift = <2>;
140 reg-io-width = <4>; 283 reg-io-width = <4>;
141 clocks = <&osc>; 284 clocks = <&apb2_gates 21>;
142 status = "disabled"; 285 status = "disabled";
143 }; 286 };
144 287
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
new file mode 100644
index 000000000000..31b76f08b3ad
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -0,0 +1,53 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun7i-a20.dtsi"
16
17/ {
18 model = "Cubietech Cubieboard2";
19 compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
20
21 soc@01c00000 {
22 pinctrl@01c20800 {
23 led_pins_cubieboard2: led_pins@0 {
24 allwinner,pins = "PH20", "PH21";
25 allwinner,function = "gpio_out";
26 allwinner,drive = <0>;
27 allwinner,pull = <0>;
28 };
29 };
30
31 uart0: serial@01c28000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&uart0_pins_a>;
34 status = "okay";
35 };
36 };
37
38 leds {
39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&led_pins_cubieboard2>;
42
43 blue {
44 label = "cubieboard2:blue:usr";
45 gpios = <&pio 7 21 0>;
46 };
47
48 green {
49 label = "cubieboard2:green:usr";
50 gpios = <&pio 7 20 0>;
51 };
52 };
53};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index d3395846491c..34a6c02a7c72 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -19,16 +19,43 @@
19 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; 19 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
20 20
21 soc@01c00000 { 21 soc@01c00000 {
22 pinctrl@01c20800 {
23 led_pins_olinuxino: led_pins@0 {
24 allwinner,pins = "PH2";
25 allwinner,function = "gpio_out";
26 allwinner,drive = <1>;
27 allwinner,pull = <0>;
28 };
29 };
30
22 uart0: serial@01c28000 { 31 uart0: serial@01c28000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&uart0_pins_a>;
23 status = "okay"; 34 status = "okay";
24 }; 35 };
25 36
26 uart6: serial@01c29800 { 37 uart6: serial@01c29800 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&uart6_pins_a>;
27 status = "okay"; 40 status = "okay";
28 }; 41 };
29 42
30 uart7: serial@01c29c00 { 43 uart7: serial@01c29c00 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&uart7_pins_a>;
31 status = "okay"; 46 status = "okay";
32 }; 47 };
33 }; 48 };
49
50 leds {
51 compatible = "gpio-leds";
52 pinctrl-names = "default";
53 pinctrl-0 = <&led_pins_olinuxino>;
54
55 green {
56 label = "a20-olinuxino-micro:green:usr";
57 gpios = <&pio 7 2 0>;
58 default-state = "on";
59 };
60 };
34}; 61};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 33391517118c..999ff45cb77e 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -44,7 +44,8 @@
44 44
45 osc24M: osc24M@01c20050 { 45 osc24M: osc24M@01c20050 {
46 #clock-cells = <0>; 46 #clock-cells = <0>;
47 compatible = "fixed-clock"; 47 compatible = "allwinner,sun4i-osc-clk";
48 reg = <0x01c20050 0x4>;
48 clock-frequency = <24000000>; 49 clock-frequency = <24000000>;
49 }; 50 };
50 51
@@ -53,6 +54,111 @@
53 compatible = "fixed-clock"; 54 compatible = "fixed-clock";
54 clock-frequency = <32768>; 55 clock-frequency = <32768>;
55 }; 56 };
57
58 pll1: pll1@01c20000 {
59 #clock-cells = <0>;
60 compatible = "allwinner,sun4i-pll1-clk";
61 reg = <0x01c20000 0x4>;
62 clocks = <&osc24M>;
63 };
64
65 /*
66 * This is a dummy clock, to be used as placeholder on
67 * other mux clocks when a specific parent clock is not
68 * yet implemented. It should be dropped when the driver
69 * is complete.
70 */
71 pll6: pll6 {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
75 };
76
77 cpu: cpu@01c20054 {
78 #clock-cells = <0>;
79 compatible = "allwinner,sun4i-cpu-clk";
80 reg = <0x01c20054 0x4>;
81 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
82 };
83
84 axi: axi@01c20054 {
85 #clock-cells = <0>;
86 compatible = "allwinner,sun4i-axi-clk";
87 reg = <0x01c20054 0x4>;
88 clocks = <&cpu>;
89 };
90
91 ahb: ahb@01c20054 {
92 #clock-cells = <0>;
93 compatible = "allwinner,sun4i-ahb-clk";
94 reg = <0x01c20054 0x4>;
95 clocks = <&axi>;
96 };
97
98 ahb_gates: ahb_gates@01c20060 {
99 #clock-cells = <1>;
100 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
101 reg = <0x01c20060 0x8>;
102 clocks = <&ahb>;
103 clock-output-names = "ahb_usb0", "ahb_ehci0",
104 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
105 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
106 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
107 "ahb_nand", "ahb_sdram", "ahb_ace",
108 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
109 "ahb_spi2", "ahb_spi3", "ahb_sata",
110 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
111 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
112 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
113 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
114 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
115 "ahb_mali";
116 };
117
118 apb0: apb0@01c20054 {
119 #clock-cells = <0>;
120 compatible = "allwinner,sun4i-apb0-clk";
121 reg = <0x01c20054 0x4>;
122 clocks = <&ahb>;
123 };
124
125 apb0_gates: apb0_gates@01c20068 {
126 #clock-cells = <1>;
127 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
128 reg = <0x01c20068 0x4>;
129 clocks = <&apb0>;
130 clock-output-names = "apb0_codec", "apb0_spdif",
131 "apb0_ac97", "apb0_iis0", "apb0_iis1",
132 "apb0_pio", "apb0_ir0", "apb0_ir1",
133 "apb0_iis2", "apb0_keypad";
134 };
135
136 apb1_mux: apb1_mux@01c20058 {
137 #clock-cells = <0>;
138 compatible = "allwinner,sun4i-apb1-mux-clk";
139 reg = <0x01c20058 0x4>;
140 clocks = <&osc24M>, <&pll6>, <&osc32k>;
141 };
142
143 apb1: apb1@01c20058 {
144 #clock-cells = <0>;
145 compatible = "allwinner,sun4i-apb1-clk";
146 reg = <0x01c20058 0x4>;
147 clocks = <&apb1_mux>;
148 };
149
150 apb1_gates: apb1_gates@01c2006c {
151 #clock-cells = <1>;
152 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
153 reg = <0x01c2006c 0x4>;
154 clocks = <&apb1>;
155 clock-output-names = "apb1_i2c0", "apb1_i2c1",
156 "apb1_i2c2", "apb1_i2c3", "apb1_can",
157 "apb1_scr", "apb1_ps20", "apb1_ps21",
158 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
159 "apb1_uart2", "apb1_uart3", "apb1_uart4",
160 "apb1_uart5", "apb1_uart6", "apb1_uart7";
161 };
56 }; 162 };
57 163
58 soc@01c00000 { 164 soc@01c00000 {
@@ -61,6 +167,39 @@
61 #size-cells = <1>; 167 #size-cells = <1>;
62 ranges; 168 ranges;
63 169
170 pio: pinctrl@01c20800 {
171 compatible = "allwinner,sun7i-a20-pinctrl";
172 reg = <0x01c20800 0x400>;
173 interrupts = <0 28 1>;
174 clocks = <&apb0_gates 5>;
175 gpio-controller;
176 interrupt-controller;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 #gpio-cells = <3>;
180
181 uart0_pins_a: uart0@0 {
182 allwinner,pins = "PB22", "PB23";
183 allwinner,function = "uart0";
184 allwinner,drive = <0>;
185 allwinner,pull = <0>;
186 };
187
188 uart6_pins_a: uart6@0 {
189 allwinner,pins = "PI12", "PI13";
190 allwinner,function = "uart6";
191 allwinner,drive = <0>;
192 allwinner,pull = <0>;
193 };
194
195 uart7_pins_a: uart7@0 {
196 allwinner,pins = "PI20", "PI21";
197 allwinner,function = "uart7";
198 allwinner,drive = <0>;
199 allwinner,pull = <0>;
200 };
201 };
202
64 timer@01c20c00 { 203 timer@01c20c00 {
65 compatible = "allwinner,sun4i-timer"; 204 compatible = "allwinner,sun4i-timer";
66 reg = <0x01c20c00 0x90>; 205 reg = <0x01c20c00 0x90>;
@@ -84,7 +223,7 @@
84 interrupts = <0 1 1>; 223 interrupts = <0 1 1>;
85 reg-shift = <2>; 224 reg-shift = <2>;
86 reg-io-width = <4>; 225 reg-io-width = <4>;
87 clocks = <&osc24M>; 226 clocks = <&apb1_gates 16>;
88 status = "disabled"; 227 status = "disabled";
89 }; 228 };
90 229
@@ -94,7 +233,7 @@
94 interrupts = <0 2 1>; 233 interrupts = <0 2 1>;
95 reg-shift = <2>; 234 reg-shift = <2>;
96 reg-io-width = <4>; 235 reg-io-width = <4>;
97 clocks = <&osc24M>; 236 clocks = <&apb1_gates 17>;
98 status = "disabled"; 237 status = "disabled";
99 }; 238 };
100 239
@@ -104,7 +243,7 @@
104 interrupts = <0 3 1>; 243 interrupts = <0 3 1>;
105 reg-shift = <2>; 244 reg-shift = <2>;
106 reg-io-width = <4>; 245 reg-io-width = <4>;
107 clocks = <&osc24M>; 246 clocks = <&apb1_gates 18>;
108 status = "disabled"; 247 status = "disabled";
109 }; 248 };
110 249
@@ -114,7 +253,7 @@
114 interrupts = <0 4 1>; 253 interrupts = <0 4 1>;
115 reg-shift = <2>; 254 reg-shift = <2>;
116 reg-io-width = <4>; 255 reg-io-width = <4>;
117 clocks = <&osc24M>; 256 clocks = <&apb1_gates 19>;
118 status = "disabled"; 257 status = "disabled";
119 }; 258 };
120 259
@@ -124,7 +263,7 @@
124 interrupts = <0 17 1>; 263 interrupts = <0 17 1>;
125 reg-shift = <2>; 264 reg-shift = <2>;
126 reg-io-width = <4>; 265 reg-io-width = <4>;
127 clocks = <&osc24M>; 266 clocks = <&apb1_gates 20>;
128 status = "disabled"; 267 status = "disabled";
129 }; 268 };
130 269
@@ -134,7 +273,7 @@
134 interrupts = <0 18 1>; 273 interrupts = <0 18 1>;
135 reg-shift = <2>; 274 reg-shift = <2>;
136 reg-io-width = <4>; 275 reg-io-width = <4>;
137 clocks = <&osc24M>; 276 clocks = <&apb1_gates 21>;
138 status = "disabled"; 277 status = "disabled";
139 }; 278 };
140 279
@@ -144,7 +283,7 @@
144 interrupts = <0 19 1>; 283 interrupts = <0 19 1>;
145 reg-shift = <2>; 284 reg-shift = <2>;
146 reg-io-width = <4>; 285 reg-io-width = <4>;
147 clocks = <&osc24M>; 286 clocks = <&apb1_gates 22>;
148 status = "disabled"; 287 status = "disabled";
149 }; 288 };
150 289
@@ -154,7 +293,7 @@
154 interrupts = <0 20 1>; 293 interrupts = <0 20 1>;
155 reg-shift = <2>; 294 reg-shift = <2>;
156 reg-io-width = <4>; 295 reg-io-width = <4>;
157 clocks = <&osc24M>; 296 clocks = <&apb1_gates 23>;
158 status = "disabled"; 297 status = "disabled";
159 }; 298 };
160 299
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 759b0cd20013..15f98cbcb75a 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -37,30 +37,35 @@
37 device_type = "cpu"; 37 device_type = "cpu";
38 compatible = "arm,cortex-a15"; 38 compatible = "arm,cortex-a15";
39 reg = <0>; 39 reg = <0>;
40 cci-control-port = <&cci_control1>;
40 }; 41 };
41 42
42 cpu1: cpu@1 { 43 cpu1: cpu@1 {
43 device_type = "cpu"; 44 device_type = "cpu";
44 compatible = "arm,cortex-a15"; 45 compatible = "arm,cortex-a15";
45 reg = <1>; 46 reg = <1>;
47 cci-control-port = <&cci_control1>;
46 }; 48 };
47 49
48 cpu2: cpu@2 { 50 cpu2: cpu@2 {
49 device_type = "cpu"; 51 device_type = "cpu";
50 compatible = "arm,cortex-a7"; 52 compatible = "arm,cortex-a7";
51 reg = <0x100>; 53 reg = <0x100>;
54 cci-control-port = <&cci_control2>;
52 }; 55 };
53 56
54 cpu3: cpu@3 { 57 cpu3: cpu@3 {
55 device_type = "cpu"; 58 device_type = "cpu";
56 compatible = "arm,cortex-a7"; 59 compatible = "arm,cortex-a7";
57 reg = <0x101>; 60 reg = <0x101>;
61 cci-control-port = <&cci_control2>;
58 }; 62 };
59 63
60 cpu4: cpu@4 { 64 cpu4: cpu@4 {
61 device_type = "cpu"; 65 device_type = "cpu";
62 compatible = "arm,cortex-a7"; 66 compatible = "arm,cortex-a7";
63 reg = <0x102>; 67 reg = <0x102>;
68 cci-control-port = <&cci_control2>;
64 }; 69 };
65 }; 70 };
66 71
@@ -104,6 +109,26 @@
104 interrupts = <1 9 0xf04>; 109 interrupts = <1 9 0xf04>;
105 }; 110 };
106 111
112 cci@2c090000 {
113 compatible = "arm,cci-400";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 reg = <0 0x2c090000 0 0x1000>;
117 ranges = <0x0 0x0 0x2c090000 0x10000>;
118
119 cci_control1: slave-if@4000 {
120 compatible = "arm,cci-400-ctrl-if";
121 interface-type = "ace";
122 reg = <0x4000 0x1000>;
123 };
124
125 cci_control2: slave-if@5000 {
126 compatible = "arm,cci-400-ctrl-if";
127 interface-type = "ace";
128 reg = <0x5000 0x1000>;
129 };
130 };
131
107 memory-controller@7ffd0000 { 132 memory-controller@7ffd0000 {
108 compatible = "arm,pl354", "arm,primecell"; 133 compatible = "arm,pl354", "arm,primecell";
109 reg = <0 0x7ffd0000 0 0x1000>; 134 reg = <0 0x7ffd0000 0 0x1000>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 13:31:30 -0500