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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-07 14:06:17 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-07 14:06:17 -0400
commit38f56f33ca381751f9b8910f67e7a805ec0b68cb (patch)
tree202f2ce60f3f43a948607ec76c8cc48c1cf73a4b /arch/arm/boot
parentfcba914542082b272f31c8e4c40000b88ed3208d (diff)
parent4183bef2e093a2f0aab45f2d5fed82b0e02aeacf (diff)
Merge tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree updates (part 2) from Arnd Bergmann: "These are mostly new device tree bindings for existing drivers, as well as changes to the device tree source files to add support for those devices, and a couple of new boards, most notably Samsung's Exynos5 based Chromebook. The changes depend on earlier platform specific updates and touch the usual platforms: omap, exynos, tegra, mxs, mvebu and davinci." * tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits) ARM: exynos: dts: cros5250: add EC device ARM: dts: Add sbs-battery for exynos5250-snow ARM: dts: Add i2c-arbitrator bus for exynos5250-snow ARM: dts: add mshc controller node for Exynos4x12 SoCs ARM: dts: Add chip-id controller node on Exynos4/5 SoC ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree ARM: davinci: da850-evm: add SPI flash support ARM: davinci: da850: override SPI DT node device name ARM: davinci: da850: add SPI1 DT node spi/davinci: add DT binding documentation spi/davinci: no wildcards in DT compatible property ARM: dts: mvebu: Convert mvebu device tree files to 64 bits ARM: dts: mvebu: introduce internal-regs node ARM: dts: mvebu: Convert all the mvebu files to use the range property ARM: dts: mvebu: move all peripherals inside soc ARM: dts: mvebu: fix cpus section indentation ARM: davinci: da850: add EHRPWM & ECAP DT node ARM/dts: OMAP3: fix pinctrl-single configuration ARM: dts: Add OMAP3430 SDP NOR flash memory binding ARM: dts: Add NOR flash bindings for OMAP2420 H4 ...
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/Makefile5
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts10
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts18
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts18
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi40
-rw-r--r--arch/arm/boot/dts/am3517-evm.dts2
-rw-r--r--arch/arm/boot/dts/am3517_mt_ventoux.dts2
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts134
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts176
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts96
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi336
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi330
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts202
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts222
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi284
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi342
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi484
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts262
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi202
-rw-r--r--arch/arm/boot/dts/cros5250-common.dtsi54
-rw-r--r--arch/arm/boot/dts/da850-evm.dts40
-rw-r--r--arch/arm/boot/dts/da850.dtsi94
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi32
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts4
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts57
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi7
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts21
-rw-r--r--arch/arm/boot/dts/exynos4412-smdk4412.dts8
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi8
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi7
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts343
-rw-r--r--arch/arm/boot/dts/exynos5250-pinctrl.dtsi783
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts49
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts149
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi348
-rw-r--r--arch/arm/boot/dts/exynos5440-sd5v1.dts39
-rw-r--r--arch/arm/boot/dts/exynos5440-ssdk5440.dts6
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi55
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts36
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts1
-rw-r--r--arch/arm/boot/dts/imx23.dtsi42
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts25
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts25
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts50
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts36
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts27
-rw-r--r--arch/arm/boot/dts/imx28.dtsi62
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi8
-rw-r--r--arch/arm/boot/dts/omap2.dtsi39
-rw-r--r--arch/arm/boot/dts/omap2420-h4.dts46
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi67
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi87
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts26
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts8
-rw-r--r--arch/arm/boot/dts/omap3-devkit8000.dts169
-rw-r--r--arch/arm/boot/dts/omap3-evm.dts14
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi122
-rw-r--r--arch/arm/boot/dts/omap3-igep0020.dts56
-rw-r--r--arch/arm/boot/dts/omap3-igep0030.dts44
-rw-r--r--arch/arm/boot/dts/omap3-overo.dtsi31
-rw-r--r--arch/arm/boot/dts/omap3.dtsi142
-rw-r--r--arch/arm/boot/dts/omap3430-sdp.dts190
-rw-r--r--arch/arm/boot/dts/omap34xx.dtsi28
-rw-r--r--arch/arm/boot/dts/omap36xx.dtsi13
-rw-r--r--arch/arm/boot/dts/omap4-panda-a4.dts5
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi251
-rw-r--r--arch/arm/boot/dts/omap4-panda-es.dts5
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts201
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts74
-rw-r--r--arch/arm/boot/dts/omap4-var-som.dts2
-rw-r--r--arch/arm/boot/dts/omap4.dtsi135
-rw-r--r--arch/arm/boot/dts/omap443x.dtsi27
-rw-r--r--arch/arm/boot/dts/omap4460.dtsi32
-rw-r--r--arch/arm/boot/dts/omap5-evm.dts110
-rw-r--r--arch/arm/boot/dts/omap5.dtsi245
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts891
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi240
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi12
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts20
-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts7
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts10
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts3
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts11
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi6
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts3
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts23
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts22
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts13
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi53
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts8
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a02.dts1
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a04.dts1
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi11
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi1
-rw-r--r--arch/arm/boot/dts/twl4030.dtsi18
-rw-r--r--arch/arm/boot/dts/twl6030.dtsi12
96 files changed, 6839 insertions, 2277 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 2ab88e91e65f..e6611eaa2885 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -53,6 +53,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
53 exynos4412-smdk4412.dtb \ 53 exynos4412-smdk4412.dtb \
54 exynos4412-origen.dtb \ 54 exynos4412-origen.dtb \
55 exynos5250-arndale.dtb \ 55 exynos5250-arndale.dtb \
56 exynos5440-sd5v1.dtb \
56 exynos5250-smdk5250.dtb \ 57 exynos5250-smdk5250.dtb \
57 exynos5250-snow.dtb \ 58 exynos5250-snow.dtb \
58 exynos5440-ssdk5440.dtb 59 exynos5440-ssdk5440.dtb
@@ -134,10 +135,14 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
134 imx28-tx28.dtb 135 imx28-tx28.dtb
135dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb 136dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
136dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ 137dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
138 omap3430-sdp.dtb \
137 omap3-beagle.dtb \ 139 omap3-beagle.dtb \
140 omap3-devkit8000.dtb \
138 omap3-beagle-xm.dtb \ 141 omap3-beagle-xm.dtb \
139 omap3-evm.dtb \ 142 omap3-evm.dtb \
140 omap3-tobi.dtb \ 143 omap3-tobi.dtb \
144 omap3-igep0020.dtb \
145 omap3-igep0030.dtb \
141 omap4-panda.dtb \ 146 omap4-panda.dtb \
142 omap4-panda-a4.dtb \ 147 omap4-panda-a4.dtb \
143 omap4-panda-es.dtb \ 148 omap4-panda-es.dtb \
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 11b240c5d323..5302f79c05b7 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -43,7 +43,7 @@
43 status = "okay"; 43 status = "okay";
44 }; 44 };
45 45
46 i2c1: i2c@44e0b000 { 46 i2c0: i2c@44e0b000 {
47 status = "okay"; 47 status = "okay";
48 clock-frequency = <400000>; 48 clock-frequency = <400000>;
49 49
@@ -59,27 +59,27 @@
59 59
60 led@2 { 60 led@2 {
61 label = "beaglebone:green:heartbeat"; 61 label = "beaglebone:green:heartbeat";
62 gpios = <&gpio2 21 0>; 62 gpios = <&gpio1 21 0>;
63 linux,default-trigger = "heartbeat"; 63 linux,default-trigger = "heartbeat";
64 default-state = "off"; 64 default-state = "off";
65 }; 65 };
66 66
67 led@3 { 67 led@3 {
68 label = "beaglebone:green:mmc0"; 68 label = "beaglebone:green:mmc0";
69 gpios = <&gpio2 22 0>; 69 gpios = <&gpio1 22 0>;
70 linux,default-trigger = "mmc0"; 70 linux,default-trigger = "mmc0";
71 default-state = "off"; 71 default-state = "off";
72 }; 72 };
73 73
74 led@4 { 74 led@4 {
75 label = "beaglebone:green:usr2"; 75 label = "beaglebone:green:usr2";
76 gpios = <&gpio2 23 0>; 76 gpios = <&gpio1 23 0>;
77 default-state = "off"; 77 default-state = "off";
78 }; 78 };
79 79
80 led@5 { 80 led@5 {
81 label = "beaglebone:green:usr3"; 81 label = "beaglebone:green:usr3";
82 gpios = <&gpio2 24 0>; 82 gpios = <&gpio1 24 0>;
83 default-state = "off"; 83 default-state = "off";
84 }; 84 };
85 }; 85 };
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d6496440fcea..0423298a26fe 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -51,7 +51,7 @@
51 status = "okay"; 51 status = "okay";
52 }; 52 };
53 53
54 i2c1: i2c@44e0b000 { 54 i2c0: i2c@44e0b000 {
55 status = "okay"; 55 status = "okay";
56 clock-frequency = <400000>; 56 clock-frequency = <400000>;
57 57
@@ -60,7 +60,7 @@
60 }; 60 };
61 }; 61 };
62 62
63 i2c2: i2c@4802a000 { 63 i2c1: i2c@4802a000 {
64 status = "okay"; 64 status = "okay";
65 clock-frequency = <100000>; 65 clock-frequency = <100000>;
66 66
@@ -123,12 +123,12 @@
123 debounce-delay-ms = <5>; 123 debounce-delay-ms = <5>;
124 col-scan-delay-us = <2>; 124 col-scan-delay-us = <2>;
125 125
126 row-gpios = <&gpio2 25 0 /* Bank1, pin25 */ 126 row-gpios = <&gpio1 25 0 /* Bank1, pin25 */
127 &gpio2 26 0 /* Bank1, pin26 */ 127 &gpio1 26 0 /* Bank1, pin26 */
128 &gpio2 27 0>; /* Bank1, pin27 */ 128 &gpio1 27 0>; /* Bank1, pin27 */
129 129
130 col-gpios = <&gpio2 21 0 /* Bank1, pin21 */ 130 col-gpios = <&gpio1 21 0 /* Bank1, pin21 */
131 &gpio2 22 0>; /* Bank1, pin22 */ 131 &gpio1 22 0>; /* Bank1, pin22 */
132 132
133 linux,keymap = <0x0000008b /* MENU */ 133 linux,keymap = <0x0000008b /* MENU */
134 0x0100009e /* BACK */ 134 0x0100009e /* BACK */
@@ -147,14 +147,14 @@
147 switch@9 { 147 switch@9 {
148 label = "volume-up"; 148 label = "volume-up";
149 linux,code = <115>; 149 linux,code = <115>;
150 gpios = <&gpio1 2 1>; 150 gpios = <&gpio0 2 1>;
151 gpio-key,wakeup; 151 gpio-key,wakeup;
152 }; 152 };
153 153
154 switch@10 { 154 switch@10 {
155 label = "volume-down"; 155 label = "volume-down";
156 linux,code = <114>; 156 linux,code = <114>;
157 gpios = <&gpio1 3 1>; 157 gpios = <&gpio0 3 1>;
158 gpio-key,wakeup; 158 gpio-key,wakeup;
159 }; 159 };
160 }; 160 };
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162a4ff2..f67c360844f4 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -58,7 +58,7 @@
58 status = "okay"; 58 status = "okay";
59 }; 59 };
60 60
61 i2c1: i2c@44e0b000 { 61 i2c0: i2c@44e0b000 {
62 status = "okay"; 62 status = "okay";
63 clock-frequency = <400000>; 63 clock-frequency = <400000>;
64 64
@@ -115,26 +115,26 @@
115 115
116 led@1 { 116 led@1 {
117 label = "evmsk:green:usr0"; 117 label = "evmsk:green:usr0";
118 gpios = <&gpio2 4 0>; 118 gpios = <&gpio1 4 0>;
119 default-state = "off"; 119 default-state = "off";
120 }; 120 };
121 121
122 led@2 { 122 led@2 {
123 label = "evmsk:green:usr1"; 123 label = "evmsk:green:usr1";
124 gpios = <&gpio2 5 0>; 124 gpios = <&gpio1 5 0>;
125 default-state = "off"; 125 default-state = "off";
126 }; 126 };
127 127
128 led@3 { 128 led@3 {
129 label = "evmsk:green:mmc0"; 129 label = "evmsk:green:mmc0";
130 gpios = <&gpio2 6 0>; 130 gpios = <&gpio1 6 0>;
131 linux,default-trigger = "mmc0"; 131 linux,default-trigger = "mmc0";
132 default-state = "off"; 132 default-state = "off";
133 }; 133 };
134 134
135 led@4 { 135 led@4 {
136 label = "evmsk:green:heartbeat"; 136 label = "evmsk:green:heartbeat";
137 gpios = <&gpio2 7 0>; 137 gpios = <&gpio1 7 0>;
138 linux,default-trigger = "heartbeat"; 138 linux,default-trigger = "heartbeat";
139 default-state = "off"; 139 default-state = "off";
140 }; 140 };
@@ -148,26 +148,26 @@
148 switch@1 { 148 switch@1 {
149 label = "button0"; 149 label = "button0";
150 linux,code = <0x100>; 150 linux,code = <0x100>;
151 gpios = <&gpio3 3 0>; 151 gpios = <&gpio2 3 0>;
152 }; 152 };
153 153
154 switch@2 { 154 switch@2 {
155 label = "button1"; 155 label = "button1";
156 linux,code = <0x101>; 156 linux,code = <0x101>;
157 gpios = <&gpio3 2 0>; 157 gpios = <&gpio2 2 0>;
158 }; 158 };
159 159
160 switch@3 { 160 switch@3 {
161 label = "button2"; 161 label = "button2";
162 linux,code = <0x102>; 162 linux,code = <0x102>;
163 gpios = <&gpio1 30 0>; 163 gpios = <&gpio0 30 0>;
164 gpio-key,wakeup; 164 gpio-key,wakeup;
165 }; 165 };
166 166
167 switch@4 { 167 switch@4 {
168 label = "button3"; 168 label = "button3";
169 linux,code = <0x103>; 169 linux,code = <0x103>;
170 gpios = <&gpio3 5 0>; 170 gpios = <&gpio2 5 0>;
171 }; 171 };
172 }; 172 };
173}; 173};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 91fe4f148f80..d1101103aa51 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -21,6 +21,8 @@
21 serial3 = &uart4; 21 serial3 = &uart4;
22 serial4 = &uart5; 22 serial4 = &uart5;
23 serial5 = &uart6; 23 serial5 = &uart6;
24 d_can0 = &dcan0;
25 d_can1 = &dcan1;
24 }; 26 };
25 27
26 cpus { 28 cpus {
@@ -87,7 +89,7 @@
87 reg = <0x48200000 0x1000>; 89 reg = <0x48200000 0x1000>;
88 }; 90 };
89 91
90 gpio1: gpio@44e07000 { 92 gpio0: gpio@44e07000 {
91 compatible = "ti,omap4-gpio"; 93 compatible = "ti,omap4-gpio";
92 ti,hwmods = "gpio1"; 94 ti,hwmods = "gpio1";
93 gpio-controller; 95 gpio-controller;
@@ -98,7 +100,7 @@
98 interrupts = <96>; 100 interrupts = <96>;
99 }; 101 };
100 102
101 gpio2: gpio@4804c000 { 103 gpio1: gpio@4804c000 {
102 compatible = "ti,omap4-gpio"; 104 compatible = "ti,omap4-gpio";
103 ti,hwmods = "gpio2"; 105 ti,hwmods = "gpio2";
104 gpio-controller; 106 gpio-controller;
@@ -109,7 +111,7 @@
109 interrupts = <98>; 111 interrupts = <98>;
110 }; 112 };
111 113
112 gpio3: gpio@481ac000 { 114 gpio2: gpio@481ac000 {
113 compatible = "ti,omap4-gpio"; 115 compatible = "ti,omap4-gpio";
114 ti,hwmods = "gpio3"; 116 ti,hwmods = "gpio3";
115 gpio-controller; 117 gpio-controller;
@@ -120,7 +122,7 @@
120 interrupts = <32>; 122 interrupts = <32>;
121 }; 123 };
122 124
123 gpio4: gpio@481ae000 { 125 gpio3: gpio@481ae000 {
124 compatible = "ti,omap4-gpio"; 126 compatible = "ti,omap4-gpio";
125 ti,hwmods = "gpio4"; 127 ti,hwmods = "gpio4";
126 gpio-controller; 128 gpio-controller;
@@ -185,7 +187,7 @@
185 status = "disabled"; 187 status = "disabled";
186 }; 188 };
187 189
188 i2c1: i2c@44e0b000 { 190 i2c0: i2c@44e0b000 {
189 compatible = "ti,omap4-i2c"; 191 compatible = "ti,omap4-i2c";
190 #address-cells = <1>; 192 #address-cells = <1>;
191 #size-cells = <0>; 193 #size-cells = <0>;
@@ -195,7 +197,7 @@
195 status = "disabled"; 197 status = "disabled";
196 }; 198 };
197 199
198 i2c2: i2c@4802a000 { 200 i2c1: i2c@4802a000 {
199 compatible = "ti,omap4-i2c"; 201 compatible = "ti,omap4-i2c";
200 #address-cells = <1>; 202 #address-cells = <1>;
201 #size-cells = <0>; 203 #size-cells = <0>;
@@ -205,7 +207,7 @@
205 status = "disabled"; 207 status = "disabled";
206 }; 208 };
207 209
208 i2c3: i2c@4819c000 { 210 i2c2: i2c@4819c000 {
209 compatible = "ti,omap4-i2c"; 211 compatible = "ti,omap4-i2c";
210 #address-cells = <1>; 212 #address-cells = <1>;
211 #size-cells = <0>; 213 #size-cells = <0>;
@@ -225,7 +227,8 @@
225 dcan0: d_can@481cc000 { 227 dcan0: d_can@481cc000 {
226 compatible = "bosch,d_can"; 228 compatible = "bosch,d_can";
227 ti,hwmods = "d_can0"; 229 ti,hwmods = "d_can0";
228 reg = <0x481cc000 0x2000>; 230 reg = <0x481cc000 0x2000
231 0x44e10644 0x4>;
229 interrupts = <52>; 232 interrupts = <52>;
230 status = "disabled"; 233 status = "disabled";
231 }; 234 };
@@ -233,13 +236,14 @@
233 dcan1: d_can@481d0000 { 236 dcan1: d_can@481d0000 {
234 compatible = "bosch,d_can"; 237 compatible = "bosch,d_can";
235 ti,hwmods = "d_can1"; 238 ti,hwmods = "d_can1";
236 reg = <0x481d0000 0x2000>; 239 reg = <0x481d0000 0x2000
240 0x44e10644 0x4>;
237 interrupts = <55>; 241 interrupts = <55>;
238 status = "disabled"; 242 status = "disabled";
239 }; 243 };
240 244
241 timer1: timer@44e31000 { 245 timer1: timer@44e31000 {
242 compatible = "ti,omap2-timer"; 246 compatible = "ti,am335x-timer-1ms";
243 reg = <0x44e31000 0x400>; 247 reg = <0x44e31000 0x400>;
244 interrupts = <67>; 248 interrupts = <67>;
245 ti,hwmods = "timer1"; 249 ti,hwmods = "timer1";
@@ -247,21 +251,21 @@
247 }; 251 };
248 252
249 timer2: timer@48040000 { 253 timer2: timer@48040000 {
250 compatible = "ti,omap2-timer"; 254 compatible = "ti,am335x-timer";
251 reg = <0x48040000 0x400>; 255 reg = <0x48040000 0x400>;
252 interrupts = <68>; 256 interrupts = <68>;
253 ti,hwmods = "timer2"; 257 ti,hwmods = "timer2";
254 }; 258 };
255 259
256 timer3: timer@48042000 { 260 timer3: timer@48042000 {
257 compatible = "ti,omap2-timer"; 261 compatible = "ti,am335x-timer";
258 reg = <0x48042000 0x400>; 262 reg = <0x48042000 0x400>;
259 interrupts = <69>; 263 interrupts = <69>;
260 ti,hwmods = "timer3"; 264 ti,hwmods = "timer3";
261 }; 265 };
262 266
263 timer4: timer@48044000 { 267 timer4: timer@48044000 {
264 compatible = "ti,omap2-timer"; 268 compatible = "ti,am335x-timer";
265 reg = <0x48044000 0x400>; 269 reg = <0x48044000 0x400>;
266 interrupts = <92>; 270 interrupts = <92>;
267 ti,hwmods = "timer4"; 271 ti,hwmods = "timer4";
@@ -269,7 +273,7 @@
269 }; 273 };
270 274
271 timer5: timer@48046000 { 275 timer5: timer@48046000 {
272 compatible = "ti,omap2-timer"; 276 compatible = "ti,am335x-timer";
273 reg = <0x48046000 0x400>; 277 reg = <0x48046000 0x400>;
274 interrupts = <93>; 278 interrupts = <93>;
275 ti,hwmods = "timer5"; 279 ti,hwmods = "timer5";
@@ -277,7 +281,7 @@
277 }; 281 };
278 282
279 timer6: timer@48048000 { 283 timer6: timer@48048000 {
280 compatible = "ti,omap2-timer"; 284 compatible = "ti,am335x-timer";
281 reg = <0x48048000 0x400>; 285 reg = <0x48048000 0x400>;
282 interrupts = <94>; 286 interrupts = <94>;
283 ti,hwmods = "timer6"; 287 ti,hwmods = "timer6";
@@ -285,7 +289,7 @@
285 }; 289 };
286 290
287 timer7: timer@4804a000 { 291 timer7: timer@4804a000 {
288 compatible = "ti,omap2-timer"; 292 compatible = "ti,am335x-timer";
289 reg = <0x4804a000 0x400>; 293 reg = <0x4804a000 0x400>;
290 interrupts = <95>; 294 interrupts = <95>;
291 ti,hwmods = "timer7"; 295 ti,hwmods = "timer7";
@@ -305,7 +309,7 @@
305 #address-cells = <1>; 309 #address-cells = <1>;
306 #size-cells = <0>; 310 #size-cells = <0>;
307 reg = <0x48030000 0x400>; 311 reg = <0x48030000 0x400>;
308 interrupt = <65>; 312 interrupts = <65>;
309 ti,spi-num-cs = <2>; 313 ti,spi-num-cs = <2>;
310 ti,hwmods = "spi0"; 314 ti,hwmods = "spi0";
311 status = "disabled"; 315 status = "disabled";
@@ -316,7 +320,7 @@
316 #address-cells = <1>; 320 #address-cells = <1>;
317 #size-cells = <0>; 321 #size-cells = <0>;
318 reg = <0x481a0000 0x400>; 322 reg = <0x481a0000 0x400>;
319 interrupt = <125>; 323 interrupts = <125>;
320 ti,spi-num-cs = <2>; 324 ti,spi-num-cs = <2>;
321 ti,hwmods = "spi1"; 325 ti,hwmods = "spi1";
322 status = "disabled"; 326 status = "disabled";
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index 474f760ecadf..e9b5bdae4908 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -7,7 +7,7 @@
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap3.dtsi" 10/include/ "omap34xx.dtsi"
11 11
12/ { 12/ {
13 model = "TI AM3517 EVM (AM3517/05)"; 13 model = "TI AM3517 EVM (AM3517/05)";
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index 5eb26d7d9b4e..556868388a23 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -7,7 +7,7 @@
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap3.dtsi" 10/include/ "omap34xx.dtsi"
11 11
12/ { 12/ {
13 model = "TeeJet Mt.Ventoux"; 13 model = "TeeJet Mt.Ventoux";
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 6403acdbb75f..2353b1f13704 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -30,85 +30,87 @@
30 }; 30 };
31 31
32 soc { 32 soc {
33 serial@d0012000 { 33 internal-regs {
34 clock-frequency = <200000000>; 34 serial@12000 {
35 status = "okay"; 35 clock-frequency = <200000000>;
36 }; 36 status = "okay";
37 sata@d00a0000 {
38 nr-ports = <2>;
39 status = "okay";
40 };
41
42 mdio {
43 phy0: ethernet-phy@0 {
44 reg = <0>;
45 }; 37 };
46 38 sata@a0000 {
47 phy1: ethernet-phy@1 { 39 nr-ports = <2>;
48 reg = <1>; 40 status = "okay";
49 }; 41 };
50 };
51 42
52 ethernet@d0070000 { 43 mdio {
53 status = "okay"; 44 phy0: ethernet-phy@0 {
54 phy = <&phy0>; 45 reg = <0>;
55 phy-mode = "rgmii-id"; 46 };
56 };
57 ethernet@d0074000 {
58 status = "okay";
59 phy = <&phy1>;
60 phy-mode = "rgmii-id";
61 };
62 47
63 mvsdio@d00d4000 { 48 phy1: ethernet-phy@1 {
64 pinctrl-0 = <&sdio_pins1>; 49 reg = <1>;
65 pinctrl-names = "default"; 50 };
66 /* 51 };
67 * This device is disabled by default, because
68 * using the SD card connector requires
69 * changing the default CON40 connector
70 * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
71 * different connector
72 * "DB-88F6710_MPP_RGMII_SD_Jumper".
73 */
74 status = "disabled";
75 /* No CD or WP GPIOs */
76 };
77 52
78 usb@d0050000 { 53 ethernet@70000 {
79 status = "okay"; 54 status = "okay";
80 }; 55 phy = <&phy0>;
56 phy-mode = "rgmii-id";
57 };
58 ethernet@74000 {
59 status = "okay";
60 phy = <&phy1>;
61 phy-mode = "rgmii-id";
62 };
81 63
82 usb@d0051000 { 64 mvsdio@d4000 {
83 status = "okay"; 65 pinctrl-0 = <&sdio_pins1>;
84 }; 66 pinctrl-names = "default";
67 /*
68 * This device is disabled by default, because
69 * using the SD card connector requires
70 * changing the default CON40 connector
71 * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
72 * different connector
73 * "DB-88F6710_MPP_RGMII_SD_Jumper".
74 */
75 status = "disabled";
76 /* No CD or WP GPIOs */
77 };
85 78
86 spi0: spi@d0010600 { 79 usb@50000 {
87 status = "okay"; 80 status = "okay";
81 };
88 82
89 spi-flash@0 { 83 usb@51000 {
90 #address-cells = <1>; 84 status = "okay";
91 #size-cells = <1>;
92 compatible = "mx25l25635e";
93 reg = <0>; /* Chip select 0 */
94 spi-max-frequency = <50000000>;
95 }; 85 };
96 };
97 86
98 pcie-controller { 87 spi0: spi@10600 {
99 status = "okay";
100 /*
101 * The two PCIe units are accessible through
102 * both standard PCIe slots and mini-PCIe
103 * slots on the board.
104 */
105 pcie@1,0 {
106 /* Port 0, Lane 0 */
107 status = "okay"; 88 status = "okay";
89
90 spi-flash@0 {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "mx25l25635e";
94 reg = <0>; /* Chip select 0 */
95 spi-max-frequency = <50000000>;
96 };
108 }; 97 };
109 pcie@2,0 { 98
110 /* Port 1, Lane 0 */ 99 pcie-controller {
111 status = "okay"; 100 status = "okay";
101 /*
102 * The two PCIe units are accessible through
103 * both standard PCIe slots and mini-PCIe
104 * slots on the board.
105 */
106 pcie@1,0 {
107 /* Port 0, Lane 0 */
108 status = "okay";
109 };
110 pcie@2,0 {
111 /* Port 1, Lane 0 */
112 status = "okay";
113 };
112 }; 114 };
113 }; 115 };
114 }; 116 };
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 58ee79372206..14e36e19d515 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -25,113 +25,115 @@
25 }; 25 };
26 26
27 soc { 27 soc {
28 serial@d0012000 { 28 internal-regs {
29 clock-frequency = <200000000>; 29 serial@12000 {
30 status = "okay"; 30 clock-frequency = <200000000>;
31 }; 31 status = "okay";
32 timer@d0020300 {
33 clock-frequency = <600000000>;
34 status = "okay";
35 };
36
37 pinctrl {
38 pwr_led_pin: pwr-led-pin {
39 marvell,pins = "mpp63";
40 marvell,function = "gpo";
41 }; 32 };
42 33 timer@20300 {
43 stat_led_pins: stat-led-pins { 34 clock-frequency = <600000000>;
44 marvell,pins = "mpp64", "mpp65"; 35 status = "okay";
45 marvell,function = "gpio";
46 }; 36 };
47 };
48 37
49 gpio_leds { 38 pinctrl {
50 compatible = "gpio-leds"; 39 pwr_led_pin: pwr-led-pin {
51 pinctrl-names = "default"; 40 marvell,pins = "mpp63";
52 pinctrl-0 = <&pwr_led_pin &stat_led_pins>; 41 marvell,function = "gpo";
42 };
53 43
54 green_pwr_led { 44 stat_led_pins: stat-led-pins {
55 label = "mirabox:green:pwr"; 45 marvell,pins = "mpp64", "mpp65";
56 gpios = <&gpio1 31 1>; 46 marvell,function = "gpio";
57 linux,default-trigger = "heartbeat"; 47 };
58 }; 48 };
59 49
60 blue_stat_led { 50 gpio_leds {
61 label = "mirabox:blue:stat"; 51 compatible = "gpio-leds";
62 gpios = <&gpio2 0 1>; 52 pinctrl-names = "default";
63 linux,default-trigger = "cpu0"; 53 pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
54
55 green_pwr_led {
56 label = "mirabox:green:pwr";
57 gpios = <&gpio1 31 1>;
58 linux,default-trigger = "heartbeat";
59 };
60
61 blue_stat_led {
62 label = "mirabox:blue:stat";
63 gpios = <&gpio2 0 1>;
64 linux,default-trigger = "cpu0";
65 };
66
67 green_stat_led {
68 label = "mirabox:green:stat";
69 gpios = <&gpio2 1 1>;
70 default-state = "off";
71 };
64 }; 72 };
65 73
66 green_stat_led { 74 mdio {
67 label = "mirabox:green:stat"; 75 phy0: ethernet-phy@0 {
68 gpios = <&gpio2 1 1>; 76 reg = <0>;
69 default-state = "off"; 77 };
70 };
71 };
72 78
73 mdio { 79 phy1: ethernet-phy@1 {
74 phy0: ethernet-phy@0 { 80 reg = <1>;
75 reg = <0>; 81 };
76 }; 82 };
77 83 ethernet@70000 {
78 phy1: ethernet-phy@1 { 84 status = "okay";
79 reg = <1>; 85 phy = <&phy0>;
86 phy-mode = "rgmii-id";
87 };
88 ethernet@74000 {
89 status = "okay";
90 phy = <&phy1>;
91 phy-mode = "rgmii-id";
80 }; 92 };
81 };
82 ethernet@d0070000 {
83 status = "okay";
84 phy = <&phy0>;
85 phy-mode = "rgmii-id";
86 };
87 ethernet@d0074000 {
88 status = "okay";
89 phy = <&phy1>;
90 phy-mode = "rgmii-id";
91 };
92
93 mvsdio@d00d4000 {
94 pinctrl-0 = <&sdio_pins3>;
95 pinctrl-names = "default";
96 status = "okay";
97 /*
98 * No CD or WP GPIOs: SDIO interface used for
99 * Wifi/Bluetooth chip
100 */
101 };
102
103 usb@d0050000 {
104 status = "okay";
105 };
106 93
107 usb@d0051000 { 94 mvsdio@d4000 {
108 status = "okay"; 95 pinctrl-0 = <&sdio_pins3>;
109 }; 96 pinctrl-names = "default";
97 status = "okay";
98 /*
99 * No CD or WP GPIOs: SDIO interface used for
100 * Wifi/Bluetooth chip
101 */
102 };
110 103
111 i2c@d0011000 { 104 usb@50000 {
112 status = "okay"; 105 status = "okay";
113 clock-frequency = <100000>;
114 pca9505: pca9505@25 {
115 compatible = "nxp,pca9505";
116 gpio-controller;
117 #gpio-cells = <2>;
118 reg = <0x25>;
119 }; 106 };
120 };
121 107
122 pcie-controller { 108 usb@51000 {
123 status = "okay"; 109 status = "okay";
110 };
124 111
125 /* Internal mini-PCIe connector */ 112 i2c@11000 {
126 pcie@1,0 {
127 /* Port 0, Lane 0 */
128 status = "okay"; 113 status = "okay";
114 clock-frequency = <100000>;
115 pca9505: pca9505@25 {
116 compatible = "nxp,pca9505";
117 gpio-controller;
118 #gpio-cells = <2>;
119 reg = <0x25>;
120 };
129 }; 121 };
130 122
131 /* Connected on the PCB to a USB 3.0 XHCI controller */ 123 pcie-controller {
132 pcie@2,0 {
133 /* Port 1, Lane 0 */
134 status = "okay"; 124 status = "okay";
125
126 /* Internal mini-PCIe connector */
127 pcie@1,0 {
128 /* Port 0, Lane 0 */
129 status = "okay";
130 };
131
132 /* Connected on the PCB to a USB 3.0 XHCI controller */
133 pcie@2,0 {
134 /* Port 1, Lane 0 */
135 status = "okay";
136 };
135 }; 137 };
136 }; 138 };
137 }; 139 };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 516dec31b469..130f8390a7e4 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -28,60 +28,62 @@
28 }; 28 };
29 29
30 soc { 30 soc {
31 serial@d0012000 { 31 internal-regs {
32 clock-frequency = <200000000>; 32 serial@12000 {
33 status = "okay"; 33 clock-frequency = <200000000>;
34 }; 34 status = "okay";
35 sata@d00a0000 {
36 nr-ports = <2>;
37 status = "okay";
38 };
39
40 mdio {
41 phy0: ethernet-phy@0 {
42 reg = <0>;
43 }; 35 };
36 sata@a0000 {
37 nr-ports = <2>;
38 status = "okay";
39 };
40
41 mdio {
42 phy0: ethernet-phy@0 {
43 reg = <0>;
44 };
44 45
45 phy1: ethernet-phy@1 { 46 phy1: ethernet-phy@1 {
46 reg = <1>; 47 reg = <1>;
48 };
47 }; 49 };
48 };
49 50
50 ethernet@d0070000 { 51 ethernet@70000 {
51 status = "okay"; 52 status = "okay";
52 phy = <&phy0>; 53 phy = <&phy0>;
53 phy-mode = "sgmii"; 54 phy-mode = "sgmii";
54 }; 55 };
55 ethernet@d0074000 { 56 ethernet@74000 {
56 status = "okay"; 57 status = "okay";
57 phy = <&phy1>; 58 phy = <&phy1>;
58 phy-mode = "rgmii-id"; 59 phy-mode = "rgmii-id";
59 }; 60 };
60 61
61 mvsdio@d00d4000 { 62 mvsdio@d4000 {
62 pinctrl-0 = <&sdio_pins1>; 63 pinctrl-0 = <&sdio_pins1>;
63 pinctrl-names = "default"; 64 pinctrl-names = "default";
64 status = "okay"; 65 status = "okay";
65 /* No CD or WP GPIOs */ 66 /* No CD or WP GPIOs */
66 }; 67 };
67 68
68 usb@d0050000 { 69 usb@50000 {
69 status = "okay"; 70 status = "okay";
70 }; 71 };
71 72
72 usb@d0051000 { 73 usb@51000 {
73 status = "okay"; 74 status = "okay";
74 }; 75 };
75 };
76 76
77 gpio-keys { 77 gpio-keys {
78 compatible = "gpio-keys"; 78 compatible = "gpio-keys";
79 #address-cells = <1>; 79 #address-cells = <1>;
80 #size-cells = <0>; 80 #size-cells = <0>;
81 button@1 { 81 button@1 {
82 label = "Software Button"; 82 label = "Software Button";
83 linux,code = <116>; 83 linux,code = <116>;
84 gpios = <&gpio0 6 1>; 84 gpios = <&gpio0 6 1>;
85 };
86 };
85 }; 87 };
86 }; 88 };
87}; 89 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 9693f796bcfe..272bbc65fab0 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -16,7 +16,7 @@
16 * 370 and Armada XP SoC. 16 * 370 and Armada XP SoC.
17 */ 17 */
18 18
19/include/ "skeleton.dtsi" 19/include/ "skeleton64.dtsi"
20 20
21/ { 21/ {
22 model = "Marvell Armada 370 and XP SoC"; 22 model = "Marvell Armada 370 and XP SoC";
@@ -28,199 +28,203 @@
28 }; 28 };
29 }; 29 };
30 30
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
34 #size-cells = <1>;
35 interrupt-controller;
36 };
37
38 coherency-fabric@d0020200 {
39 compatible = "marvell,coherency-fabric";
40 reg = <0xd0020200 0xb0>,
41 <0xd0021810 0x1c>;
42 };
43
44 soc { 31 soc {
45 #address-cells = <1>; 32 #address-cells = <1>;
46 #size-cells = <1>; 33 #size-cells = <1>;
47 compatible = "simple-bus"; 34 compatible = "simple-bus";
48 interrupt-parent = <&mpic>; 35 interrupt-parent = <&mpic>;
49 ranges; 36 ranges = <0 0 0xd0000000 0x100000>;
37
38 internal-regs {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 ranges;
43
44 mpic: interrupt-controller@20000 {
45 compatible = "marvell,mpic";
46 #interrupt-cells = <1>;
47 #size-cells = <1>;
48 interrupt-controller;
49 };
50
51 coherency-fabric@20200 {
52 compatible = "marvell,coherency-fabric";
53 reg = <0x20200 0xb0>, <0x21810 0x1c>;
54 };
50 55
51 serial@d0012000 { 56 serial@12000 {
52 compatible = "snps,dw-apb-uart"; 57 compatible = "snps,dw-apb-uart";
53 reg = <0xd0012000 0x100>; 58 reg = <0x12000 0x100>;
54 reg-shift = <2>; 59 reg-shift = <2>;
55 interrupts = <41>; 60 interrupts = <41>;
56 reg-io-width = <1>; 61 reg-io-width = <1>;
57 status = "disabled"; 62 status = "disabled";
58 }; 63 };
59 serial@d0012100 { 64 serial@12100 {
60 compatible = "snps,dw-apb-uart"; 65 compatible = "snps,dw-apb-uart";
61 reg = <0xd0012100 0x100>; 66 reg = <0x12100 0x100>;
62 reg-shift = <2>; 67 reg-shift = <2>;
63 interrupts = <42>; 68 interrupts = <42>;
64 reg-io-width = <1>; 69 reg-io-width = <1>;
65 status = "disabled"; 70 status = "disabled";
66 }; 71 };
67 72
68 timer@d0020300 { 73 timer@20300 {
69 compatible = "marvell,armada-370-xp-timer"; 74 compatible = "marvell,armada-370-xp-timer";
70 reg = <0xd0020300 0x30>, 75 reg = <0x20300 0x30>, <0x21040 0x30>;
71 <0xd0021040 0x30>; 76 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
72 interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 77 clocks = <&coreclk 2>;
73 clocks = <&coreclk 2>; 78 };
74 }; 79
75 80 sata@a0000 {
76 sata@d00a0000 { 81 compatible = "marvell,orion-sata";
77 compatible = "marvell,orion-sata"; 82 reg = <0xa0000 0x2400>;
78 reg = <0xd00a0000 0x2400>; 83 interrupts = <55>;
79 interrupts = <55>; 84 clocks = <&gateclk 15>, <&gateclk 30>;
80 clocks = <&gateclk 15>, <&gateclk 30>; 85 clock-names = "0", "1";
81 clock-names = "0", "1"; 86 status = "disabled";
82 status = "disabled"; 87 };
83 };
84 88
85 mdio { 89 mdio {
86 #address-cells = <1>; 90 #address-cells = <1>;
87 #size-cells = <0>; 91 #size-cells = <0>;
88 compatible = "marvell,orion-mdio"; 92 compatible = "marvell,orion-mdio";
89 reg = <0xd0072004 0x4>; 93 reg = <0x72004 0x4>;
90 }; 94 };
91 95
92 ethernet@d0070000 { 96 ethernet@70000 {
93 compatible = "marvell,armada-370-neta"; 97 compatible = "marvell,armada-370-neta";
94 reg = <0xd0070000 0x2500>; 98 reg = <0x70000 0x2500>;
95 interrupts = <8>; 99 interrupts = <8>;
96 clocks = <&gateclk 4>; 100 clocks = <&gateclk 4>;
97 status = "disabled"; 101 status = "disabled";
98 }; 102 };
99 103
100 ethernet@d0074000 { 104 ethernet@74000 {
101 compatible = "marvell,armada-370-neta"; 105 compatible = "marvell,armada-370-neta";
102 reg = <0xd0074000 0x2500>; 106 reg = <0x74000 0x2500>;
103 interrupts = <10>; 107 interrupts = <10>;
104 clocks = <&gateclk 3>; 108 clocks = <&gateclk 3>;
105 status = "disabled"; 109 status = "disabled";
106 }; 110 };
107 111
108 i2c0: i2c@d0011000 { 112 i2c0: i2c@11000 {
109 compatible = "marvell,mv64xxx-i2c"; 113 compatible = "marvell,mv64xxx-i2c";
110 reg = <0xd0011000 0x20>; 114 reg = <0x11000 0x20>;
111 #address-cells = <1>; 115 #address-cells = <1>;
112 #size-cells = <0>; 116 #size-cells = <0>;
113 interrupts = <31>; 117 interrupts = <31>;
114 timeout-ms = <1000>; 118 timeout-ms = <1000>;
115 clocks = <&coreclk 0>; 119 clocks = <&coreclk 0>;
116 status = "disabled"; 120 status = "disabled";
117 }; 121 };
118 122
119 i2c1: i2c@d0011100 { 123 i2c1: i2c@11100 {
120 compatible = "marvell,mv64xxx-i2c"; 124 compatible = "marvell,mv64xxx-i2c";
121 reg = <0xd0011100 0x20>; 125 reg = <0x11100 0x20>;
122 #address-cells = <1>; 126 #address-cells = <1>;
123 #size-cells = <0>; 127 #size-cells = <0>;
124 interrupts = <32>; 128 interrupts = <32>;
125 timeout-ms = <1000>; 129 timeout-ms = <1000>;
126 clocks = <&coreclk 0>; 130 clocks = <&coreclk 0>;
127 status = "disabled"; 131 status = "disabled";
128 }; 132 };
129 133
130 rtc@10300 { 134 rtc@10300 {
131 compatible = "marvell,orion-rtc"; 135 compatible = "marvell,orion-rtc";
132 reg = <0xd0010300 0x20>; 136 reg = <0x10300 0x20>;
133 interrupts = <50>; 137 interrupts = <50>;
134 }; 138 };
135 139
136 mvsdio@d00d4000 { 140 mvsdio@d4000 {
137 compatible = "marvell,orion-sdio"; 141 compatible = "marvell,orion-sdio";
138 reg = <0xd00d4000 0x200>; 142 reg = <0xd4000 0x200>;
139 interrupts = <54>; 143 interrupts = <54>;
140 clocks = <&gateclk 17>; 144 clocks = <&gateclk 17>;
141 status = "disabled"; 145 status = "disabled";
142 }; 146 };
143
144 usb@d0050000 {
145 compatible = "marvell,orion-ehci";
146 reg = <0xd0050000 0x500>;
147 interrupts = <45>;
148 status = "disabled";
149 };
150
151 usb@d0051000 {
152 compatible = "marvell,orion-ehci";
153 reg = <0xd0051000 0x500>;
154 interrupts = <46>;
155 status = "disabled";
156 };
157
158 spi0: spi@d0010600 {
159 compatible = "marvell,orion-spi";
160 reg = <0xd0010600 0x28>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 cell-index = <0>;
164 interrupts = <30>;
165 clocks = <&coreclk 0>;
166 status = "disabled";
167 };
168
169 spi1: spi@d0010680 {
170 compatible = "marvell,orion-spi";
171 reg = <0xd0010680 0x28>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 cell-index = <1>;
175 interrupts = <92>;
176 clocks = <&coreclk 0>;
177 status = "disabled";
178 };
179
180 devbus-bootcs@d0010400 {
181 compatible = "marvell,mvebu-devbus";
182 reg = <0xd0010400 0x8>;
183 #address-cells = <1>;
184 #size-cells = <1>;
185 clocks = <&coreclk 0>;
186 status = "disabled";
187 };
188
189 devbus-cs0@d0010408 {
190 compatible = "marvell,mvebu-devbus";
191 reg = <0xd0010408 0x8>;
192 #address-cells = <1>;
193 #size-cells = <1>;
194 clocks = <&coreclk 0>;
195 status = "disabled";
196 };
197
198 devbus-cs1@d0010410 {
199 compatible = "marvell,mvebu-devbus";
200 reg = <0xd0010410 0x8>;
201 #address-cells = <1>;
202 #size-cells = <1>;
203 clocks = <&coreclk 0>;
204 status = "disabled";
205 };
206 147
207 devbus-cs2@d0010418 { 148 usb@50000 {
208 compatible = "marvell,mvebu-devbus"; 149 compatible = "marvell,orion-ehci";
209 reg = <0xd0010418 0x8>; 150 reg = <0x50000 0x500>;
210 #address-cells = <1>; 151 interrupts = <45>;
211 #size-cells = <1>; 152 status = "disabled";
212 clocks = <&coreclk 0>; 153 };
213 status = "disabled";
214 };
215 154
216 devbus-cs3@d0010420 { 155 usb@51000 {
217 compatible = "marvell,mvebu-devbus"; 156 compatible = "marvell,orion-ehci";
218 reg = <0xd0010420 0x8>; 157 reg = <0x51000 0x500>;
219 #address-cells = <1>; 158 interrupts = <46>;
220 #size-cells = <1>; 159 status = "disabled";
221 clocks = <&coreclk 0>; 160 };
222 status = "disabled"; 161
162 spi0: spi@10600 {
163 compatible = "marvell,orion-spi";
164 reg = <0x10600 0x28>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 cell-index = <0>;
168 interrupts = <30>;
169 clocks = <&coreclk 0>;
170 status = "disabled";
171 };
172
173 spi1: spi@10680 {
174 compatible = "marvell,orion-spi";
175 reg = <0x10680 0x28>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 cell-index = <1>;
179 interrupts = <92>;
180 clocks = <&coreclk 0>;
181 status = "disabled";
182 };
183
184 devbus-bootcs@10400 {
185 compatible = "marvell,mvebu-devbus";
186 reg = <0x10400 0x8>;
187 #address-cells = <1>;
188 #size-cells = <1>;
189 clocks = <&coreclk 0>;
190 status = "disabled";
191 };
192
193 devbus-cs0@10408 {
194 compatible = "marvell,mvebu-devbus";
195 reg = <0x10408 0x8>;
196 #address-cells = <1>;
197 #size-cells = <1>;
198 clocks = <&coreclk 0>;
199 status = "disabled";
200 };
201
202 devbus-cs1@10410 {
203 compatible = "marvell,mvebu-devbus";
204 reg = <0x10410 0x8>;
205 #address-cells = <1>;
206 #size-cells = <1>;
207 clocks = <&coreclk 0>;
208 status = "disabled";
209 };
210
211 devbus-cs2@10418 {
212 compatible = "marvell,mvebu-devbus";
213 reg = <0x10418 0x8>;
214 #address-cells = <1>;
215 #size-cells = <1>;
216 clocks = <&coreclk 0>;
217 status = "disabled";
218 };
219
220 devbus-cs3@10420 {
221 compatible = "marvell,mvebu-devbus";
222 reg = <0x10420 0x8>;
223 #address-cells = <1>;
224 #size-cells = <1>;
225 clocks = <&coreclk 0>;
226 status = "disabled";
227 };
223 }; 228 };
224 }; 229 };
225}; 230 };
226
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 18f6eb47cc50..b2c1b5af9749 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -16,16 +16,11 @@
16 */ 16 */
17 17
18/include/ "armada-370-xp.dtsi" 18/include/ "armada-370-xp.dtsi"
19/include/ "skeleton.dtsi"
19 20
20/ { 21/ {
21 model = "Marvell Armada 370 family SoC"; 22 model = "Marvell Armada 370 family SoC";
22 compatible = "marvell,armada370", "marvell,armada-370-xp"; 23 compatible = "marvell,armada370", "marvell,armada-370-xp";
23 L2: l2-cache {
24 compatible = "marvell,aurora-outer-cache";
25 reg = <0xd0008000 0x1000>;
26 cache-id-part = <0x100>;
27 wt-override;
28 };
29 24
30 aliases { 25 aliases {
31 gpio0 = &gpio0; 26 gpio0 = &gpio0;
@@ -33,188 +28,197 @@
33 gpio2 = &gpio2; 28 gpio2 = &gpio2;
34 }; 29 };
35 30
36 mpic: interrupt-controller@d0020000 {
37 reg = <0xd0020a00 0x1d0>,
38 <0xd0021870 0x58>;
39 };
40
41 soc { 31 soc {
42 system-controller@d0018200 { 32 ranges = <0 0xd0000000 0x100000>;
33 internal-regs {
34 system-controller@18200 {
43 compatible = "marvell,armada-370-xp-system-controller"; 35 compatible = "marvell,armada-370-xp-system-controller";
44 reg = <0xd0018200 0x100>; 36 reg = <0x18200 0x100>;
45 };
46
47 pinctrl {
48 compatible = "marvell,mv88f6710-pinctrl";
49 reg = <0xd0018000 0x38>;
50
51 sdio_pins1: sdio-pins1 {
52 marvell,pins = "mpp9", "mpp11", "mpp12",
53 "mpp13", "mpp14", "mpp15";
54 marvell,function = "sd0";
55 }; 37 };
56 38
57 sdio_pins2: sdio-pins2 { 39 L2: l2-cache {
58 marvell,pins = "mpp47", "mpp48", "mpp49", 40 compatible = "marvell,aurora-outer-cache";
59 "mpp50", "mpp51", "mpp52"; 41 reg = <0xd0008000 0x1000>;
60 marvell,function = "sd0"; 42 cache-id-part = <0x100>;
43 wt-override;
61 }; 44 };
62 45
63 sdio_pins3: sdio-pins3 { 46 mpic: interrupt-controller@20000 {
64 marvell,pins = "mpp48", "mpp49", "mpp50", 47 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
65 "mpp51", "mpp52", "mpp53";
66 marvell,function = "sd0";
67 }; 48 };
68 };
69
70 gpio0: gpio@d0018100 {
71 compatible = "marvell,orion-gpio";
72 reg = <0xd0018100 0x40>;
73 ngpios = <32>;
74 gpio-controller;
75 #gpio-cells = <2>;
76 interrupt-controller;
77 #interrupts-cells = <2>;
78 interrupts = <82>, <83>, <84>, <85>;
79 };
80
81 gpio1: gpio@d0018140 {
82 compatible = "marvell,orion-gpio";
83 reg = <0xd0018140 0x40>;
84 ngpios = <32>;
85 gpio-controller;
86 #gpio-cells = <2>;
87 interrupt-controller;
88 #interrupts-cells = <2>;
89 interrupts = <87>, <88>, <89>, <90>;
90 };
91
92 gpio2: gpio@d0018180 {
93 compatible = "marvell,orion-gpio";
94 reg = <0xd0018180 0x40>;
95 ngpios = <2>;
96 gpio-controller;
97 #gpio-cells = <2>;
98 interrupt-controller;
99 #interrupts-cells = <2>;
100 interrupts = <91>;
101 };
102 49
103 coreclk: mvebu-sar@d0018230 { 50 pinctrl {
104 compatible = "marvell,armada-370-core-clock"; 51 compatible = "marvell,mv88f6710-pinctrl";
105 reg = <0xd0018230 0x08>; 52 reg = <0x18000 0x38>;
106 #clock-cells = <1>; 53
107 }; 54 sdio_pins1: sdio-pins1 {
108 55 marvell,pins = "mpp9", "mpp11", "mpp12",
109 gateclk: clock-gating-control@d0018220 { 56 "mpp13", "mpp14", "mpp15";
110 compatible = "marvell,armada-370-gating-clock"; 57 marvell,function = "sd0";
111 reg = <0xd0018220 0x4>; 58 };
112 clocks = <&coreclk 0>; 59
113 #clock-cells = <1>; 60 sdio_pins2: sdio-pins2 {
114 }; 61 marvell,pins = "mpp47", "mpp48", "mpp49",
115 62 "mpp50", "mpp51", "mpp52";
116 xor@d0060800 { 63 marvell,function = "sd0";
117 compatible = "marvell,orion-xor"; 64 };
118 reg = <0xd0060800 0x100 65
119 0xd0060A00 0x100>; 66 sdio_pins3: sdio-pins3 {
120 status = "okay"; 67 marvell,pins = "mpp48", "mpp49", "mpp50",
121 68 "mpp51", "mpp52", "mpp53";
122 xor00 { 69 marvell,function = "sd0";
123 interrupts = <51>; 70 };
124 dmacap,memcpy;
125 dmacap,xor;
126 }; 71 };
127 xor01 {
128 interrupts = <52>;
129 dmacap,memcpy;
130 dmacap,xor;
131 dmacap,memset;
132 };
133 };
134
135 xor@d0060900 {
136 compatible = "marvell,orion-xor";
137 reg = <0xd0060900 0x100
138 0xd0060b00 0x100>;
139 status = "okay";
140 72
141 xor10 { 73 gpio0: gpio@18100 {
142 interrupts = <94>; 74 compatible = "marvell,orion-gpio";
143 dmacap,memcpy; 75 reg = <0x18100 0x40>;
144 dmacap,xor; 76 ngpios = <32>;
77 gpio-controller;
78 #gpio-cells = <2>;
79 interrupt-controller;
80 #interrupts-cells = <2>;
81 interrupts = <82>, <83>, <84>, <85>;
145 }; 82 };
146 xor11 {
147 interrupts = <95>;
148 dmacap,memcpy;
149 dmacap,xor;
150 dmacap,memset;
151 };
152 };
153 83
154 usb@d0050000 { 84 gpio1: gpio@18140 {
155 clocks = <&coreclk 0>; 85 compatible = "marvell,orion-gpio";
156 }; 86 reg = <0x18140 0x40>;
157 87 ngpios = <32>;
158 usb@d0051000 { 88 gpio-controller;
159 clocks = <&coreclk 0>; 89 #gpio-cells = <2>;
160 }; 90 interrupt-controller;
91 #interrupts-cells = <2>;
92 interrupts = <87>, <88>, <89>, <90>;
93 };
161 94
162 thermal@d0018300 { 95 gpio2: gpio@18180 {
163 compatible = "marvell,armada370-thermal"; 96 compatible = "marvell,orion-gpio";
164 reg = <0xd0018300 0x4 97 reg = <0x18180 0x40>;
165 0xd0018304 0x4>; 98 ngpios = <2>;
166 status = "okay"; 99 gpio-controller;
167 }; 100 #gpio-cells = <2>;
101 interrupt-controller;
102 #interrupts-cells = <2>;
103 interrupts = <91>;
104 };
168 105
169 pcie-controller { 106 coreclk: mvebu-sar@18230 {
170 compatible = "marvell,armada-370-pcie"; 107 compatible = "marvell,armada-370-core-clock";
171 status = "disabled"; 108 reg = <0x18230 0x08>;
172 device_type = "pci"; 109 #clock-cells = <1>;
110 };
173 111
174 #address-cells = <3>; 112 gateclk: clock-gating-control@18220 {
175 #size-cells = <2>; 113 compatible = "marvell,armada-370-gating-clock";
114 reg = <0x18220 0x4>;
115 clocks = <&coreclk 0>;
116 #clock-cells = <1>;
117 };
176 118
177 bus-range = <0x00 0xff>; 119 xor@60800 {
120 compatible = "marvell,orion-xor";
121 reg = <0x60800 0x100
122 0x60A00 0x100>;
123 status = "okay";
124
125 xor00 {
126 interrupts = <51>;
127 dmacap,memcpy;
128 dmacap,xor;
129 };
130 xor01 {
131 interrupts = <52>;
132 dmacap,memcpy;
133 dmacap,xor;
134 dmacap,memset;
135 };
136 };
178 137
179 reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>; 138 xor@60900 {
139 compatible = "marvell,orion-xor";
140 reg = <0x60900 0x100
141 0x60b00 0x100>;
142 status = "okay";
143
144 xor10 {
145 interrupts = <94>;
146 dmacap,memcpy;
147 dmacap,xor;
148 };
149 xor11 {
150 interrupts = <95>;
151 dmacap,memcpy;
152 dmacap,xor;
153 dmacap,memset;
154 };
155 };
180 156
181 reg-names = "pcie0.0", "pcie1.0"; 157 usb@50000 {
158 clocks = <&coreclk 0>;
159 };
182 160
183 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ 161 usb@51000 {
184 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ 162 clocks = <&coreclk 0>;
185 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ 163 };
186 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
187 164
188 pcie@1,0 { 165 thermal@18300 {
189 device_type = "pci"; 166 compatible = "marvell,armada370-thermal";
190 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; 167 reg = <0x18300 0x4
191 reg = <0x0800 0 0 0 0>; 168 0x18304 0x4>;
192 #address-cells = <3>; 169 status = "okay";
193 #size-cells = <2>;
194 #interrupt-cells = <1>;
195 ranges;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &mpic 58>;
198 marvell,pcie-port = <0>;
199 marvell,pcie-lane = <0>;
200 clocks = <&gateclk 5>;
201 status = "disabled";
202 }; 170 };
203 171
204 pcie@2,0 { 172 pcie-controller {
173 compatible = "marvell,armada-370-pcie";
174 status = "disabled";
205 device_type = "pci"; 175 device_type = "pci";
206 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; 176
207 reg = <0x1000 0 0 0 0>;
208 #address-cells = <3>; 177 #address-cells = <3>;
209 #size-cells = <2>; 178 #size-cells = <2>;
210 #interrupt-cells = <1>; 179
211 ranges; 180 bus-range = <0x00 0xff>;
212 interrupt-map-mask = <0 0 0 0>; 181
213 interrupt-map = <0 0 0 0 &mpic 62>; 182 reg = <0x40000 0x2000>, <0x80000 0x2000>;
214 marvell,pcie-port = <1>; 183
215 marvell,pcie-lane = <0>; 184 reg-names = "pcie0.0", "pcie1.0";
216 clocks = <&gateclk 9>; 185
217 status = "disabled"; 186 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
187 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
188 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
189 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
190
191 pcie@1,0 {
192 device_type = "pci";
193 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
194 reg = <0x0800 0 0 0 0>;
195 #address-cells = <3>;
196 #size-cells = <2>;
197 #interrupt-cells = <1>;
198 ranges;
199 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 58>;
201 marvell,pcie-port = <0>;
202 marvell,pcie-lane = <0>;
203 clocks = <&gateclk 5>;
204 status = "disabled";
205 };
206
207 pcie@2,0 {
208 device_type = "pci";
209 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
210 reg = <0x1000 0 0 0 0>;
211 #address-cells = <3>;
212 #size-cells = <2>;
213 #interrupt-cells = <1>;
214 ranges;
215 interrupt-map-mask = <0 0 0 0>;
216 interrupt-map = <0 0 0 0 &mpic 62>;
217 marvell,pcie-port = <1>;
218 marvell,pcie-lane = <0>;
219 clocks = <&gateclk 9>;
220 status = "disabled";
221 };
218 }; 222 };
219 }; 223 };
220 }; 224 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 54cc5bb705fb..d6cc8bf8272e 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -26,132 +26,134 @@
26 26
27 memory { 27 memory {
28 device_type = "memory"; 28 device_type = "memory";
29 reg = <0x00000000 0x80000000>; /* 2 GB */ 29 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
30 }; 30 };
31 31
32 soc { 32 soc {
33 serial@d0012000 { 33 internal-regs {
34 clock-frequency = <250000000>; 34 serial@12000 {
35 status = "okay"; 35 clock-frequency = <250000000>;
36 }; 36 status = "okay";
37 serial@d0012100 {
38 clock-frequency = <250000000>;
39 status = "okay";
40 };
41 serial@d0012200 {
42 clock-frequency = <250000000>;
43 status = "okay";
44 };
45 serial@d0012300 {
46 clock-frequency = <250000000>;
47 status = "okay";
48 };
49
50 sata@d00a0000 {
51 nr-ports = <2>;
52 status = "okay";
53 };
54
55 mdio {
56 phy0: ethernet-phy@0 {
57 reg = <0>;
58 }; 37 };
59 38 serial@12100 {
60 phy1: ethernet-phy@1 { 39 clock-frequency = <250000000>;
61 reg = <1>; 40 status = "okay";
62 }; 41 };
63 42 serial@12200 {
64 phy2: ethernet-phy@2 { 43 clock-frequency = <250000000>;
65 reg = <25>; 44 status = "okay";
66 }; 45 };
67 46 serial@12300 {
68 phy3: ethernet-phy@3 { 47 clock-frequency = <250000000>;
69 reg = <27>; 48 status = "okay";
70 }; 49 };
71 };
72
73 ethernet@d0070000 {
74 status = "okay";
75 phy = <&phy0>;
76 phy-mode = "rgmii-id";
77 };
78 ethernet@d0074000 {
79 status = "okay";
80 phy = <&phy1>;
81 phy-mode = "rgmii-id";
82 };
83 ethernet@d0030000 {
84 status = "okay";
85 phy = <&phy2>;
86 phy-mode = "sgmii";
87 };
88 ethernet@d0034000 {
89 status = "okay";
90 phy = <&phy3>;
91 phy-mode = "sgmii";
92 };
93
94 mvsdio@d00d4000 {
95 pinctrl-0 = <&sdio_pins>;
96 pinctrl-names = "default";
97 status = "okay";
98 /* No CD or WP GPIOs */
99 };
100 50
101 usb@d0050000 { 51 sata@a0000 {
102 status = "okay"; 52 nr-ports = <2>;
103 }; 53 status = "okay";
54 };
104 55
105 usb@d0051000 { 56 mdio {
106 status = "okay"; 57 phy0: ethernet-phy@0 {
107 }; 58 reg = <0>;
59 };
108 60
109 usb@d0052000 { 61 phy1: ethernet-phy@1 {
110 status = "okay"; 62 reg = <1>;
111 }; 63 };
112 64
113 spi0: spi@d0010600 { 65 phy2: ethernet-phy@2 {
114 status = "okay"; 66 reg = <25>;
67 };
115 68
116 spi-flash@0 { 69 phy3: ethernet-phy@3 {
117 #address-cells = <1>; 70 reg = <27>;
118 #size-cells = <1>; 71 };
119 compatible = "m25p64";
120 reg = <0>; /* Chip select 0 */
121 spi-max-frequency = <20000000>;
122 }; 72 };
123 };
124 73
125 pcie-controller { 74 ethernet@70000 {
126 status = "okay"; 75 status = "okay";
76 phy = <&phy0>;
77 phy-mode = "rgmii-id";
78 };
79 ethernet@74000 {
80 status = "okay";
81 phy = <&phy1>;
82 phy-mode = "rgmii-id";
83 };
84 ethernet@30000 {
85 status = "okay";
86 phy = <&phy2>;
87 phy-mode = "sgmii";
88 };
89 ethernet@34000 {
90 status = "okay";
91 phy = <&phy3>;
92 phy-mode = "sgmii";
93 };
127 94
128 /* 95 mvsdio@d4000 {
129 * All 6 slots are physically present as 96 pinctrl-0 = <&sdio_pins>;
130 * standard PCIe slots on the board. 97 pinctrl-names = "default";
131 */
132 pcie@1,0 {
133 /* Port 0, Lane 0 */
134 status = "okay"; 98 status = "okay";
99 /* No CD or WP GPIOs */
135 }; 100 };
136 pcie@2,0 { 101
137 /* Port 0, Lane 1 */ 102 usb@50000 {
138 status = "okay"; 103 status = "okay";
139 }; 104 };
140 pcie@3,0 { 105
141 /* Port 0, Lane 2 */ 106 usb@51000 {
142 status = "okay"; 107 status = "okay";
143 }; 108 };
144 pcie@4,0 { 109
145 /* Port 0, Lane 3 */ 110 usb@52000 {
146 status = "okay"; 111 status = "okay";
147 }; 112 };
148 pcie@9,0 { 113
149 /* Port 2, Lane 0 */ 114 spi0: spi@10600 {
150 status = "okay"; 115 status = "okay";
116
117 spi-flash@0 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "m25p64";
121 reg = <0>; /* Chip select 0 */
122 spi-max-frequency = <20000000>;
123 };
151 }; 124 };
152 pcie@10,0 { 125
153 /* Port 3, Lane 0 */ 126 pcie-controller {
154 status = "okay"; 127 status = "okay";
128
129 /*
130 * All 6 slots are physically present as
131 * standard PCIe slots on the board.
132 */
133 pcie@1,0 {
134 /* Port 0, Lane 0 */
135 status = "okay";
136 };
137 pcie@2,0 {
138 /* Port 0, Lane 1 */
139 status = "okay";
140 };
141 pcie@3,0 {
142 /* Port 0, Lane 2 */
143 status = "okay";
144 };
145 pcie@4,0 {
146 /* Port 0, Lane 3 */
147 status = "okay";
148 };
149 pcie@9,0 {
150 /* Port 2, Lane 0 */
151 status = "okay";
152 };
153 pcie@10,0 {
154 /* Port 3, Lane 0 */
155 status = "okay";
156 };
155 }; 157 };
156 }; 158 };
157 }; 159 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 04f28a712b98..26ad06fc147e 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -26,137 +26,141 @@
26 26
27 memory { 27 memory {
28 device_type = "memory"; 28 device_type = "memory";
29
30 /* 29 /*
31 * 4 GB of plug-in RAM modules by default but only 3GB 30 * 8 GB of plug-in RAM modules by default.The amount
32 * are visible, the amount of memory available can be 31 * of memory available can be changed by the
33 * changed by the bootloader according the size of the 32 * bootloader according the size of the module
34 * module actually plugged 33 * actually plugged. Only 7GB are usable because
34 * addresses from 0xC0000000 to 0xffffffff are used by
35 * the internal registers of the SoC.
35 */ 36 */
36 reg = <0x00000000 0xC0000000>; 37 reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
38 <0x00000001 0x00000000 0x00000001 0x00000000>;
37 }; 39 };
38 40
39 soc { 41 soc {
40 serial@d0012000 { 42 internal-regs {
41 clock-frequency = <250000000>; 43 serial@12000 {
42 status = "okay"; 44 clock-frequency = <250000000>;
43 }; 45 status = "okay";
44 serial@d0012100 {
45 clock-frequency = <250000000>;
46 status = "okay";
47 };
48 serial@d0012200 {
49 clock-frequency = <250000000>;
50 status = "okay";
51 };
52 serial@d0012300 {
53 clock-frequency = <250000000>;
54 status = "okay";
55 };
56
57 sata@d00a0000 {
58 nr-ports = <2>;
59 status = "okay";
60 };
61
62 mdio {
63 phy0: ethernet-phy@0 {
64 reg = <16>;
65 }; 46 };
66 47 serial@12100 {
67 phy1: ethernet-phy@1 { 48 clock-frequency = <250000000>;
68 reg = <17>; 49 status = "okay";
69 }; 50 };
70 51 serial@12200 {
71 phy2: ethernet-phy@2 { 52 clock-frequency = <250000000>;
72 reg = <18>; 53 status = "okay";
54 };
55 serial@12300 {
56 clock-frequency = <250000000>;
57 status = "okay";
73 }; 58 };
74 59
75 phy3: ethernet-phy@3 { 60 sata@a0000 {
76 reg = <19>; 61 nr-ports = <2>;
62 status = "okay";
77 }; 63 };
78 };
79 64
80 ethernet@d0070000 { 65 mdio {
81 status = "okay"; 66 phy0: ethernet-phy@0 {
82 phy = <&phy0>; 67 reg = <16>;
83 phy-mode = "rgmii-id"; 68 };
84 };
85 ethernet@d0074000 {
86 status = "okay";
87 phy = <&phy1>;
88 phy-mode = "rgmii-id";
89 };
90 ethernet@d0030000 {
91 status = "okay";
92 phy = <&phy2>;
93 phy-mode = "rgmii-id";
94 };
95 ethernet@d0034000 {
96 status = "okay";
97 phy = <&phy3>;
98 phy-mode = "rgmii-id";
99 };
100 69
101 spi0: spi@d0010600 { 70 phy1: ethernet-phy@1 {
102 status = "okay"; 71 reg = <17>;
72 };
103 73
104 spi-flash@0 { 74 phy2: ethernet-phy@2 {
105 #address-cells = <1>; 75 reg = <18>;
106 #size-cells = <1>; 76 };
107 compatible = "n25q128a13";
108 reg = <0>; /* Chip select 0 */
109 spi-max-frequency = <108000000>;
110 };
111 };
112 77
113 devbus-bootcs@d0010400 { 78 phy3: ethernet-phy@3 {
114 status = "okay"; 79 reg = <19>;
115 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ 80 };
116
117 /* Device Bus parameters are required */
118
119 /* Read parameters */
120 devbus,bus-width = <8>;
121 devbus,turn-off-ps = <60000>;
122 devbus,badr-skew-ps = <0>;
123 devbus,acc-first-ps = <124000>;
124 devbus,acc-next-ps = <248000>;
125 devbus,rd-setup-ps = <0>;
126 devbus,rd-hold-ps = <0>;
127
128 /* Write parameters */
129 devbus,sync-enable = <0>;
130 devbus,wr-high-ps = <60000>;
131 devbus,wr-low-ps = <60000>;
132 devbus,ale-wr-ps = <60000>;
133
134 /* NOR 16 MiB */
135 nor@0 {
136 compatible = "cfi-flash";
137 reg = <0 0x1000000>;
138 bank-width = <2>;
139 }; 81 };
140 };
141 82
142 pcie-controller { 83 ethernet@70000 {
143 status = "okay"; 84 status = "okay";
85 phy = <&phy0>;
86 phy-mode = "rgmii-id";
87 };
88 ethernet@74000 {
89 status = "okay";
90 phy = <&phy1>;
91 phy-mode = "rgmii-id";
92 };
93 ethernet@30000 {
94 status = "okay";
95 phy = <&phy2>;
96 phy-mode = "rgmii-id";
97 };
98 ethernet@34000 {
99 status = "okay";
100 phy = <&phy3>;
101 phy-mode = "rgmii-id";
102 };
144 103
145 /* 104 spi0: spi@10600 {
146 * The 3 slots are physically present as
147 * standard PCIe slots on the board.
148 */
149 pcie@1,0 {
150 /* Port 0, Lane 0 */
151 status = "okay"; 105 status = "okay";
106
107 spi-flash@0 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "n25q128a13";
111 reg = <0>; /* Chip select 0 */
112 spi-max-frequency = <108000000>;
113 };
152 }; 114 };
153 pcie@9,0 { 115
154 /* Port 2, Lane 0 */ 116 devbus-bootcs@10400 {
155 status = "okay"; 117 status = "okay";
118 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
119
120 /* Device Bus parameters are required */
121
122 /* Read parameters */
123 devbus,bus-width = <8>;
124 devbus,turn-off-ps = <60000>;
125 devbus,badr-skew-ps = <0>;
126 devbus,acc-first-ps = <124000>;
127 devbus,acc-next-ps = <248000>;
128 devbus,rd-setup-ps = <0>;
129 devbus,rd-hold-ps = <0>;
130
131 /* Write parameters */
132 devbus,sync-enable = <0>;
133 devbus,wr-high-ps = <60000>;
134 devbus,wr-low-ps = <60000>;
135 devbus,ale-wr-ps = <60000>;
136
137 /* NOR 16 MiB */
138 nor@0 {
139 compatible = "cfi-flash";
140 reg = <0 0x1000000>;
141 bank-width = <2>;
142 };
156 }; 143 };
157 pcie@10,0 { 144
158 /* Port 3, Lane 0 */ 145 pcie-controller {
159 status = "okay"; 146 status = "okay";
147
148 /*
149 * The 3 slots are physically present as
150 * standard PCIe slots on the board.
151 */
152 pcie@1,0 {
153 /* Port 0, Lane 0 */
154 status = "okay";
155 };
156 pcie@9,0 {
157 /* Port 2, Lane 0 */
158 status = "okay";
159 };
160 pcie@10,0 {
161 /* Port 3, Lane 0 */
162 status = "okay";
163 };
160 }; 164 };
161 }; 165 };
162 }; 166 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index c2c78459a4d4..f8eaa383e07f 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -25,159 +25,161 @@
25 }; 25 };
26 26
27 cpus { 27 cpus {
28 #address-cells = <1>; 28 #address-cells = <1>;
29 #size-cells = <0>; 29 #size-cells = <0>;
30 30
31 cpu@0 { 31 cpu@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 compatible = "marvell,sheeva-v7"; 33 compatible = "marvell,sheeva-v7";
34 reg = <0>; 34 reg = <0>;
35 clocks = <&cpuclk 0>; 35 clocks = <&cpuclk 0>;
36 };
37
38 cpu@1 {
39 device_type = "cpu";
40 compatible = "marvell,sheeva-v7";
41 reg = <1>;
42 clocks = <&cpuclk 1>;
43 };
44 };
45
46 soc {
47 pinctrl {
48 compatible = "marvell,mv78230-pinctrl";
49 reg = <0xd0018000 0x38>;
50
51 sdio_pins: sdio-pins {
52 marvell,pins = "mpp30", "mpp31", "mpp32",
53 "mpp33", "mpp34", "mpp35";
54 marvell,function = "sd0";
55 };
56 };
57
58 gpio0: gpio@d0018100 {
59 compatible = "marvell,orion-gpio";
60 reg = <0xd0018100 0x40>;
61 ngpios = <32>;
62 gpio-controller;
63 #gpio-cells = <2>;
64 interrupt-controller;
65 #interrupts-cells = <2>;
66 interrupts = <82>, <83>, <84>, <85>;
67 }; 36 };
68 37
69 gpio1: gpio@d0018140 { 38 cpu@1 {
70 compatible = "marvell,orion-gpio"; 39 device_type = "cpu";
71 reg = <0xd0018140 0x40>; 40 compatible = "marvell,sheeva-v7";
72 ngpios = <17>; 41 reg = <1>;
73 gpio-controller; 42 clocks = <&cpuclk 1>;
74 #gpio-cells = <2>;
75 interrupt-controller;
76 #interrupts-cells = <2>;
77 interrupts = <87>, <88>, <89>;
78 }; 43 };
44 };
79 45
80 /* 46 soc {
81 * MV78230 has 2 PCIe units Gen2.0: One unit can be 47 internal-regs {
82 * configured as x4 or quad x1 lanes. One unit is 48 pinctrl {
83 * x4/x1. 49 compatible = "marvell,mv78230-pinctrl";
84 */ 50 reg = <0x18000 0x38>;
85 pcie-controller { 51
86 compatible = "marvell,armada-xp-pcie"; 52 sdio_pins: sdio-pins {
87 status = "disabled"; 53 marvell,pins = "mpp30", "mpp31", "mpp32",
88 device_type = "pci"; 54 "mpp33", "mpp34", "mpp35";
89 55 marvell,function = "sd0";
90 #address-cells = <3>; 56 };
91 #size-cells = <2>;
92
93 bus-range = <0x00 0xff>;
94
95 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
96 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
97 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
98 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
99 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
100 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
101 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
102
103 pcie@1,0 {
104 device_type = "pci";
105 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
106 reg = <0x0800 0 0 0 0>;
107 #address-cells = <3>;
108 #size-cells = <2>;
109 #interrupt-cells = <1>;
110 ranges;
111 interrupt-map-mask = <0 0 0 0>;
112 interrupt-map = <0 0 0 0 &mpic 58>;
113 marvell,pcie-port = <0>;
114 marvell,pcie-lane = <0>;
115 clocks = <&gateclk 5>;
116 status = "disabled";
117 }; 57 };
118 58
119 pcie@2,0 { 59 gpio0: gpio@18100 {
120 device_type = "pci"; 60 compatible = "marvell,orion-gpio";
121 assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>; 61 reg = <0x18100 0x40>;
122 reg = <0x1000 0 0 0 0>; 62 ngpios = <32>;
123 #address-cells = <3>; 63 gpio-controller;
124 #size-cells = <2>; 64 #gpio-cells = <2>;
125 #interrupt-cells = <1>; 65 interrupt-controller;
126 ranges; 66 #interrupts-cells = <2>;
127 interrupt-map-mask = <0 0 0 0>; 67 interrupts = <82>, <83>, <84>, <85>;
128 interrupt-map = <0 0 0 0 &mpic 59>;
129 marvell,pcie-port = <0>;
130 marvell,pcie-lane = <1>;
131 clocks = <&gateclk 6>;
132 status = "disabled";
133 }; 68 };
134 69
135 pcie@3,0 { 70 gpio1: gpio@18140 {
136 device_type = "pci"; 71 compatible = "marvell,orion-gpio";
137 assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>; 72 reg = <0x18140 0x40>;
138 reg = <0x1800 0 0 0 0>; 73 ngpios = <17>;
139 #address-cells = <3>; 74 gpio-controller;
140 #size-cells = <2>; 75 #gpio-cells = <2>;
141 #interrupt-cells = <1>; 76 interrupt-controller;
142 ranges; 77 #interrupts-cells = <2>;
143 interrupt-map-mask = <0 0 0 0>; 78 interrupts = <87>, <88>, <89>;
144 interrupt-map = <0 0 0 0 &mpic 60>;
145 marvell,pcie-port = <0>;
146 marvell,pcie-lane = <2>;
147 clocks = <&gateclk 7>;
148 status = "disabled";
149 }; 79 };
150 80
151 pcie@4,0 { 81 /*
152 device_type = "pci"; 82 * MV78230 has 2 PCIe units Gen2.0: One unit can be
153 assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>; 83 * configured as x4 or quad x1 lanes. One unit is
154 reg = <0x2000 0 0 0 0>; 84 * x4/x1.
155 #address-cells = <3>; 85 */
156 #size-cells = <2>; 86 pcie-controller {
157 #interrupt-cells = <1>; 87 compatible = "marvell,armada-xp-pcie";
158 ranges;
159 interrupt-map-mask = <0 0 0 0>;
160 interrupt-map = <0 0 0 0 &mpic 61>;
161 marvell,pcie-port = <0>;
162 marvell,pcie-lane = <3>;
163 clocks = <&gateclk 8>;
164 status = "disabled"; 88 status = "disabled";
165 };
166
167 pcie@9,0 {
168 device_type = "pci"; 89 device_type = "pci";
169 assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>; 90
170 reg = <0x4800 0 0 0 0>; 91#address-cells = <3>;
171 #address-cells = <3>; 92#size-cells = <2>;
172 #size-cells = <2>; 93
173 #interrupt-cells = <1>; 94 bus-range = <0x00 0xff>;
174 ranges; 95
175 interrupt-map-mask = <0 0 0 0>; 96 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
176 interrupt-map = <0 0 0 0 &mpic 99>; 97 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
177 marvell,pcie-port = <2>; 98 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
178 marvell,pcie-lane = <0>; 99 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
179 clocks = <&gateclk 26>; 100 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
180 status = "disabled"; 101 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
102 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
103
104 pcie@1,0 {
105 device_type = "pci";
106 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
107 reg = <0x0800 0 0 0 0>;
108 #address-cells = <3>;
109 #size-cells = <2>;
110 #interrupt-cells = <1>;
111 ranges;
112 interrupt-map-mask = <0 0 0 0>;
113 interrupt-map = <0 0 0 0 &mpic 58>;
114 marvell,pcie-port = <0>;
115 marvell,pcie-lane = <0>;
116 clocks = <&gateclk 5>;
117 status = "disabled";
118 };
119
120 pcie@2,0 {
121 device_type = "pci";
122 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
123 reg = <0x1000 0 0 0 0>;
124 #address-cells = <3>;
125 #size-cells = <2>;
126 #interrupt-cells = <1>;
127 ranges;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &mpic 59>;
130 marvell,pcie-port = <0>;
131 marvell,pcie-lane = <1>;
132 clocks = <&gateclk 6>;
133 status = "disabled";
134 };
135
136 pcie@3,0 {
137 device_type = "pci";
138 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
139 reg = <0x1800 0 0 0 0>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 #interrupt-cells = <1>;
143 ranges;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 60>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <2>;
148 clocks = <&gateclk 7>;
149 status = "disabled";
150 };
151
152 pcie@4,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
155 reg = <0x2000 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 61>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <3>;
164 clocks = <&gateclk 8>;
165 status = "disabled";
166 };
167
168 pcie@9,0 {
169 device_type = "pci";
170 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
171 reg = <0x4800 0 0 0 0>;
172 #address-cells = <3>;
173 #size-cells = <2>;
174 #interrupt-cells = <1>;
175 ranges;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 99>;
178 marvell,pcie-port = <2>;
179 marvell,pcie-lane = <0>;
180 clocks = <&gateclk 26>;
181 status = "disabled";
182 };
181 }; 183 };
182 }; 184 };
183 }; 185 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 885bf229eef7..f4029f015aff 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -26,196 +26,198 @@
26 }; 26 };
27 27
28 cpus { 28 cpus {
29 #address-cells = <1>; 29 #address-cells = <1>;
30 #size-cells = <0>; 30 #size-cells = <0>;
31 31
32 cpu@0 { 32 cpu@0 {
33 device_type = "cpu"; 33 device_type = "cpu";
34 compatible = "marvell,sheeva-v7"; 34 compatible = "marvell,sheeva-v7";
35 reg = <0>; 35 reg = <0>;
36 clocks = <&cpuclk 0>; 36 clocks = <&cpuclk 0>;
37 }; 37 };
38 38
39 cpu@1 { 39 cpu@1 {
40 device_type = "cpu"; 40 device_type = "cpu";
41 compatible = "marvell,sheeva-v7"; 41 compatible = "marvell,sheeva-v7";
42 reg = <1>; 42 reg = <1>;
43 clocks = <&cpuclk 1>; 43 clocks = <&cpuclk 1>;
44 }; 44 };
45 }; 45 };
46 46
47 soc { 47 soc {
48 pinctrl { 48 internal-regs {
49 compatible = "marvell,mv78260-pinctrl"; 49 pinctrl {
50 reg = <0xd0018000 0x38>; 50 compatible = "marvell,mv78260-pinctrl";
51 51 reg = <0x18000 0x38>;
52 sdio_pins: sdio-pins { 52
53 marvell,pins = "mpp30", "mpp31", "mpp32", 53 sdio_pins: sdio-pins {
54 "mpp33", "mpp34", "mpp35"; 54 marvell,pins = "mpp30", "mpp31", "mpp32",
55 marvell,function = "sd0"; 55 "mpp33", "mpp34", "mpp35";
56 marvell,function = "sd0";
57 };
56 }; 58 };
57 };
58 59
59 gpio0: gpio@d0018100 { 60 gpio0: gpio@18100 {
60 compatible = "marvell,orion-gpio"; 61 compatible = "marvell,orion-gpio";
61 reg = <0xd0018100 0x40>; 62 reg = <0x18100 0x40>;
62 ngpios = <32>; 63 ngpios = <32>;
63 gpio-controller; 64 gpio-controller;
64 #gpio-cells = <2>; 65 #gpio-cells = <2>;
65 interrupt-controller; 66 interrupt-controller;
66 #interrupts-cells = <2>; 67 #interrupts-cells = <2>;
67 interrupts = <82>, <83>, <84>, <85>; 68 interrupts = <82>, <83>, <84>, <85>;
68 }; 69 };
69 70
70 gpio1: gpio@d0018140 { 71 gpio1: gpio@18140 {
71 compatible = "marvell,orion-gpio"; 72 compatible = "marvell,orion-gpio";
72 reg = <0xd0018140 0x40>; 73 reg = <0x18140 0x40>;
73 ngpios = <32>; 74 ngpios = <32>;
74 gpio-controller; 75 gpio-controller;
75 #gpio-cells = <2>; 76 #gpio-cells = <2>;
76 interrupt-controller; 77 interrupt-controller;
77 #interrupts-cells = <2>; 78 #interrupts-cells = <2>;
78 interrupts = <87>, <88>, <89>, <90>; 79 interrupts = <87>, <88>, <89>, <90>;
79 }; 80 };
80 81
81 gpio2: gpio@d0018180 { 82 gpio2: gpio@18180 {
82 compatible = "marvell,orion-gpio"; 83 compatible = "marvell,orion-gpio";
83 reg = <0xd0018180 0x40>; 84 reg = <0x18180 0x40>;
84 ngpios = <3>; 85 ngpios = <3>;
85 gpio-controller; 86 gpio-controller;
86 #gpio-cells = <2>; 87 #gpio-cells = <2>;
87 interrupt-controller; 88 interrupt-controller;
88 #interrupts-cells = <2>; 89 #interrupts-cells = <2>;
89 interrupts = <91>; 90 interrupts = <91>;
90 }; 91 };
91 92
92 ethernet@d0034000 { 93 ethernet@34000 {
93 compatible = "marvell,armada-370-neta"; 94 compatible = "marvell,armada-370-neta";
94 reg = <0xd0034000 0x2500>; 95 reg = <0x34000 0x2500>;
95 interrupts = <14>; 96 interrupts = <14>;
96 clocks = <&gateclk 1>; 97 clocks = <&gateclk 1>;
97 status = "disabled"; 98 status = "disabled";
98 };
99
100 /*
101 * MV78260 has 3 PCIe units Gen2.0: Two units can be
102 * configured as x4 or quad x1 lanes. One unit is
103 * x4/x1.
104 */
105 pcie-controller {
106 compatible = "marvell,armada-xp-pcie";
107 status = "disabled";
108 device_type = "pci";
109
110 #address-cells = <3>;
111 #size-cells = <2>;
112
113 bus-range = <0x00 0xff>;
114
115 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
116 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
117 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
118 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
119 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
120 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
121 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
122 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
123 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
124
125 pcie@1,0 {
126 device_type = "pci";
127 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
128 reg = <0x0800 0 0 0 0>;
129 #address-cells = <3>;
130 #size-cells = <2>;
131 #interrupt-cells = <1>;
132 ranges;
133 interrupt-map-mask = <0 0 0 0>;
134 interrupt-map = <0 0 0 0 &mpic 58>;
135 marvell,pcie-port = <0>;
136 marvell,pcie-lane = <0>;
137 clocks = <&gateclk 5>;
138 status = "disabled";
139 };
140
141 pcie@2,0 {
142 device_type = "pci";
143 assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
144 reg = <0x1000 0 0 0 0>;
145 #address-cells = <3>;
146 #size-cells = <2>;
147 #interrupt-cells = <1>;
148 ranges;
149 interrupt-map-mask = <0 0 0 0>;
150 interrupt-map = <0 0 0 0 &mpic 59>;
151 marvell,pcie-port = <0>;
152 marvell,pcie-lane = <1>;
153 clocks = <&gateclk 6>;
154 status = "disabled";
155 }; 99 };
156 100
157 pcie@3,0 { 101 /*
158 device_type = "pci"; 102 * MV78260 has 3 PCIe units Gen2.0: Two units can be
159 assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>; 103 * configured as x4 or quad x1 lanes. One unit is
160 reg = <0x1800 0 0 0 0>; 104 * x4/x1.
161 #address-cells = <3>; 105 */
162 #size-cells = <2>; 106 pcie-controller {
163 #interrupt-cells = <1>; 107 compatible = "marvell,armada-xp-pcie";
164 ranges;
165 interrupt-map-mask = <0 0 0 0>;
166 interrupt-map = <0 0 0 0 &mpic 60>;
167 marvell,pcie-port = <0>;
168 marvell,pcie-lane = <2>;
169 clocks = <&gateclk 7>;
170 status = "disabled"; 108 status = "disabled";
171 };
172
173 pcie@4,0 {
174 device_type = "pci"; 109 device_type = "pci";
175 assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
176 reg = <0x2000 0 0 0 0>;
177 #address-cells = <3>;
178 #size-cells = <2>;
179 #interrupt-cells = <1>;
180 ranges;
181 interrupt-map-mask = <0 0 0 0>;
182 interrupt-map = <0 0 0 0 &mpic 61>;
183 marvell,pcie-port = <0>;
184 marvell,pcie-lane = <3>;
185 clocks = <&gateclk 8>;
186 status = "disabled";
187 };
188 110
189 pcie@9,0 {
190 device_type = "pci";
191 assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
192 reg = <0x4800 0 0 0 0>;
193 #address-cells = <3>; 111 #address-cells = <3>;
194 #size-cells = <2>; 112 #size-cells = <2>;
195 #interrupt-cells = <1>;
196 ranges;
197 interrupt-map-mask = <0 0 0 0>;
198 interrupt-map = <0 0 0 0 &mpic 99>;
199 marvell,pcie-port = <2>;
200 marvell,pcie-lane = <0>;
201 clocks = <&gateclk 26>;
202 status = "disabled";
203 };
204 113
205 pcie@10,0 { 114 bus-range = <0x00 0xff>;
206 device_type = "pci"; 115
207 assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>; 116 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
208 reg = <0x5000 0 0 0 0>; 117 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
209 #address-cells = <3>; 118 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
210 #size-cells = <2>; 119 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
211 #interrupt-cells = <1>; 120 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
212 ranges; 121 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
213 interrupt-map-mask = <0 0 0 0>; 122 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
214 interrupt-map = <0 0 0 0 &mpic 103>; 123 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
215 marvell,pcie-port = <3>; 124 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
216 marvell,pcie-lane = <0>; 125
217 clocks = <&gateclk 27>; 126 pcie@1,0 {
218 status = "disabled"; 127 device_type = "pci";
128 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
129 reg = <0x0800 0 0 0 0>;
130 #address-cells = <3>;
131 #size-cells = <2>;
132 #interrupt-cells = <1>;
133 ranges;
134 interrupt-map-mask = <0 0 0 0>;
135 interrupt-map = <0 0 0 0 &mpic 58>;
136 marvell,pcie-port = <0>;
137 marvell,pcie-lane = <0>;
138 clocks = <&gateclk 5>;
139 status = "disabled";
140 };
141
142 pcie@2,0 {
143 device_type = "pci";
144 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
145 reg = <0x1000 0 0 0 0>;
146 #address-cells = <3>;
147 #size-cells = <2>;
148 #interrupt-cells = <1>;
149 ranges;
150 interrupt-map-mask = <0 0 0 0>;
151 interrupt-map = <0 0 0 0 &mpic 59>;
152 marvell,pcie-port = <0>;
153 marvell,pcie-lane = <1>;
154 clocks = <&gateclk 6>;
155 status = "disabled";
156 };
157
158 pcie@3,0 {
159 device_type = "pci";
160 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
161 reg = <0x1800 0 0 0 0>;
162 #address-cells = <3>;
163 #size-cells = <2>;
164 #interrupt-cells = <1>;
165 ranges;
166 interrupt-map-mask = <0 0 0 0>;
167 interrupt-map = <0 0 0 0 &mpic 60>;
168 marvell,pcie-port = <0>;
169 marvell,pcie-lane = <2>;
170 clocks = <&gateclk 7>;
171 status = "disabled";
172 };
173
174 pcie@4,0 {
175 device_type = "pci";
176 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
177 reg = <0x2000 0 0 0 0>;
178 #address-cells = <3>;
179 #size-cells = <2>;
180 #interrupt-cells = <1>;
181 ranges;
182 interrupt-map-mask = <0 0 0 0>;
183 interrupt-map = <0 0 0 0 &mpic 61>;
184 marvell,pcie-port = <0>;
185 marvell,pcie-lane = <3>;
186 clocks = <&gateclk 8>;
187 status = "disabled";
188 };
189
190 pcie@9,0 {
191 device_type = "pci";
192 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
193 reg = <0x4800 0 0 0 0>;
194 #address-cells = <3>;
195 #size-cells = <2>;
196 #interrupt-cells = <1>;
197 ranges;
198 interrupt-map-mask = <0 0 0 0>;
199 interrupt-map = <0 0 0 0 &mpic 99>;
200 marvell,pcie-port = <2>;
201 marvell,pcie-lane = <0>;
202 clocks = <&gateclk 26>;
203 status = "disabled";
204 };
205
206 pcie@10,0 {
207 device_type = "pci";
208 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
209 reg = <0x5000 0 0 0 0>;
210 #address-cells = <3>;
211 #size-cells = <2>;
212 #interrupt-cells = <1>;
213 ranges;
214 interrupt-map-mask = <0 0 0 0>;
215 interrupt-map = <0 0 0 0 &mpic 103>;
216 marvell,pcie-port = <3>;
217 marvell,pcie-lane = <0>;
218 clocks = <&gateclk 27>;
219 status = "disabled";
220 };
219 }; 221 };
220 }; 222 };
221 }; 223 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 23a5ac4490a8..6ab56bd35de9 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -27,277 +27,279 @@
27 27
28 28
29 cpus { 29 cpus {
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <0>; 31 #size-cells = <0>;
32 32
33 cpu@0 { 33 cpu@0 {
34 device_type = "cpu"; 34 device_type = "cpu";
35 compatible = "marvell,sheeva-v7"; 35 compatible = "marvell,sheeva-v7";
36 reg = <0>; 36 reg = <0>;
37 clocks = <&cpuclk 0>; 37 clocks = <&cpuclk 0>;
38 }; 38 };
39 39
40 cpu@1 { 40 cpu@1 {
41 device_type = "cpu"; 41 device_type = "cpu";
42 compatible = "marvell,sheeva-v7"; 42 compatible = "marvell,sheeva-v7";
43 reg = <1>; 43 reg = <1>;
44 clocks = <&cpuclk 1>; 44 clocks = <&cpuclk 1>;
45 }; 45 };
46 46
47 cpu@2 { 47 cpu@2 {
48 device_type = "cpu"; 48 device_type = "cpu";
49 compatible = "marvell,sheeva-v7"; 49 compatible = "marvell,sheeva-v7";
50 reg = <2>; 50 reg = <2>;
51 clocks = <&cpuclk 2>; 51 clocks = <&cpuclk 2>;
52 }; 52 };
53 53
54 cpu@3 { 54 cpu@3 {
55 device_type = "cpu"; 55 device_type = "cpu";
56 compatible = "marvell,sheeva-v7"; 56 compatible = "marvell,sheeva-v7";
57 reg = <3>; 57 reg = <3>;
58 clocks = <&cpuclk 3>; 58 clocks = <&cpuclk 3>;
59 }; 59 };
60 }; 60 };
61 61
62 soc { 62 soc {
63 pinctrl { 63 internal-regs {
64 compatible = "marvell,mv78460-pinctrl"; 64 pinctrl {
65 reg = <0xd0018000 0x38>; 65 compatible = "marvell,mv78460-pinctrl";
66 reg = <0x18000 0x38>;
66 67
67 sdio_pins: sdio-pins { 68 sdio_pins: sdio-pins {
68 marvell,pins = "mpp30", "mpp31", "mpp32", 69 marvell,pins = "mpp30", "mpp31", "mpp32",
69 "mpp33", "mpp34", "mpp35"; 70 "mpp33", "mpp34", "mpp35";
70 marvell,function = "sd0"; 71 marvell,function = "sd0";
72 };
71 }; 73 };
72 };
73 74
74 gpio0: gpio@d0018100 { 75 gpio0: gpio@18100 {
75 compatible = "marvell,orion-gpio"; 76 compatible = "marvell,orion-gpio";
76 reg = <0xd0018100 0x40>; 77 reg = <0x18100 0x40>;
77 ngpios = <32>; 78 ngpios = <32>;
78 gpio-controller; 79 gpio-controller;
79 #gpio-cells = <2>; 80 #gpio-cells = <2>;
80 interrupt-controller; 81 interrupt-controller;
81 #interrupts-cells = <2>; 82 #interrupts-cells = <2>;
82 interrupts = <82>, <83>, <84>, <85>; 83 interrupts = <82>, <83>, <84>, <85>;
83 }; 84 };
84 85
85 gpio1: gpio@d0018140 { 86 gpio1: gpio@18140 {
86 compatible = "marvell,orion-gpio"; 87 compatible = "marvell,orion-gpio";
87 reg = <0xd0018140 0x40>; 88 reg = <0x18140 0x40>;
88 ngpios = <32>; 89 ngpios = <32>;
89 gpio-controller; 90 gpio-controller;
90 #gpio-cells = <2>; 91 #gpio-cells = <2>;
91 interrupt-controller; 92 interrupt-controller;
92 #interrupts-cells = <2>; 93 #interrupts-cells = <2>;
93 interrupts = <87>, <88>, <89>, <90>; 94 interrupts = <87>, <88>, <89>, <90>;
94 }; 95 };
95 96
96 gpio2: gpio@d0018180 { 97 gpio2: gpio@18180 {
97 compatible = "marvell,orion-gpio"; 98 compatible = "marvell,orion-gpio";
98 reg = <0xd0018180 0x40>; 99 reg = <0x18180 0x40>;
99 ngpios = <3>; 100 ngpios = <3>;
100 gpio-controller; 101 gpio-controller;
101 #gpio-cells = <2>; 102 #gpio-cells = <2>;
102 interrupt-controller; 103 interrupt-controller;
103 #interrupts-cells = <2>; 104 #interrupts-cells = <2>;
104 interrupts = <91>; 105 interrupts = <91>;
105 }; 106 };
106 107
107 ethernet@d0034000 { 108 ethernet@34000 {
108 compatible = "marvell,armada-370-neta"; 109 compatible = "marvell,armada-370-neta";
109 reg = <0xd0034000 0x2500>; 110 reg = <0x34000 0x2500>;
110 interrupts = <14>; 111 interrupts = <14>;
111 clocks = <&gateclk 1>; 112 clocks = <&gateclk 1>;
112 status = "disabled"; 113 status = "disabled";
113 }; 114 };
114 115
115 /* 116 /*
116 * MV78460 has 4 PCIe units Gen2.0: Two units can be 117 * MV78460 has 4 PCIe units Gen2.0: Two units can be
117 * configured as x4 or quad x1 lanes. Two units are 118 * configured as x4 or quad x1 lanes. Two units are
118 * x4/x1. 119 * x4/x1.
119 */ 120 */
120 pcie-controller { 121 pcie-controller {
121 compatible = "marvell,armada-xp-pcie"; 122 compatible = "marvell,armada-xp-pcie";
122 status = "disabled"; 123 status = "disabled";
123 device_type = "pci"; 124 device_type = "pci";
124 125
125 #address-cells = <3>; 126 #address-cells = <3>;
126 #size-cells = <2>; 127 #size-cells = <2>;
127 128
128 bus-range = <0x00 0xff>; 129 bus-range = <0x00 0xff>;
129 130
130 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ 131 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
131 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ 132 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
132 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ 133 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
133 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ 134 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
134 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ 135 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
135 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ 136 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
136 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */ 137 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
137 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */ 138 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
138 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */ 139 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
139 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */ 140 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
140 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ 141 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
141 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ 142 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
142 143
143 pcie@1,0 { 144 pcie@1,0 {
144 device_type = "pci"; 145 device_type = "pci";
145 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; 146 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
146 reg = <0x0800 0 0 0 0>; 147 reg = <0x0800 0 0 0 0>;
147 #address-cells = <3>; 148 #address-cells = <3>;
148 #size-cells = <2>; 149 #size-cells = <2>;
149 #interrupt-cells = <1>; 150 #interrupt-cells = <1>;
150 ranges; 151 ranges;
151 interrupt-map-mask = <0 0 0 0>; 152 interrupt-map-mask = <0 0 0 0>;
152 interrupt-map = <0 0 0 0 &mpic 58>; 153 interrupt-map = <0 0 0 0 &mpic 58>;
153 marvell,pcie-port = <0>; 154 marvell,pcie-port = <0>;
154 marvell,pcie-lane = <0>; 155 marvell,pcie-lane = <0>;
155 clocks = <&gateclk 5>; 156 clocks = <&gateclk 5>;
156 status = "disabled"; 157 status = "disabled";
157 }; 158 };
158 159
159 pcie@2,0 { 160 pcie@2,0 {
160 device_type = "pci"; 161 device_type = "pci";
161 assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>; 162 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
162 reg = <0x1000 0 0 0 0>; 163 reg = <0x1000 0 0 0 0>;
163 #address-cells = <3>; 164 #address-cells = <3>;
164 #size-cells = <2>; 165 #size-cells = <2>;
165 #interrupt-cells = <1>; 166 #interrupt-cells = <1>;
166 ranges; 167 ranges;
167 interrupt-map-mask = <0 0 0 0>; 168 interrupt-map-mask = <0 0 0 0>;
168 interrupt-map = <0 0 0 0 &mpic 59>; 169 interrupt-map = <0 0 0 0 &mpic 59>;
169 marvell,pcie-port = <0>; 170 marvell,pcie-port = <0>;
170 marvell,pcie-lane = <1>; 171 marvell,pcie-lane = <1>;
171 clocks = <&gateclk 6>; 172 clocks = <&gateclk 6>;
172 status = "disabled"; 173 status = "disabled";
173 }; 174 };
174 175
175 pcie@3,0 { 176 pcie@3,0 {
176 device_type = "pci"; 177 device_type = "pci";
177 assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>; 178 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
178 reg = <0x1800 0 0 0 0>; 179 reg = <0x1800 0 0 0 0>;
179 #address-cells = <3>; 180 #address-cells = <3>;
180 #size-cells = <2>; 181 #size-cells = <2>;
181 #interrupt-cells = <1>; 182 #interrupt-cells = <1>;
182 ranges; 183 ranges;
183 interrupt-map-mask = <0 0 0 0>; 184 interrupt-map-mask = <0 0 0 0>;
184 interrupt-map = <0 0 0 0 &mpic 60>; 185 interrupt-map = <0 0 0 0 &mpic 60>;
185 marvell,pcie-port = <0>; 186 marvell,pcie-port = <0>;
186 marvell,pcie-lane = <2>; 187 marvell,pcie-lane = <2>;
187 clocks = <&gateclk 7>; 188 clocks = <&gateclk 7>;
188 status = "disabled"; 189 status = "disabled";
189 }; 190 };
190 191
191 pcie@4,0 { 192 pcie@4,0 {
192 device_type = "pci"; 193 device_type = "pci";
193 assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>; 194 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
194 reg = <0x2000 0 0 0 0>; 195 reg = <0x2000 0 0 0 0>;
195 #address-cells = <3>; 196 #address-cells = <3>;
196 #size-cells = <2>; 197 #size-cells = <2>;
197 #interrupt-cells = <1>; 198 #interrupt-cells = <1>;
198 ranges; 199 ranges;
199 interrupt-map-mask = <0 0 0 0>; 200 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 61>; 201 interrupt-map = <0 0 0 0 &mpic 61>;
201 marvell,pcie-port = <0>; 202 marvell,pcie-port = <0>;
202 marvell,pcie-lane = <3>; 203 marvell,pcie-lane = <3>;
203 clocks = <&gateclk 8>; 204 clocks = <&gateclk 8>;
204 status = "disabled"; 205 status = "disabled";
205 }; 206 };
206 207
207 pcie@5,0 { 208 pcie@5,0 {
208 device_type = "pci"; 209 device_type = "pci";
209 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; 210 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
210 reg = <0x2800 0 0 0 0>; 211 reg = <0x2800 0 0 0 0>;
211 #address-cells = <3>; 212 #address-cells = <3>;
212 #size-cells = <2>; 213 #size-cells = <2>;
213 #interrupt-cells = <1>; 214 #interrupt-cells = <1>;
214 ranges; 215 ranges;
215 interrupt-map-mask = <0 0 0 0>; 216 interrupt-map-mask = <0 0 0 0>;
216 interrupt-map = <0 0 0 0 &mpic 62>; 217 interrupt-map = <0 0 0 0 &mpic 62>;
217 marvell,pcie-port = <1>; 218 marvell,pcie-port = <1>;
218 marvell,pcie-lane = <0>; 219 marvell,pcie-lane = <0>;
219 clocks = <&gateclk 9>; 220 clocks = <&gateclk 9>;
220 status = "disabled"; 221 status = "disabled";
221 }; 222 };
222 223
223 pcie@6,0 { 224 pcie@6,0 {
224 device_type = "pci"; 225 device_type = "pci";
225 assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>; 226 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
226 reg = <0x3000 0 0 0 0>; 227 reg = <0x3000 0 0 0 0>;
227 #address-cells = <3>; 228 #address-cells = <3>;
228 #size-cells = <2>; 229 #size-cells = <2>;
229 #interrupt-cells = <1>; 230 #interrupt-cells = <1>;
230 ranges; 231 ranges;
231 interrupt-map-mask = <0 0 0 0>; 232 interrupt-map-mask = <0 0 0 0>;
232 interrupt-map = <0 0 0 0 &mpic 63>; 233 interrupt-map = <0 0 0 0 &mpic 63>;
233 marvell,pcie-port = <1>; 234 marvell,pcie-port = <1>;
234 marvell,pcie-lane = <1>; 235 marvell,pcie-lane = <1>;
235 clocks = <&gateclk 10>; 236 clocks = <&gateclk 10>;
236 status = "disabled"; 237 status = "disabled";
237 }; 238 };
238 239
239 pcie@7,0 { 240 pcie@7,0 {
240 device_type = "pci"; 241 device_type = "pci";
241 assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>; 242 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
242 reg = <0x3800 0 0 0 0>; 243 reg = <0x3800 0 0 0 0>;
243 #address-cells = <3>; 244 #address-cells = <3>;
244 #size-cells = <2>; 245 #size-cells = <2>;
245 #interrupt-cells = <1>; 246 #interrupt-cells = <1>;
246 ranges; 247 ranges;
247 interrupt-map-mask = <0 0 0 0>; 248 interrupt-map-mask = <0 0 0 0>;
248 interrupt-map = <0 0 0 0 &mpic 64>; 249 interrupt-map = <0 0 0 0 &mpic 64>;
249 marvell,pcie-port = <1>; 250 marvell,pcie-port = <1>;
250 marvell,pcie-lane = <2>; 251 marvell,pcie-lane = <2>;
251 clocks = <&gateclk 11>; 252 clocks = <&gateclk 11>;
252 status = "disabled"; 253 status = "disabled";
253 }; 254 };
254 255
255 pcie@8,0 { 256 pcie@8,0 {
256 device_type = "pci"; 257 device_type = "pci";
257 assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>; 258 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
258 reg = <0x4000 0 0 0 0>; 259 reg = <0x4000 0 0 0 0>;
259 #address-cells = <3>; 260 #address-cells = <3>;
260 #size-cells = <2>; 261 #size-cells = <2>;
261 #interrupt-cells = <1>; 262 #interrupt-cells = <1>;
262 ranges; 263 ranges;
263 interrupt-map-mask = <0 0 0 0>; 264 interrupt-map-mask = <0 0 0 0>;
264 interrupt-map = <0 0 0 0 &mpic 65>; 265 interrupt-map = <0 0 0 0 &mpic 65>;
265 marvell,pcie-port = <1>; 266 marvell,pcie-port = <1>;
266 marvell,pcie-lane = <3>; 267 marvell,pcie-lane = <3>;
267 clocks = <&gateclk 12>; 268 clocks = <&gateclk 12>;
268 status = "disabled"; 269 status = "disabled";
269 }; 270 };
270 pcie@9,0 { 271 pcie@9,0 {
271 device_type = "pci"; 272 device_type = "pci";
272 assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>; 273 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
273 reg = <0x4800 0 0 0 0>; 274 reg = <0x4800 0 0 0 0>;
274 #address-cells = <3>; 275 #address-cells = <3>;
275 #size-cells = <2>; 276 #size-cells = <2>;
276 #interrupt-cells = <1>; 277 #interrupt-cells = <1>;
277 ranges; 278 ranges;
278 interrupt-map-mask = <0 0 0 0>; 279 interrupt-map-mask = <0 0 0 0>;
279 interrupt-map = <0 0 0 0 &mpic 99>; 280 interrupt-map = <0 0 0 0 &mpic 99>;
280 marvell,pcie-port = <2>; 281 marvell,pcie-port = <2>;
281 marvell,pcie-lane = <0>; 282 marvell,pcie-lane = <0>;
282 clocks = <&gateclk 26>; 283 clocks = <&gateclk 26>;
283 status = "disabled"; 284 status = "disabled";
284 }; 285 };
285 286
286 pcie@10,0 { 287 pcie@10,0 {
287 device_type = "pci"; 288 device_type = "pci";
288 assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>; 289 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
289 reg = <0x5000 0 0 0 0>; 290 reg = <0x5000 0 0 0 0>;
290 #address-cells = <3>; 291 #address-cells = <3>;
291 #size-cells = <2>; 292 #size-cells = <2>;
292 #interrupt-cells = <1>; 293 #interrupt-cells = <1>;
293 ranges; 294 ranges;
294 interrupt-map-mask = <0 0 0 0>; 295 interrupt-map-mask = <0 0 0 0>;
295 interrupt-map = <0 0 0 0 &mpic 103>; 296 interrupt-map = <0 0 0 0 &mpic 103>;
296 marvell,pcie-port = <3>; 297 marvell,pcie-port = <3>;
297 marvell,pcie-lane = <0>; 298 marvell,pcie-lane = <0>;
298 clocks = <&gateclk 27>; 299 clocks = <&gateclk 27>;
299 status = "disabled"; 300 status = "disabled";
301 };
300 }; 302 };
301 }; 303 };
302 }; 304 };
303 }; 305};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 9d04f04d4e39..f14d36c46159 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -23,158 +23,160 @@
23 23
24 memory { 24 memory {
25 device_type = "memory"; 25 device_type = "memory";
26 reg = <0x00000000 0xC0000000>; /* 3 GB */ 26 reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */
27 }; 27 };
28 28
29 soc { 29 soc {
30 serial@d0012000 { 30 internal-regs {
31 clock-frequency = <250000000>; 31 serial@12000 {
32 status = "okay"; 32 clock-frequency = <250000000>;
33 }; 33 status = "okay";
34 serial@d0012100 {
35 clock-frequency = <250000000>;
36 status = "okay";
37 };
38 pinctrl {
39 led_pins: led-pins-0 {
40 marvell,pins = "mpp49", "mpp51", "mpp53";
41 marvell,function = "gpio";
42 }; 34 };
43 }; 35 serial@12100 {
44 leds { 36 clock-frequency = <250000000>;
45 compatible = "gpio-leds"; 37 status = "okay";
46 pinctrl-names = "default";
47 pinctrl-0 = <&led_pins>;
48
49 red_led {
50 label = "red_led";
51 gpios = <&gpio1 17 1>;
52 default-state = "off";
53 }; 38 };
54 39 pinctrl {
55 yellow_led { 40 led_pins: led-pins-0 {
56 label = "yellow_led"; 41 marvell,pins = "mpp49", "mpp51", "mpp53";
57 gpios = <&gpio1 19 1>; 42 marvell,function = "gpio";
58 default-state = "off"; 43 };
59 }; 44 };
60 45 leds {
61 green_led { 46 compatible = "gpio-leds";
62 label = "green_led"; 47 pinctrl-names = "default";
63 gpios = <&gpio1 21 1>; 48 pinctrl-0 = <&led_pins>;
64 default-state = "off"; 49
65 linux,default-trigger = "heartbeat"; 50 red_led {
51 label = "red_led";
52 gpios = <&gpio1 17 1>;
53 default-state = "off";
54 };
55
56 yellow_led {
57 label = "yellow_led";
58 gpios = <&gpio1 19 1>;
59 default-state = "off";
60 };
61
62 green_led {
63 label = "green_led";
64 gpios = <&gpio1 21 1>;
65 default-state = "off";
66 linux,default-trigger = "heartbeat";
67 };
66 }; 68 };
67 };
68 69
69 gpio_keys { 70 gpio_keys {
70 compatible = "gpio-keys"; 71 compatible = "gpio-keys";
71 #address-cells = <1>; 72 #address-cells = <1>;
72 #size-cells = <0>; 73 #size-cells = <0>;
73 74
74 button@1 { 75 button@1 {
75 label = "Init Button"; 76 label = "Init Button";
76 linux,code = <116>; 77 linux,code = <116>;
77 gpios = <&gpio1 28 0>; 78 gpios = <&gpio1 28 0>;
79 };
78 }; 80 };
79 };
80 81
81 mdio { 82 mdio {
82 phy0: ethernet-phy@0 { 83 phy0: ethernet-phy@0 {
83 reg = <0>; 84 reg = <0>;
84 }; 85 };
85 86
86 phy1: ethernet-phy@1 { 87 phy1: ethernet-phy@1 {
87 reg = <1>; 88 reg = <1>;
88 }; 89 };
89 90
90 phy2: ethernet-phy@2 { 91 phy2: ethernet-phy@2 {
91 reg = <2>; 92 reg = <2>;
92 }; 93 };
93 94
94 phy3: ethernet-phy@3 { 95 phy3: ethernet-phy@3 {
95 reg = <3>; 96 reg = <3>;
97 };
96 }; 98 };
97 };
98 99
99 ethernet@d0070000 { 100 ethernet@70000 {
100 status = "okay"; 101 status = "okay";
101 phy = <&phy0>; 102 phy = <&phy0>;
102 phy-mode = "sgmii"; 103 phy-mode = "sgmii";
103 }; 104 };
104 ethernet@d0074000 { 105 ethernet@74000 {
105 status = "okay"; 106 status = "okay";
106 phy = <&phy1>; 107 phy = <&phy1>;
107 phy-mode = "sgmii"; 108 phy-mode = "sgmii";
108 }; 109 };
109 ethernet@d0030000 { 110 ethernet@30000 {
110 status = "okay"; 111 status = "okay";
111 phy = <&phy2>; 112 phy = <&phy2>;
112 phy-mode = "sgmii"; 113 phy-mode = "sgmii";
113 }; 114 };
114 ethernet@d0034000 { 115 ethernet@34000 {
115 status = "okay"; 116 status = "okay";
116 phy = <&phy3>; 117 phy = <&phy3>;
117 phy-mode = "sgmii"; 118 phy-mode = "sgmii";
118 }; 119 };
119 i2c@d0011000 { 120 i2c@11000 {
120 status = "okay"; 121 status = "okay";
121 clock-frequency = <400000>; 122 clock-frequency = <400000>;
122 }; 123 };
123 i2c@d0011100 { 124 i2c@11100 {
124 status = "okay"; 125 status = "okay";
125 clock-frequency = <400000>; 126 clock-frequency = <400000>;
126 127
127 s35390a: s35390a@30 { 128 s35390a: s35390a@30 {
128 compatible = "s35390a"; 129 compatible = "s35390a";
129 reg = <0x30>; 130 reg = <0x30>;
131 };
132 };
133 sata@a0000 {
134 nr-ports = <2>;
135 status = "okay";
136 };
137 usb@50000 {
138 status = "okay";
139 };
140 usb@51000 {
141 status = "okay";
130 }; 142 };
131 };
132 sata@d00a0000 {
133 nr-ports = <2>;
134 status = "okay";
135 };
136 usb@d0050000 {
137 status = "okay";
138 };
139 usb@d0051000 {
140 status = "okay";
141 };
142 143
143 devbus-bootcs@d0010400 { 144 devbus-bootcs@10400 {
144 status = "okay"; 145 status = "okay";
145 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ 146 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
146 147
147 /* Device Bus parameters are required */ 148 /* Device Bus parameters are required */
148 149
149 /* Read parameters */ 150 /* Read parameters */
150 devbus,bus-width = <8>; 151 devbus,bus-width = <8>;
151 devbus,turn-off-ps = <60000>; 152 devbus,turn-off-ps = <60000>;
152 devbus,badr-skew-ps = <0>; 153 devbus,badr-skew-ps = <0>;
153 devbus,acc-first-ps = <124000>; 154 devbus,acc-first-ps = <124000>;
154 devbus,acc-next-ps = <248000>; 155 devbus,acc-next-ps = <248000>;
155 devbus,rd-setup-ps = <0>; 156 devbus,rd-setup-ps = <0>;
156 devbus,rd-hold-ps = <0>; 157 devbus,rd-hold-ps = <0>;
157 158
158 /* Write parameters */ 159 /* Write parameters */
159 devbus,sync-enable = <0>; 160 devbus,sync-enable = <0>;
160 devbus,wr-high-ps = <60000>; 161 devbus,wr-high-ps = <60000>;
161 devbus,wr-low-ps = <60000>; 162 devbus,wr-low-ps = <60000>;
162 devbus,ale-wr-ps = <60000>; 163 devbus,ale-wr-ps = <60000>;
163 164
164 /* NOR 128 MiB */ 165 /* NOR 128 MiB */
165 nor@0 { 166 nor@0 {
166 compatible = "cfi-flash"; 167 compatible = "cfi-flash";
167 reg = <0 0x8000000>; 168 reg = <0 0x8000000>;
168 bank-width = <2>; 169 bank-width = <2>;
170 };
169 }; 171 };
170 };
171 172
172 pcie-controller { 173 pcie-controller {
173 status = "okay";
174 /* Internal mini-PCIe connector */
175 pcie@1,0 {
176 /* Port 0, Lane 0 */
177 status = "okay"; 174 status = "okay";
175 /* Internal mini-PCIe connector */
176 pcie@1,0 {
177 /* Port 0, Lane 0 */
178 status = "okay";
179 };
178 }; 180 };
179 }; 181 };
180 }; 182 };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 29dfeb6d4a26..bacab11c10dc 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,140 +22,140 @@
22 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24 24
25 L2: l2-cache { 25 soc {
26 compatible = "marvell,aurora-system-cache"; 26 internal-regs {
27 reg = <0xd0008000 0x1000>; 27 L2: l2-cache {
28 cache-id-part = <0x100>; 28 compatible = "marvell,aurora-system-cache";
29 wt-override; 29 reg = <0x08000 0x1000>;
30 }; 30 cache-id-part = <0x100>;
31 wt-override;
32 };
31 33
32 mpic: interrupt-controller@d0020000 { 34 mpic: interrupt-controller@20000 {
33 reg = <0xd0020a00 0x2d0>, 35 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
34 <0xd0021070 0x58>; 36 };
35 };
36 37
37 armada-370-xp-pmsu@d0022000 { 38 armada-370-xp-pmsu@22000 {
38 compatible = "marvell,armada-370-xp-pmsu"; 39 compatible = "marvell,armada-370-xp-pmsu";
39 reg = <0xd0022100 0x430>, 40 reg = <0x22100 0x430>, <0x20800 0x20>;
40 <0xd0020800 0x20>; 41 };
41 };
42 42
43 soc { 43 serial@12200 {
44 serial@d0012200 {
45 compatible = "snps,dw-apb-uart"; 44 compatible = "snps,dw-apb-uart";
46 reg = <0xd0012200 0x100>; 45 reg = <0x12200 0x100>;
47 reg-shift = <2>; 46 reg-shift = <2>;
48 interrupts = <43>; 47 interrupts = <43>;
49 reg-io-width = <1>; 48 reg-io-width = <1>;
50 status = "disabled"; 49 status = "disabled";
51 }; 50 };
52 serial@d0012300 { 51 serial@12300 {
53 compatible = "snps,dw-apb-uart"; 52 compatible = "snps,dw-apb-uart";
54 reg = <0xd0012300 0x100>; 53 reg = <0x12300 0x100>;
55 reg-shift = <2>; 54 reg-shift = <2>;
56 interrupts = <44>; 55 interrupts = <44>;
57 reg-io-width = <1>; 56 reg-io-width = <1>;
58 status = "disabled"; 57 status = "disabled";
59 }; 58 };
60 59
61 timer@d0020300 { 60 timer@20300 {
62 marvell,timer-25Mhz; 61 marvell,timer-25Mhz;
63 }; 62 };
64 63
65 coreclk: mvebu-sar@d0018230 { 64 coreclk: mvebu-sar@18230 {
66 compatible = "marvell,armada-xp-core-clock"; 65 compatible = "marvell,armada-xp-core-clock";
67 reg = <0xd0018230 0x08>; 66 reg = <0x18230 0x08>;
68 #clock-cells = <1>; 67 #clock-cells = <1>;
69 }; 68 };
70 69
71 cpuclk: clock-complex@d0018700 { 70 cpuclk: clock-complex@18700 {
72 #clock-cells = <1>; 71 #clock-cells = <1>;
73 compatible = "marvell,armada-xp-cpu-clock"; 72 compatible = "marvell,armada-xp-cpu-clock";
74 reg = <0xd0018700 0xA0>; 73 reg = <0x18700 0xA0>;
75 clocks = <&coreclk 1>; 74 clocks = <&coreclk 1>;
76 }; 75 };
77 76
78 gateclk: clock-gating-control@d0018220 { 77 gateclk: clock-gating-control@18220 {
79 compatible = "marvell,armada-xp-gating-clock"; 78 compatible = "marvell,armada-xp-gating-clock";
80 reg = <0xd0018220 0x4>; 79 reg = <0x18220 0x4>;
81 clocks = <&coreclk 0>; 80 clocks = <&coreclk 0>;
82 #clock-cells = <1>; 81 #clock-cells = <1>;
83 }; 82 };
84 83
85 system-controller@d0018200 { 84 system-controller@18200 {
86 compatible = "marvell,armada-370-xp-system-controller"; 85 compatible = "marvell,armada-370-xp-system-controller";
87 reg = <0xd0018200 0x500>; 86 reg = <0x18200 0x500>;
88 }; 87 };
89 88
90 ethernet@d0030000 { 89 ethernet@30000 {
91 compatible = "marvell,armada-370-neta"; 90 compatible = "marvell,armada-370-neta";
92 reg = <0xd0030000 0x2500>; 91 reg = <0x30000 0x2500>;
93 interrupts = <12>; 92 interrupts = <12>;
94 clocks = <&gateclk 2>; 93 clocks = <&gateclk 2>;
95 status = "disabled"; 94 status = "disabled";
96 };
97
98 xor@d0060900 {
99 compatible = "marvell,orion-xor";
100 reg = <0xd0060900 0x100
101 0xd0060b00 0x100>;
102 clocks = <&gateclk 22>;
103 status = "okay";
104
105 xor10 {
106 interrupts = <51>;
107 dmacap,memcpy;
108 dmacap,xor;
109 };
110 xor11 {
111 interrupts = <52>;
112 dmacap,memcpy;
113 dmacap,xor;
114 dmacap,memset;
115 }; 95 };
116 };
117 96
118 xor@d00f0900 { 97 xor@60900 {
119 compatible = "marvell,orion-xor"; 98 compatible = "marvell,orion-xor";
120 reg = <0xd00F0900 0x100 99 reg = <0x60900 0x100
121 0xd00F0B00 0x100>; 100 0x60b00 0x100>;
122 clocks = <&gateclk 28>; 101 clocks = <&gateclk 22>;
123 status = "okay"; 102 status = "okay";
124 103
125 xor00 { 104 xor10 {
126 interrupts = <94>; 105 interrupts = <51>;
127 dmacap,memcpy; 106 dmacap,memcpy;
128 dmacap,xor; 107 dmacap,xor;
108 };
109 xor11 {
110 interrupts = <52>;
111 dmacap,memcpy;
112 dmacap,xor;
113 dmacap,memset;
114 };
129 }; 115 };
130 xor01 { 116
131 interrupts = <95>; 117 xor@f0900 {
132 dmacap,memcpy; 118 compatible = "marvell,orion-xor";
133 dmacap,xor; 119 reg = <0xF0900 0x100
134 dmacap,memset; 120 0xF0B00 0x100>;
121 clocks = <&gateclk 28>;
122 status = "okay";
123
124 xor00 {
125 interrupts = <94>;
126 dmacap,memcpy;
127 dmacap,xor;
128 };
129 xor01 {
130 interrupts = <95>;
131 dmacap,memcpy;
132 dmacap,xor;
133 dmacap,memset;
134 };
135 }; 135 };
136 };
137 136
138 usb@d0050000 { 137 usb@50000 {
139 clocks = <&gateclk 18>; 138 clocks = <&gateclk 18>;
140 }; 139 };
141 140
142 usb@d0051000 { 141 usb@51000 {
143 clocks = <&gateclk 19>; 142 clocks = <&gateclk 19>;
144 }; 143 };
145 144
146 usb@d0052000 { 145 usb@52000 {
147 compatible = "marvell,orion-ehci"; 146 compatible = "marvell,orion-ehci";
148 reg = <0xd0052000 0x500>; 147 reg = <0x52000 0x500>;
149 interrupts = <47>; 148 interrupts = <47>;
150 clocks = <&gateclk 20>; 149 clocks = <&gateclk 20>;
151 status = "disabled"; 150 status = "disabled";
152 }; 151 };
153 152
154 thermal@d00182b0 { 153 thermal@182b0 {
155 compatible = "marvell,armadaxp-thermal"; 154 compatible = "marvell,armadaxp-thermal";
156 reg = <0xd00182b0 0x4 155 reg = <0x182b0 0x4
157 0xd00184d0 0x4>; 156 0x184d0 0x4>;
158 status = "okay"; 157 status = "okay";
158 };
159 }; 159 };
160 }; 160 };
161}; 161};
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index 62eceb4f0d3f..0a61bbb9102f 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -19,11 +19,19 @@
19 chosen { 19 chosen {
20 }; 20 };
21 21
22 pinctrl@11400000 {
23 /*
24 * Disabled pullups since external part has its own pullups and
25 * double-pulling gets us out of spec in some cases.
26 */
27 i2c2_bus: i2c2-bus {
28 samsung,pin-pud = <0>;
29 };
30 };
31
22 i2c@12C60000 { 32 i2c@12C60000 {
23 samsung,i2c-sda-delay = <100>; 33 samsung,i2c-sda-delay = <100>;
24 samsung,i2c-max-bus-freq = <378000>; 34 samsung,i2c-max-bus-freq = <378000>;
25 gpios = <&gpb3 0 2 3 0>,
26 <&gpb3 1 2 3 0>;
27 35
28 max77686@09 { 36 max77686@09 {
29 compatible = "maxim,max77686"; 37 compatible = "maxim,max77686";
@@ -167,21 +175,12 @@
167 i2c@12C70000 { 175 i2c@12C70000 {
168 samsung,i2c-sda-delay = <100>; 176 samsung,i2c-sda-delay = <100>;
169 samsung,i2c-max-bus-freq = <378000>; 177 samsung,i2c-max-bus-freq = <378000>;
170 gpios = <&gpb3 2 2 3 0>,
171 <&gpb3 3 2 3 0>;
172 }; 178 };
173 179
174 i2c@12C80000 { 180 i2c@12C80000 {
175 samsung,i2c-sda-delay = <100>; 181 samsung,i2c-sda-delay = <100>;
176 samsung,i2c-max-bus-freq = <66000>; 182 samsung,i2c-max-bus-freq = <66000>;
177 183
178 /*
179 * Disabled pullups since external part has its own pullups and
180 * double-pulling gets us out of spec in some cases.
181 */
182 gpios = <&gpa0 6 3 0 0>,
183 <&gpa0 7 3 0 0>;
184
185 hdmiddc@50 { 184 hdmiddc@50 {
186 compatible = "samsung,exynos5-hdmiddc"; 185 compatible = "samsung,exynos5-hdmiddc";
187 reg = <0x50>; 186 reg = <0x50>;
@@ -191,19 +190,16 @@
191 i2c@12C90000 { 190 i2c@12C90000 {
192 samsung,i2c-sda-delay = <100>; 191 samsung,i2c-sda-delay = <100>;
193 samsung,i2c-max-bus-freq = <66000>; 192 samsung,i2c-max-bus-freq = <66000>;
194 gpios = <&gpa1 2 3 3 0>,
195 <&gpa1 3 3 3 0>;
196 }; 193 };
197 194
198 i2c@12CA0000 { 195 i2c@12CA0000 {
199 status = "disabled"; 196 samsung,i2c-sda-delay = <100>;
197 samsung,i2c-max-bus-freq = <66000>;
200 }; 198 };
201 199
202 i2c@12CB0000 { 200 i2c@12CB0000 {
203 samsung,i2c-sda-delay = <100>; 201 samsung,i2c-sda-delay = <100>;
204 samsung,i2c-max-bus-freq = <66000>; 202 samsung,i2c-max-bus-freq = <66000>;
205 gpios = <&gpa2 2 3 3 0>,
206 <&gpa2 3 3 3 0>;
207 }; 203 };
208 204
209 i2c@12CC0000 { 205 i2c@12CC0000 {
@@ -213,8 +209,6 @@
213 i2c@12CD0000 { 209 i2c@12CD0000 {
214 samsung,i2c-sda-delay = <100>; 210 samsung,i2c-sda-delay = <100>;
215 samsung,i2c-max-bus-freq = <66000>; 211 samsung,i2c-max-bus-freq = <66000>;
216 gpios = <&gpb2 2 3 3 0>,
217 <&gpb2 3 3 3 0>;
218 }; 212 };
219 213
220 i2c@12CE0000 { 214 i2c@12CE0000 {
@@ -236,15 +230,12 @@
236 samsung,dw-mshc-ciu-div = <3>; 230 samsung,dw-mshc-ciu-div = <3>;
237 samsung,dw-mshc-sdr-timing = <2 3>; 231 samsung,dw-mshc-sdr-timing = <2 3>;
238 samsung,dw-mshc-ddr-timing = <1 2>; 232 samsung,dw-mshc-ddr-timing = <1 2>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
239 235
240 slot@0 { 236 slot@0 {
241 reg = <0>; 237 reg = <0>;
242 bus-width = <8>; 238 bus-width = <8>;
243 gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
244 <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
245 <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
246 <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
247 <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
248 }; 239 };
249 }; 240 };
250 241
@@ -260,15 +251,13 @@
260 samsung,dw-mshc-ciu-div = <3>; 251 samsung,dw-mshc-ciu-div = <3>;
261 samsung,dw-mshc-sdr-timing = <2 3>; 252 samsung,dw-mshc-sdr-timing = <2 3>;
262 samsung,dw-mshc-ddr-timing = <1 2>; 253 samsung,dw-mshc-ddr-timing = <1 2>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
263 256
264 slot@0 { 257 slot@0 {
265 reg = <0>; 258 reg = <0>;
266 bus-width = <4>; 259 bus-width = <4>;
267 samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>; 260 wp-gpios = <&gpc2 1 0>;
268 wp-gpios = <&gpc2 1 0 0 3>;
269 gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
270 <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
271 <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
272 }; 261 };
273 }; 262 };
274 263
@@ -281,11 +270,11 @@
281 samsung,dw-mshc-ciu-div = <3>; 270 samsung,dw-mshc-ciu-div = <3>;
282 samsung,dw-mshc-sdr-timing = <2 3>; 271 samsung,dw-mshc-sdr-timing = <2 3>;
283 samsung,dw-mshc-ddr-timing = <1 2>; 272 samsung,dw-mshc-ddr-timing = <1 2>;
273 /* See board-specific dts files for pin setup */
284 274
285 slot@0 { 275 slot@0 {
286 reg = <0>; 276 reg = <0>;
287 bus-width = <4>; 277 bus-width = <4>;
288 /* See board-specific dts files for GPIOs */
289 }; 278 };
290 }; 279 };
291 280
@@ -294,9 +283,6 @@
294 }; 283 };
295 284
296 spi_1: spi@12d30000 { 285 spi_1: spi@12d30000 {
297 gpios = <&gpa2 4 2 3 0>,
298 <&gpa2 6 2 3 0>,
299 <&gpa2 7 2 3 0>;
300 samsung,spi-src-clk = <0>; 286 samsung,spi-src-clk = <0>;
301 num-cs = <1>; 287 num-cs = <1>;
302 }; 288 };
@@ -306,7 +292,7 @@
306 }; 292 };
307 293
308 hdmi { 294 hdmi {
309 hpd-gpio = <&gpx3 7 0xf 1 3>; 295 hpd-gpio = <&gpx3 7 0>;
310 }; 296 };
311 297
312 gpio-keys { 298 gpio-keys {
@@ -314,7 +300,7 @@
314 300
315 power { 301 power {
316 label = "Power"; 302 label = "Power";
317 gpios = <&gpx1 3 0 0x10000 0>; 303 gpios = <&gpx1 3 1>;
318 linux,code = <116>; /* KEY_POWER */ 304 linux,code = <116>; /* KEY_POWER */
319 gpio-key,wakeup; 305 gpio-key,wakeup;
320 }; 306 };
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c5834a6c5bf4..c914357c0d89 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -50,6 +50,46 @@
50 pinctrl-names = "default"; 50 pinctrl-names = "default";
51 pinctrl-0 = <&mmc0_pins>; 51 pinctrl-0 = <&mmc0_pins>;
52 }; 52 };
53 spi1: spi@1f0e000 {
54 status = "okay";
55 pinctrl-names = "default";
56 pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
57 flash: m25p80@0 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "m25p64";
61 spi-max-frequency = <30000000>;
62 reg = <0>;
63 partition@0 {
64 label = "U-Boot-SPL";
65 reg = <0x00000000 0x00010000>;
66 read-only;
67 };
68 partition@1 {
69 label = "U-Boot";
70 reg = <0x00010000 0x00080000>;
71 read-only;
72 };
73 partition@2 {
74 label = "U-Boot-Env";
75 reg = <0x00090000 0x00010000>;
76 read-only;
77 };
78 partition@3 {
79 label = "Kernel";
80 reg = <0x000a0000 0x00280000>;
81 };
82 partition@4 {
83 label = "Filesystem";
84 reg = <0x00320000 0x00400000>;
85 };
86 partition@5 {
87 label = "MAC-Address";
88 reg = <0x007f0000 0x00010000>;
89 read-only;
90 };
91 };
92 };
53 }; 93 };
54 nand_cs3@62000000 { 94 nand_cs3@62000000 {
55 status = "okay"; 95 status = "okay";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 3ade343f13cc..2c88313d2c7a 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -71,6 +71,60 @@
71 0x28 0x00222222 0x00ffffff 71 0x28 0x00222222 0x00ffffff
72 >; 72 >;
73 }; 73 };
74 ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
75 pinctrl-single,bits = <
76 /* EPWM0A */
77 0xc 0x00000002 0x0000000f
78 >;
79 };
80 ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
81 pinctrl-single,bits = <
82 /* EPWM0B */
83 0xc 0x00000020 0x000000f0
84 >;
85 };
86 ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
87 pinctrl-single,bits = <
88 /* EPWM1A */
89 0x14 0x00000002 0x0000000f
90 >;
91 };
92 ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
93 pinctrl-single,bits = <
94 /* EPWM1B */
95 0x14 0x00000020 0x000000f0
96 >;
97 };
98 ecap0_pins: pinmux_ecap0_pins {
99 pinctrl-single,bits = <
100 /* ECAP0_APWM0 */
101 0x8 0x20000000 0xf0000000
102 >;
103 };
104 ecap1_pins: pinmux_ecap1_pins {
105 pinctrl-single,bits = <
106 /* ECAP1_APWM1 */
107 0x4 0x40000000 0xf0000000
108 >;
109 };
110 ecap2_pins: pinmux_ecap2_pins {
111 pinctrl-single,bits = <
112 /* ECAP2_APWM2 */
113 0x4 0x00000004 0x0000000f
114 >;
115 };
116 spi1_pins: pinmux_spi_pins {
117 pinctrl-single,bits = <
118 /* SIMO, SOMI, CLK */
119 0x14 0x00110100 0x00ff0f00
120 >;
121 };
122 spi1_cs0_pin: pinmux_spi1_cs0 {
123 pinctrl-single,bits = <
124 /* CS0 */
125 0x14 0x00000010 0x000000f0
126 >;
127 };
74 }; 128 };
75 serial0: serial@1c42000 { 129 serial0: serial@1c42000 {
76 compatible = "ns16550a"; 130 compatible = "ns16550a";
@@ -122,6 +176,46 @@
122 interrupts = <16>; 176 interrupts = <16>;
123 status = "disabled"; 177 status = "disabled";
124 }; 178 };
179 ehrpwm0: ehrpwm@01f00000 {
180 compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
181 #pwm-cells = <3>;
182 reg = <0x300000 0x2000>;
183 status = "disabled";
184 };
185 ehrpwm1: ehrpwm@01f02000 {
186 compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
187 #pwm-cells = <3>;
188 reg = <0x302000 0x2000>;
189 status = "disabled";
190 };
191 ecap0: ecap@01f06000 {
192 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
193 #pwm-cells = <3>;
194 reg = <0x306000 0x80>;
195 status = "disabled";
196 };
197 ecap1: ecap@01f07000 {
198 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
199 #pwm-cells = <3>;
200 reg = <0x307000 0x80>;
201 status = "disabled";
202 };
203 ecap2: ecap@01f08000 {
204 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
205 #pwm-cells = <3>;
206 reg = <0x308000 0x80>;
207 status = "disabled";
208 };
209 spi1: spi@1f0e000 {
210 #address-cells = <1>;
211 #size-cells = <0>;
212 compatible = "ti,da830-spi";
213 reg = <0x30e000 0x1000>;
214 num-cs = <4>;
215 ti,davinci-spi-intr-line = <1>;
216 interrupts = <56>;
217 status = "disabled";
218 };
125 }; 219 };
126 nand_cs3@62000000 { 220 nand_cs3@62000000 {
127 compatible = "ti,davinci-nand"; 221 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 9ac47d51c407..7cfbbd3b7732 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -38,6 +38,11 @@
38 i2c7 = &i2c_7; 38 i2c7 = &i2c_7;
39 }; 39 };
40 40
41 chipid@10000000 {
42 compatible = "samsung,exynos4210-chipid";
43 reg = <0x10000000 0x100>;
44 };
45
41 pd_mfc: mfc-power-domain@10023C40 { 46 pd_mfc: mfc-power-domain@10023C40 {
42 compatible = "samsung,exynos4210-pd"; 47 compatible = "samsung,exynos4210-pd";
43 reg = <0x10023C40 0x20>; 48 reg = <0x10023C40 0x20>;
@@ -82,6 +87,11 @@
82 reg = <0x10440000 0x1000>; 87 reg = <0x10440000 0x1000>;
83 }; 88 };
84 89
90 sys_reg: sysreg {
91 compatible = "samsung,exynos4-sysreg", "syscon";
92 reg = <0x10010000 0x400>;
93 };
94
85 watchdog@10060000 { 95 watchdog@10060000 {
86 compatible = "samsung,s3c2410-wdt"; 96 compatible = "samsung,s3c2410-wdt";
87 reg = <0x10060000 0x100>; 97 reg = <0x10060000 0x100>;
@@ -197,6 +207,8 @@
197 interrupts = <0 58 0>; 207 interrupts = <0 58 0>;
198 clocks = <&clock 317>; 208 clocks = <&clock 317>;
199 clock-names = "i2c"; 209 clock-names = "i2c";
210 pinctrl-names = "default";
211 pinctrl-0 = <&i2c0_bus>;
200 status = "disabled"; 212 status = "disabled";
201 }; 213 };
202 214
@@ -208,6 +220,8 @@
208 interrupts = <0 59 0>; 220 interrupts = <0 59 0>;
209 clocks = <&clock 318>; 221 clocks = <&clock 318>;
210 clock-names = "i2c"; 222 clock-names = "i2c";
223 pinctrl-names = "default";
224 pinctrl-0 = <&i2c1_bus>;
211 status = "disabled"; 225 status = "disabled";
212 }; 226 };
213 227
@@ -287,6 +301,8 @@
287 #size-cells = <0>; 301 #size-cells = <0>;
288 clocks = <&clock 327>, <&clock 159>; 302 clocks = <&clock 327>, <&clock 159>;
289 clock-names = "spi", "spi_busclk0"; 303 clock-names = "spi", "spi_busclk0";
304 pinctrl-names = "default";
305 pinctrl-0 = <&spi0_bus>;
290 status = "disabled"; 306 status = "disabled";
291 }; 307 };
292 308
@@ -300,6 +316,8 @@
300 #size-cells = <0>; 316 #size-cells = <0>;
301 clocks = <&clock 328>, <&clock 160>; 317 clocks = <&clock 328>, <&clock 160>;
302 clock-names = "spi", "spi_busclk0"; 318 clock-names = "spi", "spi_busclk0";
319 pinctrl-names = "default";
320 pinctrl-0 = <&spi1_bus>;
303 status = "disabled"; 321 status = "disabled";
304 }; 322 };
305 323
@@ -313,6 +331,8 @@
313 #size-cells = <0>; 331 #size-cells = <0>;
314 clocks = <&clock 329>, <&clock 161>; 332 clocks = <&clock 329>, <&clock 161>;
315 clock-names = "spi", "spi_busclk0"; 333 clock-names = "spi", "spi_busclk0";
334 pinctrl-names = "default";
335 pinctrl-0 = <&spi2_bus>;
316 status = "disabled"; 336 status = "disabled";
317 }; 337 };
318 338
@@ -356,4 +376,16 @@
356 #dma-requests = <1>; 376 #dma-requests = <1>;
357 }; 377 };
358 }; 378 };
379
380 fimd: fimd@11c00000 {
381 compatible = "samsung,exynos4210-fimd";
382 interrupt-parent = <&combiner>;
383 reg = <0x11c00000 0x20000>;
384 interrupt-names = "fifo", "vsync", "lcd_sys";
385 interrupts = <11 0>, <11 1>, <11 2>;
386 clocks = <&clock 140>, <&clock 283>;
387 clock-names = "sclk_fimd", "fimd";
388 samsung,power-domain = <&pd_lcd0>;
389 status = "disabled";
390 };
359}; 391};
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 1b30bc8e2654..524b90846df5 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -57,6 +57,10 @@
57 status = "okay"; 57 status = "okay";
58 }; 58 };
59 59
60 g2d@12800000 {
61 status = "okay";
62 };
63
60 codec@13400000 { 64 codec@13400000 {
61 samsung,mfc-r = <0x43000000 0x800000>; 65 samsung,mfc-r = <0x43000000 0x800000>;
62 samsung,mfc-l = <0x51000000 0x800000>; 66 samsung,mfc-l = <0x51000000 0x800000>;
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index f52c86e2d424..91332b72acf5 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -30,16 +30,13 @@
30 }; 30 };
31 31
32 sdhci@12530000 { 32 sdhci@12530000 {
33 samsung,sdhci-bus-width = <4>; 33 bus-width = <4>;
34 linux,mmc_cap_4_bit_data; 34 pinctrl-names = "default";
35 samsung,sdhci-cd-internal; 35 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
36 gpio-cd = <&gpk2 2 2 3 3>; 36 status = "okay";
37 gpios = <&gpk2 0 2 0 3>, 37 };
38 <&gpk2 1 2 0 3>, 38
39 <&gpk2 3 2 3 3>, 39 g2d@12800000 {
40 <&gpk2 4 2 3 3>,
41 <&gpk2 5 2 3 3>,
42 <&gpk2 6 2 3 3>;
43 status = "okay"; 40 status = "okay";
44 }; 41 };
45 42
@@ -65,25 +62,32 @@
65 status = "okay"; 62 status = "okay";
66 }; 63 };
67 64
65 pinctrl@11000000 {
66 keypad_rows: keypad-rows {
67 samsung,pins = "gpx2-0", "gpx2-1";
68 samsung,pin-function = <3>;
69 samsung,pin-pud = <3>;
70 samsung,pin-drv = <0>;
71 };
72
73 keypad_cols: keypad-cols {
74 samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
75 "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7";
76 samsung,pin-function = <3>;
77 samsung,pin-pud = <0>;
78 samsung,pin-drv = <0>;
79 };
80 };
81
68 keypad@100A0000 { 82 keypad@100A0000 {
69 samsung,keypad-num-rows = <2>; 83 samsung,keypad-num-rows = <2>;
70 samsung,keypad-num-columns = <8>; 84 samsung,keypad-num-columns = <8>;
71 linux,keypad-no-autorepeat; 85 linux,keypad-no-autorepeat;
72 linux,keypad-wakeup; 86 linux,keypad-wakeup;
87 pinctrl-names = "default";
88 pinctrl-0 = <&keypad_rows &keypad_cols>;
73 status = "okay"; 89 status = "okay";
74 90
75 row-gpios = <&gpx2 0 3 3 0>,
76 <&gpx2 1 3 3 0>;
77
78 col-gpios = <&gpx1 0 3 0 0>,
79 <&gpx1 1 3 0 0>,
80 <&gpx1 2 3 0 0>,
81 <&gpx1 3 3 0 0>,
82 <&gpx1 4 3 0 0>,
83 <&gpx1 5 3 0 0>,
84 <&gpx1 6 3 0 0>,
85 <&gpx1 7 3 0 0>;
86
87 key_1 { 91 key_1 {
88 keypad,row = <0>; 92 keypad,row = <0>;
89 keypad,column = <3>; 93 keypad,column = <3>;
@@ -149,9 +153,7 @@
149 #address-cells = <1>; 153 #address-cells = <1>;
150 #size-cells = <0>; 154 #size-cells = <0>;
151 samsung,i2c-sda-delay = <100>; 155 samsung,i2c-sda-delay = <100>;
152 samsung,i2c-max-bus-freq = <20000>; 156 samsung,i2c-max-bus-freq = <100000>;
153 gpios = <&gpd1 0 2 3 0>,
154 <&gpd1 1 2 3 0>;
155 status = "okay"; 157 status = "okay";
156 158
157 eeprom@50 { 159 eeprom@50 {
@@ -166,9 +168,6 @@
166 }; 168 };
167 169
168 spi_2: spi@13940000 { 170 spi_2: spi@13940000 {
169 gpios = <&gpc1 1 5 3 0>,
170 <&gpc1 3 5 3 0>,
171 <&gpc1 4 5 3 0>;
172 status = "okay"; 171 status = "okay";
173 172
174 w25x80@0 { 173 w25x80@0 {
@@ -179,7 +178,7 @@
179 spi-max-frequency = <1000000>; 178 spi-max-frequency = <1000000>;
180 179
181 controller-data { 180 controller-data {
182 cs-gpio = <&gpc1 2 1 0 3>; 181 cs-gpio = <&gpc1 2 0>;
183 samsung,spi-feedback-delay = <0>; 182 samsung,spi-feedback-delay = <0>;
184 }; 183 };
185 184
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 15143bdbafb8..66e6b03bf35e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -112,4 +112,11 @@
112 reg = <0x100C0000 0x100>; 112 reg = <0x100C0000 0x100>;
113 interrupts = <2 4>; 113 interrupts = <2 4>;
114 }; 114 };
115
116 g2d@12800000 {
117 compatible = "samsung,s5pv210-g2d";
118 reg = <0x12800000 0x1000>;
119 interrupts = <0 89 0>;
120 status = "disabled";
121 };
115}; 122};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 1fecf7666dc0..1c21bad32ca9 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -72,6 +72,27 @@
72 status = "okay"; 72 status = "okay";
73 }; 73 };
74 74
75 fimd@11c00000 {
76 pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
77 pinctrl-names = "default";
78 status = "okay";
79 };
80
81 display-timings {
82 native-mode = <&timing0>;
83 timing0: timing {
84 clock-frequency = <50000>;
85 hactive = <1024>;
86 vactive = <600>;
87 hfront-porch = <64>;
88 hback-porch = <16>;
89 hsync-len = <48>;
90 vback-porch = <64>;
91 vfront-porch = <16>;
92 vsync-len = <3>;
93 };
94 };
95
75 serial@13800000 { 96 serial@13800000 {
76 status = "okay"; 97 status = "okay";
77 }; 98 };
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index 874beeaef99d..dd564310d4a5 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -27,6 +27,14 @@
27 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; 27 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
28 }; 28 };
29 29
30 g2d@10800000 {
31 status = "okay";
32 };
33
34 g2d@10800000 {
35 status = "okay";
36 };
37
30 sdhci@12530000 { 38 sdhci@12530000 {
31 bus-width = <4>; 39 bus-width = <4>;
32 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; 40 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d75c047e80a9..7f428272fee6 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -51,4 +51,12 @@
51 <0x7 0 &gic 1 12 0>; 51 <0x7 0 &gic 1 12 0>;
52 }; 52 };
53 }; 53 };
54
55 mshc@12550000 {
56 compatible = "samsung,exynos4412-dw-mshc";
57 reg = <0x12550000 0x1000>;
58 interrupts = <0 77 0>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 };
54}; 62};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 7496b8d633ea..e3380a7a285c 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -72,4 +72,11 @@
72 reg = <0x106E0000 0x1000>; 72 reg = <0x106E0000 0x1000>;
73 interrupts = <0 72 0>; 73 interrupts = <0 72 0>;
74 }; 74 };
75
76 g2d@10800000 {
77 compatible = "samsung,exynos4212-g2d";
78 reg = <0x10800000 0x1000>;
79 interrupts = <0 89 0>;
80 status = "disabled";
81 };
75}; 82};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 5de019cb0e58..02cfc76d002f 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -24,8 +24,266 @@
24 bootargs = "console=ttySAC2,115200"; 24 bootargs = "console=ttySAC2,115200";
25 }; 25 };
26 26
27 codec@11000000 {
28 samsung,mfc-r = <0x43000000 0x800000>;
29 samsung,mfc-l = <0x51000000 0x800000>;
30 };
31
27 i2c@12C60000 { 32 i2c@12C60000 {
28 status = "disabled"; 33 samsung,i2c-sda-delay = <100>;
34 samsung,i2c-max-bus-freq = <20000>;
35 samsung,i2c-slave-addr = <0x66>;
36
37 s5m8767_pmic@66 {
38 compatible = "samsung,s5m8767-pmic";
39 reg = <0x66>;
40
41 s5m8767,pmic-buck2-dvs-voltage = <1300000>;
42 s5m8767,pmic-buck3-dvs-voltage = <1100000>;
43 s5m8767,pmic-buck4-dvs-voltage = <1200000>;
44 s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>,
45 <&gpd1 1 0>,
46 <&gpd1 2 0>;
47 s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>,
48 <&gpx2 4 0>,
49 <&gpx2 5 0>;
50 regulators {
51 ldo1_reg: LDO1 {
52 regulator-name = "VDD_ALIVE_1.0V";
53 regulator-min-microvolt = <1100000>;
54 regulator-max-microvolt = <1100000>;
55 regulator-always-on;
56 regulator-boot-on;
57 op_mode = <1>;
58 };
59
60 ldo2_reg: LDO2 {
61 regulator-name = "VDD_28IO_DP_1.35V";
62 regulator-min-microvolt = <1200000>;
63 regulator-max-microvolt = <1200000>;
64 regulator-always-on;
65 regulator-boot-on;
66 op_mode = <1>;
67 };
68
69 ldo3_reg: LDO3 {
70 regulator-name = "VDD_COMMON1_1.8V";
71 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <1800000>;
73 regulator-always-on;
74 regulator-boot-on;
75 op_mode = <1>;
76 };
77
78 ldo4_reg: LDO4 {
79 regulator-name = "VDD_IOPERI_1.8V";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <1800000>;
82 op_mode = <1>;
83 };
84
85 ldo5_reg: LDO5 {
86 regulator-name = "VDD_EXT_1.8V";
87 regulator-min-microvolt = <1800000>;
88 regulator-max-microvolt = <1800000>;
89 regulator-always-on;
90 regulator-boot-on;
91 op_mode = <1>;
92 };
93
94 ldo6_reg: LDO6 {
95 regulator-name = "VDD_MPLL_1.1V";
96 regulator-min-microvolt = <1100000>;
97 regulator-max-microvolt = <1100000>;
98 regulator-always-on;
99 regulator-boot-on;
100 op_mode = <1>;
101 };
102
103 ldo7_reg: LDO7 {
104 regulator-name = "VDD_XPLL_1.1V";
105 regulator-min-microvolt = <1100000>;
106 regulator-max-microvolt = <1100000>;
107 regulator-always-on;
108 regulator-boot-on;
109 op_mode = <1>;
110 };
111
112 ldo8_reg: LDO8 {
113 regulator-name = "VDD_COMMON2_1.0V";
114 regulator-min-microvolt = <1000000>;
115 regulator-max-microvolt = <1000000>;
116 regulator-always-on;
117 regulator-boot-on;
118 op_mode = <1>;
119 };
120
121 ldo9_reg: LDO9 {
122 regulator-name = "VDD_33ON_3.0V";
123 regulator-min-microvolt = <3000000>;
124 regulator-max-microvolt = <3000000>;
125 op_mode = <1>;
126 };
127
128 ldo10_reg: LDO10 {
129 regulator-name = "VDD_COMMON3_1.8V";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <1800000>;
132 regulator-always-on;
133 regulator-boot-on;
134 op_mode = <1>;
135 };
136
137 ldo11_reg: LDO11 {
138 regulator-name = "VDD_ABB2_1.8V";
139 regulator-min-microvolt = <1800000>;
140 regulator-max-microvolt = <1800000>;
141 regulator-always-on;
142 regulator-boot-on;
143 op_mode = <1>;
144 };
145
146 ldo12_reg: LDO12 {
147 regulator-name = "VDD_USB_3.0V";
148 regulator-min-microvolt = <3000000>;
149 regulator-max-microvolt = <3000000>;
150 regulator-always-on;
151 regulator-boot-on;
152 op_mode = <1>;
153 };
154
155 ldo13_reg: LDO13 {
156 regulator-name = "VDDQ_C2C_W_1.8V";
157 regulator-min-microvolt = <1800000>;
158 regulator-max-microvolt = <1800000>;
159 regulator-always-on;
160 regulator-boot-on;
161 op_mode = <1>;
162 };
163
164 ldo14_reg: LDO14 {
165 regulator-name = "VDD18_ABB0_3_1.8V";
166 regulator-min-microvolt = <1800000>;
167 regulator-max-microvolt = <1800000>;
168 regulator-always-on;
169 regulator-boot-on;
170 op_mode = <1>;
171 };
172
173 ldo15_reg: LDO15 {
174 regulator-name = "VDD10_COMMON4_1.0V";
175 regulator-min-microvolt = <1000000>;
176 regulator-max-microvolt = <1000000>;
177 regulator-always-on;
178 regulator-boot-on;
179 op_mode = <1>;
180 };
181
182 ldo16_reg: LDO16 {
183 regulator-name = "VDD18_HSIC_1.8V";
184 regulator-min-microvolt = <1800000>;
185 regulator-max-microvolt = <1800000>;
186 regulator-always-on;
187 regulator-boot-on;
188 op_mode = <1>;
189 };
190
191 ldo17_reg: LDO17 {
192 regulator-name = "VDDQ_MMC2_3_2.8V";
193 regulator-min-microvolt = <2800000>;
194 regulator-max-microvolt = <2800000>;
195 regulator-always-on;
196 regulator-boot-on;
197 op_mode = <1>;
198 };
199
200 ldo18_reg: LDO18 {
201 regulator-name = "VDD_33ON_2.8V";
202 regulator-min-microvolt = <2800000>;
203 regulator-max-microvolt = <2800000>;
204 op_mode = <1>;
205 };
206
207 ldo22_reg: LDO22 {
208 regulator-name = "EXT_33_OFF";
209 regulator-min-microvolt = <3300000>;
210 regulator-max-microvolt = <3300000>;
211 op_mode = <1>;
212 };
213
214 ldo23_reg: LDO23 {
215 regulator-name = "EXT_28_OFF";
216 regulator-min-microvolt = <2800000>;
217 regulator-max-microvolt = <2800000>;
218 op_mode = <1>;
219 };
220
221 ldo25_reg: LDO25 {
222 regulator-name = "PVDD_LDO25";
223 regulator-min-microvolt = <1200000>;
224 regulator-max-microvolt = <1200000>;
225 op_mode = <1>;
226 };
227
228 ldo26_reg: LDO26 {
229 regulator-name = "EXT_18_OFF";
230 regulator-min-microvolt = <1800000>;
231 regulator-max-microvolt = <1800000>;
232 op_mode = <1>;
233 };
234
235 buck1_reg: BUCK1 {
236 regulator-name = "vdd_mif";
237 regulator-min-microvolt = <950000>;
238 regulator-max-microvolt = <1200000>;
239 regulator-always-on;
240 regulator-boot-on;
241 op_mode = <1>;
242 };
243
244 buck2_reg: BUCK2 {
245 regulator-name = "vdd_arm";
246 regulator-min-microvolt = <925000>;
247 regulator-max-microvolt = <1300000>;
248 regulator-always-on;
249 regulator-boot-on;
250 op_mode = <1>;
251 };
252
253 buck3_reg: BUCK3 {
254 regulator-name = "vdd_int";
255 regulator-min-microvolt = <900000>;
256 regulator-max-microvolt = <1200000>;
257 regulator-always-on;
258 regulator-boot-on;
259 op_mode = <1>;
260 };
261
262 buck4_reg: BUCK4 {
263 regulator-name = "vdd_g3d";
264 regulator-min-microvolt = <1000000>;
265 regulator-max-microvolt = <1000000>;
266 regulator-boot-on;
267 op_mode = <1>;
268 };
269
270 buck5_reg: BUCK5 {
271 regulator-name = "VDD_MEM_1.35V";
272 regulator-min-microvolt = <750000>;
273 regulator-max-microvolt = <1355000>;
274 regulator-always-on;
275 regulator-boot-on;
276 op_mode = <1>;
277 };
278
279 buck9_reg: BUCK9 {
280 regulator-name = "VDD_33_OFF_EXT1";
281 regulator-min-microvolt = <750000>;
282 regulator-max-microvolt = <3000000>;
283 op_mode = <1>;
284 };
285 };
286 };
29 }; 287 };
30 288
31 i2c@12C70000 { 289 i2c@12C70000 {
@@ -69,15 +327,13 @@
69 samsung,dw-mshc-ciu-div = <3>; 327 samsung,dw-mshc-ciu-div = <3>;
70 samsung,dw-mshc-sdr-timing = <2 3>; 328 samsung,dw-mshc-sdr-timing = <2 3>;
71 samsung,dw-mshc-ddr-timing = <1 2>; 329 samsung,dw-mshc-ddr-timing = <1 2>;
330 vmmc-supply = <&mmc_reg>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
72 333
73 slot@0 { 334 slot@0 {
74 reg = <0>; 335 reg = <0>;
75 bus-width = <8>; 336 bus-width = <8>;
76 gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
77 <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
78 <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
79 <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
80 <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
81 }; 337 };
82 }; 338 };
83 339
@@ -93,14 +349,14 @@
93 samsung,dw-mshc-ciu-div = <3>; 349 samsung,dw-mshc-ciu-div = <3>;
94 samsung,dw-mshc-sdr-timing = <2 3>; 350 samsung,dw-mshc-sdr-timing = <2 3>;
95 samsung,dw-mshc-ddr-timing = <1 2>; 351 samsung,dw-mshc-ddr-timing = <1 2>;
352 vmmc-supply = <&mmc_reg>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
96 355
97 slot@0 { 356 slot@0 {
98 reg = <0>; 357 reg = <0>;
99 bus-width = <4>; 358 bus-width = <4>;
100 samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>; 359 disable-wp;
101 gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
102 <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
103 <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
104 }; 360 };
105 }; 361 };
106 362
@@ -120,6 +376,73 @@
120 status = "disabled"; 376 status = "disabled";
121 }; 377 };
122 378
379 gpio_keys {
380 compatible = "gpio-keys";
381
382 menu {
383 label = "SW-TACT2";
384 gpios = <&gpx1 4 1>;
385 linux,code = <139>;
386 gpio-key,wakeup;
387 };
388
389 home {
390 label = "SW-TACT3";
391 gpios = <&gpx1 5 1>;
392 linux,code = <102>;
393 gpio-key,wakeup;
394 };
395
396 up {
397 label = "SW-TACT4";
398 gpios = <&gpx1 6 1>;
399 linux,code = <103>;
400 gpio-key,wakeup;
401 };
402
403 down {
404 label = "SW-TACT5";
405 gpios = <&gpx1 7 1>;
406 linux,code = <108>;
407 gpio-key,wakeup;
408 };
409
410 back {
411 label = "SW-TACT6";
412 gpios = <&gpx2 0 1>;
413 linux,code = <158>;
414 gpio-key,wakeup;
415 };
416
417 wakeup {
418 label = "SW-TACT7";
419 gpios = <&gpx2 1 1>;
420 linux,code = <143>;
421 gpio-key,wakeup;
422 };
423 };
424
425 hdmi {
426 hpd-gpio = <&gpx3 7 2>;
427 vdd_osc-supply = <&ldo10_reg>;
428 vdd_pll-supply = <&ldo8_reg>;
429 vdd-supply = <&ldo8_reg>;
430 };
431
432 mmc_reg: voltage-regulator {
433 compatible = "regulator-fixed";
434 regulator-name = "VDD_33ON_2.8V";
435 regulator-min-microvolt = <2800000>;
436 regulator-max-microvolt = <2800000>;
437 gpio = <&gpx1 1 1>;
438 enable-active-high;
439 };
440
441 reg_hdmi_en: fixedregulator@0 {
442 compatible = "regulator-fixed";
443 regulator-name = "hdmi-en";
444 };
445
123 fixed-rate-clocks { 446 fixed-rate-clocks {
124 xxti { 447 xxti {
125 compatible = "samsung,clock-xxti"; 448 compatible = "samsung,clock-xxti";
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
new file mode 100644
index 000000000000..d1650fb34c0a
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -0,0 +1,783 @@
1/*
2 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
8 * tree nodes are listed in this file.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/ {
16 pinctrl@11400000 {
17 gpa0: gpa0 {
18 gpio-controller;
19 #gpio-cells = <2>;
20
21 interrupt-controller;
22 #interrupt-cells = <2>;
23 };
24
25 gpa1: gpa1 {
26 gpio-controller;
27 #gpio-cells = <2>;
28
29 interrupt-controller;
30 #interrupt-cells = <2>;
31 };
32
33 gpa2: gpa2 {
34 gpio-controller;
35 #gpio-cells = <2>;
36
37 interrupt-controller;
38 #interrupt-cells = <2>;
39 };
40
41 gpb0: gpb0 {
42 gpio-controller;
43 #gpio-cells = <2>;
44
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 };
48
49 gpb1: gpb1 {
50 gpio-controller;
51 #gpio-cells = <2>;
52
53 interrupt-controller;
54 #interrupt-cells = <2>;
55 };
56
57 gpb2: gpb2 {
58 gpio-controller;
59 #gpio-cells = <2>;
60
61 interrupt-controller;
62 #interrupt-cells = <2>;
63 };
64
65 gpb3: gpb3 {
66 gpio-controller;
67 #gpio-cells = <2>;
68
69 interrupt-controller;
70 #interrupt-cells = <2>;
71 };
72
73 gpc0: gpc0 {
74 gpio-controller;
75 #gpio-cells = <2>;
76
77 interrupt-controller;
78 #interrupt-cells = <2>;
79 };
80
81 gpc1: gpc1 {
82 gpio-controller;
83 #gpio-cells = <2>;
84
85 interrupt-controller;
86 #interrupt-cells = <2>;
87 };
88
89 gpc2: gpc2 {
90 gpio-controller;
91 #gpio-cells = <2>;
92
93 interrupt-controller;
94 #interrupt-cells = <2>;
95 };
96
97 gpc3: gpc3 {
98 gpio-controller;
99 #gpio-cells = <2>;
100
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 };
104
105 gpd0: gpd0 {
106 gpio-controller;
107 #gpio-cells = <2>;
108
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 };
112
113 gpd1: gpd1 {
114 gpio-controller;
115 #gpio-cells = <2>;
116
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 };
120
121 gpy0: gpy0 {
122 gpio-controller;
123 #gpio-cells = <2>;
124 };
125
126 gpy1: gpy1 {
127 gpio-controller;
128 #gpio-cells = <2>;
129 };
130
131 gpy2: gpy2 {
132 gpio-controller;
133 #gpio-cells = <2>;
134 };
135
136 gpy3: gpy3 {
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 gpy4: gpy4 {
142 gpio-controller;
143 #gpio-cells = <2>;
144 };
145
146 gpy5: gpy5 {
147 gpio-controller;
148 #gpio-cells = <2>;
149 };
150
151 gpy6: gpy6 {
152 gpio-controller;
153 #gpio-cells = <2>;
154 };
155
156 gpc4: gpc4 {
157 gpio-controller;
158 #gpio-cells = <2>;
159
160 interrupt-controller;
161 #interrupt-cells = <2>;
162 };
163
164 gpx0: gpx0 {
165 gpio-controller;
166 #gpio-cells = <2>;
167
168 interrupt-controller;
169 interrupt-parent = <&combiner>;
170 #interrupt-cells = <2>;
171 interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
172 <26 0>, <26 1>, <27 0>, <27 1>;
173 };
174
175 gpx1: gpx1 {
176 gpio-controller;
177 #gpio-cells = <2>;
178
179 interrupt-controller;
180 interrupt-parent = <&combiner>;
181 #interrupt-cells = <2>;
182 interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
183 <30 0>, <30 1>, <31 0>, <31 1>;
184 };
185
186 gpx2: gpx2 {
187 gpio-controller;
188 #gpio-cells = <2>;
189
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 };
193
194 gpx3: gpx3 {
195 gpio-controller;
196 #gpio-cells = <2>;
197
198 interrupt-controller;
199 #interrupt-cells = <2>;
200 };
201
202 uart0_data: uart0-data {
203 samsung,pins = "gpa0-0", "gpa0-1";
204 samsung,pin-function = <2>;
205 samsung,pin-pud = <0>;
206 samsung,pin-drv = <0>;
207 };
208
209 uart0_fctl: uart0-fctl {
210 samsung,pins = "gpa0-2", "gpa0-3";
211 samsung,pin-function = <2>;
212 samsung,pin-pud = <0>;
213 samaung,pin-drv = <0>;
214 };
215
216 i2c2_bus: i2c2-bus {
217 samsung,pins = "gpa0-6", "gpa0-7";
218 samsung,pin-function = <3>;
219 samsung,pin-pud = <3>;
220 samaung,pin-drv = <0>;
221 };
222
223 i2c2_hs_bus: i2c2-hs-bus {
224 samsung,pins = "gpa0-6", "gpa0-7";
225 samsung,pin-function = <4>;
226 samsung,pin-pud = <3>;
227 samaung,pin-drv = <0>;
228 };
229
230 uart2_data: uart2-data {
231 samsung,pins = "gpa1-0", "gpa1-1";
232 samsung,pin-function = <2>;
233 samsung,pin-pud = <0>;
234 samsung,pin-drv = <0>;
235 };
236
237 uart2_fctl: uart2-fctl {
238 samsung,pins = "gpa1-2", "gpa1-3";
239 samsung,pin-function = <2>;
240 samsung,pin-pud = <0>;
241 samaung,pin-drv = <0>;
242 };
243
244 i2c3_bus: i2c3-bus {
245 samsung,pins = "gpa1-2", "gpa1-3";
246 samsung,pin-function = <3>;
247 samsung,pin-pud = <3>;
248 samaung,pin-drv = <0>;
249 };
250
251 i2c3_hs_bus: i2c3-hs-bus {
252 samsung,pins = "gpa1-2", "gpa1-3";
253 samsung,pin-function = <4>;
254 samsung,pin-pud = <3>;
255 samaung,pin-drv = <0>;
256 };
257
258 uart3_data: uart3-data {
259 samsung,pins = "gpa1-4", "gpa1-4";
260 samsung,pin-function = <2>;
261 samsung,pin-pud = <0>;
262 samsung,pin-drv = <0>;
263 };
264
265 spi0_bus: spi0-bus {
266 samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3";
267 samsung,pin-function = <2>;
268 samsung,pin-pud = <3>;
269 samsung,pin-drv = <0>;
270 };
271
272 i2c4_bus: i2c4-bus {
273 samsung,pins = "gpa2-0", "gpa2-1";
274 samsung,pin-function = <3>;
275 samsung,pin-pud = <3>;
276 samaung,pin-drv = <0>;
277 };
278
279 i2c5_bus: i2c5-bus {
280 samsung,pins = "gpa2-2", "gpa2-3";
281 samsung,pin-function = <3>;
282 samsung,pin-pud = <3>;
283 samaung,pin-drv = <0>;
284 };
285
286 spi1_bus: spi1-bus {
287 samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
288 samsung,pin-function = <2>;
289 samsung,pin-pud = <3>;
290 samsung,pin-drv = <0>;
291 };
292
293 i2s1_bus: i2s1-bus {
294 samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
295 "gpb0-4";
296 samsung,pin-function = <2>;
297 samsung,pin-pud = <0>;
298 samsung,pin-drv = <0>;
299 };
300
301 pcm1_bus: pcm1-bus {
302 samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
303 "gpb0-4";
304 samsung,pin-function = <3>;
305 samsung,pin-pud = <0>;
306 samsung,pin-drv = <0>;
307 };
308
309 ac97_bus: ac97-bus {
310 samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
311 "gpb0-4";
312 samsung,pin-function = <4>;
313 samsung,pin-pud = <0>;
314 samsung,pin-drv = <0>;
315 };
316
317 i2s2_bus: i2s2-bus {
318 samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
319 "gpb1-4";
320 samsung,pin-function = <2>;
321 samsung,pin-pud = <0>;
322 samsung,pin-drv = <0>;
323 };
324
325 pcm2_bus: pcm2-bus {
326 samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
327 "gpb1-4";
328 samsung,pin-function = <3>;
329 samsung,pin-pud = <0>;
330 samsung,pin-drv = <0>;
331 };
332
333 spdif_bus: spdif-bus {
334 samsung,pins = "gpb1-0", "gpb1-1";
335 samsung,pin-function = <4>;
336 samsung,pin-pud = <0>;
337 samsung,pin-drv = <0>;
338 };
339
340 spi2_bus: spi2-bus {
341 samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4";
342 samsung,pin-function = <5>;
343 samsung,pin-pud = <3>;
344 samsung,pin-drv = <0>;
345 };
346
347 i2c6_bus: i2c6-bus {
348 samsung,pins = "gpb1-3", "gpb1-4";
349 samsung,pin-function = <4>;
350 samsung,pin-pud = <3>;
351 samsung,pin-drv = <0>;
352 };
353
354 i2c7_bus: i2c7-bus {
355 samsung,pins = "gpb2-2", "gpb2-3";
356 samsung,pin-function = <3>;
357 samsung,pin-pud = <3>;
358 samsung,pin-drv = <0>;
359 };
360
361 i2c0_bus: i2c0-bus {
362 samsung,pins = "gpb3-0", "gpb3-1";
363 samsung,pin-function = <2>;
364 samsung,pin-pud = <3>;
365 samsung,pin-drv = <0>;
366 };
367
368 i2c1_bus: i2c1-bus {
369 samsung,pins = "gpb3-2", "gpb3-3";
370 samsung,pin-function = <2>;
371 samsung,pin-pud = <3>;
372 samsung,pin-drv = <0>;
373 };
374
375 i2c0_hs_bus: i2c0-hs-bus {
376 samsung,pins = "gpb3-0", "gpb3-1";
377 samsung,pin-function = <4>;
378 samsung,pin-pud = <3>;
379 samaung,pin-drv = <0>;
380 };
381
382 i2c1_hs_bus: i2c1-hs-bus {
383 samsung,pins = "gpb3-2", "gpb3-3";
384 samsung,pin-function = <4>;
385 samsung,pin-pud = <3>;
386 samaung,pin-drv = <0>;
387 };
388
389 sd0_clk: sd0-clk {
390 samsung,pins = "gpc0-0";
391 samsung,pin-function = <2>;
392 samsung,pin-pud = <0>;
393 samsung,pin-drv = <3>;
394 };
395
396 sd0_cmd: sd0-cmd {
397 samsung,pins = "gpc0-1";
398 samsung,pin-function = <2>;
399 samsung,pin-pud = <0>;
400 samsung,pin-drv = <3>;
401 };
402
403 sd0_cd: sd0-cd {
404 samsung,pins = "gpc0-2";
405 samsung,pin-function = <2>;
406 samsung,pin-pud = <3>;
407 samsung,pin-drv = <3>;
408 };
409
410 sd0_bus1: sd0-bus-width1 {
411 samsung,pins = "gpc0-3";
412 samsung,pin-function = <2>;
413 samsung,pin-pud = <3>;
414 samsung,pin-drv = <3>;
415 };
416
417 sd0_bus4: sd0-bus-width4 {
418 samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6";
419 samsung,pin-function = <2>;
420 samsung,pin-pud = <3>;
421 samsung,pin-drv = <3>;
422 };
423
424 sd0_bus8: sd0-bus-width8 {
425 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3";
426 samsung,pin-function = <2>;
427 samsung,pin-pud = <3>;
428 samsung,pin-drv = <3>;
429 };
430
431 sd1_clk: sd1-clk {
432 samsung,pins = "gpc2-0";
433 samsung,pin-function = <2>;
434 samsung,pin-pud = <0>;
435 samsung,pin-drv = <3>;
436 };
437
438 sd1_cmd: sd1-cmd {
439 samsung,pins = "gpc2-1";
440 samsung,pin-function = <2>;
441 samsung,pin-pud = <0>;
442 samsung,pin-drv = <3>;
443 };
444
445 sd1_cd: sd1-cd {
446 samsung,pins = "gpc2-2";
447 samsung,pin-function = <2>;
448 samsung,pin-pud = <3>;
449 samsung,pin-drv = <3>;
450 };
451
452 sd1_bus1: sd1-bus-width1 {
453 samsung,pins = "gpc2-3";
454 samsung,pin-function = <2>;
455 samsung,pin-pud = <3>;
456 samsung,pin-drv = <3>;
457 };
458
459 sd1_bus4: sd1-bus-width4 {
460 samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6";
461 samsung,pin-function = <2>;
462 samsung,pin-pud = <3>;
463 samsung,pin-drv = <3>;
464 };
465
466 sd2_clk: sd2-clk {
467 samsung,pins = "gpc3-0";
468 samsung,pin-function = <2>;
469 samsung,pin-pud = <0>;
470 samsung,pin-drv = <3>;
471 };
472
473 sd2_cmd: sd2-cmd {
474 samsung,pins = "gpc3-1";
475 samsung,pin-function = <2>;
476 samsung,pin-pud = <0>;
477 samsung,pin-drv = <3>;
478 };
479
480 sd2_cd: sd2-cd {
481 samsung,pins = "gpc3-2";
482 samsung,pin-function = <2>;
483 samsung,pin-pud = <3>;
484 samsung,pin-drv = <3>;
485 };
486
487 sd2_bus1: sd2-bus-width1 {
488 samsung,pins = "gpc3-3";
489 samsung,pin-function = <2>;
490 samsung,pin-pud = <3>;
491 samsung,pin-drv = <3>;
492 };
493
494 sd2_bus4: sd2-bus-width4 {
495 samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6";
496 samsung,pin-function = <2>;
497 samsung,pin-pud = <3>;
498 samsung,pin-drv = <3>;
499 };
500
501 sd2_bus8: sd2-bus-width8 {
502 samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6";
503 samsung,pin-function = <3>;
504 samsung,pin-pud = <3>;
505 samsung,pin-drv = <3>;
506 };
507
508 sd3_clk: sd3-clk {
509 samsung,pins = "gpc4-0";
510 samsung,pin-function = <2>;
511 samsung,pin-pud = <0>;
512 samsung,pin-drv = <3>;
513 };
514
515 sd3_cmd: sd3-cmd {
516 samsung,pins = "gpc4-1";
517 samsung,pin-function = <2>;
518 samsung,pin-pud = <0>;
519 samsung,pin-drv = <3>;
520 };
521
522 sd3_cd: sd3-cd {
523 samsung,pins = "gpc4-2";
524 samsung,pin-function = <2>;
525 samsung,pin-pud = <3>;
526 samsung,pin-drv = <3>;
527 };
528
529 sd3_bus1: sd3-bus-width1 {
530 samsung,pins = "gpc4-3";
531 samsung,pin-function = <2>;
532 samsung,pin-pud = <3>;
533 samsung,pin-drv = <3>;
534 };
535
536 sd3_bus4: sd3-bus-width4 {
537 samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6";
538 samsung,pin-function = <2>;
539 samsung,pin-pud = <3>;
540 samsung,pin-drv = <3>;
541 };
542
543 uart1_data: uart1-data {
544 samsung,pins = "gpd0-0", "gpd0-1";
545 samsung,pin-function = <2>;
546 samsung,pin-pud = <0>;
547 samsung,pin-drv = <0>;
548 };
549
550 uart1_fctl: uart1-fctl {
551 samsung,pins = "gpd0-2", "gpd0-3";
552 samsung,pin-function = <2>;
553 samsung,pin-pud = <0>;
554 samaung,pin-drv = <0>;
555 };
556 };
557
558 pinctrl@13400000 {
559 gpe0: gpe0 {
560 gpio-controller;
561 #gpio-cells = <2>;
562
563 interrupt-controller;
564 #interrupt-cells = <2>;
565 };
566
567 gpe1: gpe1 {
568 gpio-controller;
569 #gpio-cells = <2>;
570
571 interrupt-controller;
572 #interrupt-cells = <2>;
573 };
574
575 gpf0: gpf0 {
576 gpio-controller;
577 #gpio-cells = <2>;
578
579 interrupt-controller;
580 #interrupt-cells = <2>;
581 };
582
583 gpf1: gpf1 {
584 gpio-controller;
585 #gpio-cells = <2>;
586
587 interrupt-controller;
588 #interrupt-cells = <2>;
589 };
590
591 gpg0: gpg0 {
592 gpio-controller;
593 #gpio-cells = <2>;
594
595 interrupt-controller;
596 #interrupt-cells = <2>;
597 };
598
599 gpg1: gpg1 {
600 gpio-controller;
601 #gpio-cells = <2>;
602
603 interrupt-controller;
604 #interrupt-cells = <2>;
605 };
606
607 gpg2: gpg2 {
608 gpio-controller;
609 #gpio-cells = <2>;
610
611 interrupt-controller;
612 #interrupt-cells = <2>;
613 };
614
615 gph0: gph0 {
616 gpio-controller;
617 #gpio-cells = <2>;
618
619 interrupt-controller;
620 #interrupt-cells = <2>;
621 };
622
623 gph1: gph1 {
624 gpio-controller;
625 #gpio-cells = <2>;
626
627 interrupt-controller;
628 #interrupt-cells = <2>;
629 };
630
631 cam_gpio_a: cam-gpio-a {
632 samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
633 "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
634 "gpe1-0", "gpe1-1";
635 samsung,pin-function = <2>;
636 samsung,pin-pud = <0>;
637 samsung,pin-drv = <0>;
638 };
639
640 cam_gpio_b: cam-gpio-b {
641 samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
642 "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
643 samsung,pin-function = <3>;
644 samsung,pin-pud = <0>;
645 samaung,pin-drv = <0>;
646 };
647
648 cam_i2c2_bus: cam-i2c2-bus {
649 samsung,pins = "gpe0-6", "gpe1-0";
650 samsung,pin-function = <4>;
651 samsung,pin-pud = <3>;
652 samaung,pin-drv = <0>;
653 };
654
655 cam_spi1_bus: cam-spi1-bus {
656 samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
657 samsung,pin-function = <4>;
658 samsung,pin-pud = <0>;
659 samaung,pin-drv = <0>;
660 };
661
662 cam_i2c1_bus: cam-i2c1-bus {
663 samsung,pins = "gpf0-2", "gpf0-3";
664 samsung,pin-function = <2>;
665 samsung,pin-pud = <3>;
666 samaung,pin-drv = <0>;
667 };
668
669 cam_i2c0_bus: cam-i2c0-bus {
670 samsung,pins = "gpf0-0", "gpf0-1";
671 samsung,pin-function = <2>;
672 samsung,pin-pud = <3>;
673 samaung,pin-drv = <0>;
674 };
675
676 cam_spi0_bus: cam-spi0-bus {
677 samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
678 samsung,pin-function = <2>;
679 samsung,pin-pud = <0>;
680 samaung,pin-drv = <0>;
681 };
682
683 cam_bayrgb_bus: cam-bayrgb-bus {
684 samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3",
685 "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7",
686 "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3",
687 "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7",
688 "gpg2-0", "gpg2-1";
689 samsung,pin-function = <2>;
690 samsung,pin-pud = <0>;
691 samaung,pin-drv = <0>;
692 };
693
694 cam_port_a: cam-port-a {
695 samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3",
696 "gph1-0", "gph1-1", "gph1-2", "gph1-3",
697 "gph1-4", "gph1-5", "gph1-6", "gph1-7";
698 samsung,pin-function = <2>;
699 samsung,pin-pud = <0>;
700 samaung,pin-drv = <0>;
701 };
702 };
703
704 pinctrl@10d10000 {
705 gpv0: gpv0 {
706 gpio-controller;
707 #gpio-cells = <2>;
708
709 interrupt-controller;
710 #interrupt-cells = <2>;
711 };
712
713 gpv1: gpv1 {
714 gpio-controller;
715 #gpio-cells = <2>;
716
717 interrupt-controller;
718 #interrupt-cells = <2>;
719 };
720
721 gpv2: gpv2 {
722 gpio-controller;
723 #gpio-cells = <2>;
724
725 interrupt-controller;
726 #interrupt-cells = <2>;
727 };
728
729 gpv3: gpv3 {
730 gpio-controller;
731 #gpio-cells = <2>;
732
733 interrupt-controller;
734 #interrupt-cells = <2>;
735 };
736
737 gpv4: gpv4 {
738 gpio-controller;
739 #gpio-cells = <2>;
740
741 interrupt-controller;
742 #interrupt-cells = <2>;
743 };
744
745 c2c_rxd: c2c-rxd {
746 samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
747 "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
748 "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
749 "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7";
750 samsung,pin-function = <2>;
751 samsung,pin-pud = <0>;
752 samaung,pin-drv = <0>;
753 };
754
755 c2c_txd: c2c-txd {
756 samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
757 "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
758 "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
759 "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7";
760 samsung,pin-function = <2>;
761 samsung,pin-pud = <0>;
762 samaung,pin-drv = <0>;
763 };
764 };
765
766 pinctrl@03680000 {
767 gpz: gpz {
768 gpio-controller;
769 #gpio-cells = <2>;
770
771 interrupt-controller;
772 #interrupt-cells = <2>;
773 };
774
775 i2s0_bus: i2s0-bus {
776 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
777 "gpz-4", "gpz-5", "gpz-6";
778 samsung,pin-function = <2>;
779 samsung,pin-pud = <0>;
780 samsung,pin-drv = <0>;
781 };
782 };
783};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 872ae1f93c75..26d856ba50a1 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -30,8 +30,6 @@
30 i2c@12C60000 { 30 i2c@12C60000 {
31 samsung,i2c-sda-delay = <100>; 31 samsung,i2c-sda-delay = <100>;
32 samsung,i2c-max-bus-freq = <20000>; 32 samsung,i2c-max-bus-freq = <20000>;
33 gpios = <&gpb3 0 2 3 0>,
34 <&gpb3 1 2 3 0>;
35 33
36 eeprom@50 { 34 eeprom@50 {
37 compatible = "samsung,s524ad0xd1"; 35 compatible = "samsung,s524ad0xd1";
@@ -42,8 +40,6 @@
42 i2c@12C70000 { 40 i2c@12C70000 {
43 samsung,i2c-sda-delay = <100>; 41 samsung,i2c-sda-delay = <100>;
44 samsung,i2c-max-bus-freq = <20000>; 42 samsung,i2c-max-bus-freq = <20000>;
45 gpios = <&gpb3 2 2 3 0>,
46 <&gpb3 3 2 3 0>;
47 43
48 eeprom@51 { 44 eeprom@51 {
49 compatible = "samsung,s524ad0xd1"; 45 compatible = "samsung,s524ad0xd1";
@@ -74,8 +70,6 @@
74 i2c@12C80000 { 70 i2c@12C80000 {
75 samsung,i2c-sda-delay = <100>; 71 samsung,i2c-sda-delay = <100>;
76 samsung,i2c-max-bus-freq = <66000>; 72 samsung,i2c-max-bus-freq = <66000>;
77 gpios = <&gpa0 6 3 3 0>,
78 <&gpa0 7 3 3 0>;
79 73
80 hdmiddc@50 { 74 hdmiddc@50 {
81 compatible = "samsung,exynos5-hdmiddc"; 75 compatible = "samsung,exynos5-hdmiddc";
@@ -122,15 +116,12 @@
122 samsung,dw-mshc-ciu-div = <3>; 116 samsung,dw-mshc-ciu-div = <3>;
123 samsung,dw-mshc-sdr-timing = <2 3>; 117 samsung,dw-mshc-sdr-timing = <2 3>;
124 samsung,dw-mshc-ddr-timing = <1 2>; 118 samsung,dw-mshc-ddr-timing = <1 2>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
125 121
126 slot@0 { 122 slot@0 {
127 reg = <0>; 123 reg = <0>;
128 bus-width = <8>; 124 bus-width = <8>;
129 gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
130 <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
131 <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
132 <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
133 <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
134 }; 125 };
135 }; 126 };
136 127
@@ -146,17 +137,13 @@
146 samsung,dw-mshc-ciu-div = <3>; 137 samsung,dw-mshc-ciu-div = <3>;
147 samsung,dw-mshc-sdr-timing = <2 3>; 138 samsung,dw-mshc-sdr-timing = <2 3>;
148 samsung,dw-mshc-ddr-timing = <1 2>; 139 samsung,dw-mshc-ddr-timing = <1 2>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
149 142
150 slot@0 { 143 slot@0 {
151 reg = <0>; 144 reg = <0>;
152 bus-width = <4>; 145 bus-width = <4>;
153 samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
154 disable-wp; 146 disable-wp;
155 gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
156 <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
157 <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
158 <&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
159 <&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
160 }; 147 };
161 }; 148 };
162 149
@@ -169,10 +156,6 @@
169 }; 156 };
170 157
171 spi_1: spi@12d30000 { 158 spi_1: spi@12d30000 {
172 gpios = <&gpa2 4 2 3 0>,
173 <&gpa2 6 2 3 0>,
174 <&gpa2 7 2 3 0>;
175
176 w25q80bw@0 { 159 w25q80bw@0 {
177 #address-cells = <1>; 160 #address-cells = <1>;
178 #size-cells = <1>; 161 #size-cells = <1>;
@@ -181,7 +164,7 @@
181 spi-max-frequency = <1000000>; 164 spi-max-frequency = <1000000>;
182 165
183 controller-data { 166 controller-data {
184 cs-gpio = <&gpa2 5 1 0 3>; 167 cs-gpio = <&gpa2 5 0>;
185 samsung,spi-feedback-delay = <0>; 168 samsung,spi-feedback-delay = <0>;
186 }; 169 };
187 170
@@ -203,7 +186,7 @@
203 }; 186 };
204 187
205 hdmi { 188 hdmi {
206 hpd-gpio = <&gpx3 7 0xf 1 3>; 189 hpd-gpio = <&gpx3 7 0>;
207 }; 190 };
208 191
209 codec@11000000 { 192 codec@11000000 {
@@ -212,9 +195,7 @@
212 }; 195 };
213 196
214 i2s0: i2s@03830000 { 197 i2s0: i2s@03830000 {
215 gpios = <&gpz 0 2 0 0>, <&gpz 1 2 0 0>, <&gpz 2 2 0 0>, 198 status = "okay";
216 <&gpz 3 2 0 0>, <&gpz 4 2 0 0>, <&gpz 5 2 0 0>,
217 <&gpz 6 2 0 0>;
218 }; 199 };
219 200
220 i2s1: i2s@12D60000 { 201 i2s1: i2s@12D60000 {
@@ -245,6 +226,22 @@
245 samsung,lane-count = <4>; 226 samsung,lane-count = <4>;
246 }; 227 };
247 228
229 display-timings {
230 native-mode = <&timing0>;
231 timing0: timing@0 {
232 /* 1280x800 */
233 clock-frequency = <50000>;
234 hactive = <1280>;
235 vactive = <800>;
236 hfront-porch = <4>;
237 hback-porch = <4>;
238 hsync-len = <4>;
239 vback-porch = <4>;
240 vfront-porch = <4>;
241 vsync-len = <4>;
242 };
243 };
244
248 fixed-rate-clocks { 245 fixed-rate-clocks {
249 xxti { 246 xxti {
250 compatible = "samsung,clock-xxti"; 247 compatible = "samsung,clock-xxti";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index babd9f9b1bf9..bf4744bab445 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -16,12 +16,31 @@
16 model = "Google Snow"; 16 model = "Google Snow";
17 compatible = "google,snow", "samsung,exynos5250"; 17 compatible = "google,snow", "samsung,exynos5250";
18 18
19 aliases {
20 i2c104 = &i2c_104;
21 };
22
23 pinctrl@11400000 {
24 sd3_clk: sd3-clk {
25 samsung,pin-drv = <0>;
26 };
27
28 sd3_cmd: sd3-cmd {
29 samsung,pin-pud = <3>;
30 samsung,pin-drv = <0>;
31 };
32
33 sd3_bus4: sd3-bus-width4 {
34 samsung,pin-drv = <0>;
35 };
36 };
37
19 gpio-keys { 38 gpio-keys {
20 compatible = "gpio-keys"; 39 compatible = "gpio-keys";
21 40
22 lid-switch { 41 lid-switch {
23 label = "Lid"; 42 label = "Lid";
24 gpios = <&gpx3 5 0 0x10000 0>; 43 gpios = <&gpx3 5 1>;
25 linux,input-type = <5>; /* EV_SW */ 44 linux,input-type = <5>; /* EV_SW */
26 linux,code = <0>; /* SW_LID */ 45 linux,code = <0>; /* SW_LID */
27 debounce-interval = <1>; 46 debounce-interval = <1>;
@@ -29,15 +48,137 @@
29 }; 48 };
30 }; 49 };
31 50
51 i2c-arbitrator {
52 compatible = "i2c-arb-gpio-challenge";
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 i2c-parent = <&{/i2c@12CA0000}>;
57
58 our-claim-gpio = <&gpf0 3 1>;
59 their-claim-gpios = <&gpe0 4 1>;
60 slew-delay-us = <10>;
61 wait-retry-us = <3000>;
62 wait-free-us = <50000>;
63
64 /* Use ID 104 as a hint that we're on physical bus 4 */
65 i2c_104: i2c@0 {
66 reg = <0>;
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 battery: sbs-battery@b {
71 compatible = "sbs,sbs-battery";
72 reg = <0xb>;
73 sbs,poll-retry-count = <1>;
74 };
75
76 ec: embedded-controller {
77 compatible = "google,cros-ec-i2c";
78 reg = <0x1e>;
79 interrupts = <6 0>;
80 interrupt-parent = <&gpx1>;
81 wakeup-source;
82
83 keyboard-controller {
84 compatible = "google,cros-ec-keyb";
85 keypad,num-rows = <8>;
86 keypad,num-columns = <13>;
87 google,needs-ghost-filter;
88 linux,keymap = <0x0001003a /* CAPSLK */
89 0x0002003b /* F1 */
90 0x00030030 /* B */
91 0x00040044 /* F10 */
92 0x00060031 /* N */
93 0x0008000d /* = */
94 0x000a0064 /* R_ALT */
95
96 0x01010001 /* ESC */
97 0x0102003e /* F4 */
98 0x01030022 /* G */
99 0x01040041 /* F7 */
100 0x01060023 /* H */
101 0x01080028 /* ' */
102 0x01090043 /* F9 */
103 0x010b000e /* BKSPACE */
104
105 0x0200001d /* L_CTRL */
106 0x0201000f /* TAB */
107 0x0202003d /* F3 */
108 0x02030014 /* T */
109 0x02040040 /* F6 */
110 0x0205001b /* ] */
111 0x02060015 /* Y */
112 0x02070056 /* 102ND */
113 0x0208001a /* [ */
114 0x02090042 /* F8 */
115
116 0x03010029 /* GRAVE */
117 0x0302003c /* F2 */
118 0x03030006 /* 5 */
119 0x0304003f /* F5 */
120 0x03060007 /* 6 */
121 0x0308000c /* - */
122 0x030b002b /* \ */
123
124 0x04000061 /* R_CTRL */
125 0x0401001e /* A */
126 0x04020020 /* D */
127 0x04030021 /* F */
128 0x0404001f /* S */
129 0x04050025 /* K */
130 0x04060024 /* J */
131 0x04080027 /* ; */
132 0x04090026 /* L */
133 0x040b001c /* ENTER */
134
135 0x0501002c /* Z */
136 0x0502002e /* C */
137 0x0503002f /* V */
138 0x0504002d /* X */
139 0x05050033 /* , */
140 0x05060032 /* M */
141 0x0507002a /* L_SHIFT */
142 0x05080035 /* / */
143 0x05090034 /* . */
144 0x050B0039 /* SPACE */
145
146 0x06010002 /* 1 */
147 0x06020004 /* 3 */
148 0x06030005 /* 4 */
149 0x06040003 /* 2 */
150 0x06050009 /* 8 */
151 0x06060008 /* 7 */
152 0x0608000b /* 0 */
153 0x0609000a /* 9 */
154 0x060a0038 /* L_ALT */
155 0x060b006c /* DOWN */
156 0x060c006a /* RIGHT */
157
158 0x07010010 /* Q */
159 0x07020012 /* E */
160 0x07030013 /* R */
161 0x07040011 /* W */
162 0x07050017 /* I */
163 0x07060016 /* U */
164 0x07070036 /* R_SHIFT */
165 0x07080019 /* P */
166 0x07090018 /* O */
167 0x070b0067 /* UP */
168 0x070c0069>; /* LEFT */
169 };
170 };
171 };
172 };
173
32 /* 174 /*
33 * On Snow we've got SIP WiFi and so can keep drive strengths low to 175 * On Snow we've got SIP WiFi and so can keep drive strengths low to
34 * reduce EMI. 176 * reduce EMI.
35 */ 177 */
36 dwmmc3@12230000 { 178 dwmmc3@12230000 {
37 slot@0 { 179 slot@0 {
38 gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>, 180 pinctrl-names = "default";
39 <&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>, 181 pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
40 <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
41 }; 182 };
42 }; 183 };
43 184
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 28758e5dd15c..98dfc3ea5c0b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -18,6 +18,7 @@
18*/ 18*/
19 19
20/include/ "skeleton.dtsi" 20/include/ "skeleton.dtsi"
21/include/ "exynos5250-pinctrl.dtsi"
21 22
22/ { 23/ {
23 compatible = "samsung,exynos5250"; 24 compatible = "samsung,exynos5250";
@@ -44,6 +45,15 @@
44 i2c6 = &i2c_6; 45 i2c6 = &i2c_6;
45 i2c7 = &i2c_7; 46 i2c7 = &i2c_7;
46 i2c8 = &i2c_8; 47 i2c8 = &i2c_8;
48 pinctrl0 = &pinctrl_0;
49 pinctrl1 = &pinctrl_1;
50 pinctrl2 = &pinctrl_2;
51 pinctrl3 = &pinctrl_3;
52 };
53
54 chipid@10000000 {
55 compatible = "samsung,exynos4210-chipid";
56 reg = <0x10000000 0x100>;
47 }; 57 };
48 58
49 pd_gsc: gsc-power-domain@0x10044000 { 59 pd_gsc: gsc-power-domain@0x10044000 {
@@ -63,10 +73,22 @@
63 }; 73 };
64 74
65 gic:interrupt-controller@10481000 { 75 gic:interrupt-controller@10481000 {
66 compatible = "arm,cortex-a9-gic"; 76 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
67 #interrupt-cells = <3>; 77 #interrupt-cells = <3>;
68 interrupt-controller; 78 interrupt-controller;
69 reg = <0x10481000 0x1000>, <0x10482000 0x2000>; 79 reg = <0x10481000 0x1000>,
80 <0x10482000 0x1000>,
81 <0x10484000 0x2000>,
82 <0x10486000 0x2000>;
83 interrupts = <1 9 0xf04>;
84 };
85
86 timer {
87 compatible = "arm,armv7-timer";
88 interrupts = <1 13 0xf08>,
89 <1 14 0xf08>,
90 <1 11 0xf08>,
91 <1 10 0xf08>;
70 }; 92 };
71 93
72 combiner:interrupt-controller@10440000 { 94 combiner:interrupt-controller@10440000 {
@@ -115,6 +137,36 @@
115 interrupts = <1 2>, <22 4>; 137 interrupts = <1 2>, <22 4>;
116 }; 138 };
117 139
140 pinctrl_0: pinctrl@11400000 {
141 compatible = "samsung,exynos5250-pinctrl";
142 reg = <0x11400000 0x1000>;
143 interrupts = <0 46 0>;
144
145 wakup_eint: wakeup-interrupt-controller {
146 compatible = "samsung,exynos4210-wakeup-eint";
147 interrupt-parent = <&gic>;
148 interrupts = <0 32 0>;
149 };
150 };
151
152 pinctrl_1: pinctrl@13400000 {
153 compatible = "samsung,exynos5250-pinctrl";
154 reg = <0x13400000 0x1000>;
155 interrupts = <0 45 0>;
156 };
157
158 pinctrl_2: pinctrl@10d10000 {
159 compatible = "samsung,exynos5250-pinctrl";
160 reg = <0x10d10000 0x1000>;
161 interrupts = <0 50 0>;
162 };
163
164 pinctrl_3: pinctrl@03680000 {
165 compatible = "samsung,exynos5250-pinctrl";
166 reg = <0x0368000 0x1000>;
167 interrupts = <0 47 0>;
168 };
169
118 watchdog { 170 watchdog {
119 compatible = "samsung,s3c2410-wdt"; 171 compatible = "samsung,s3c2410-wdt";
120 reg = <0x101D0000 0x100>; 172 reg = <0x101D0000 0x100>;
@@ -200,6 +252,8 @@
200 #size-cells = <0>; 252 #size-cells = <0>;
201 clocks = <&clock 294>; 253 clocks = <&clock 294>;
202 clock-names = "i2c"; 254 clock-names = "i2c";
255 pinctrl-names = "default";
256 pinctrl-0 = <&i2c0_bus>;
203 }; 257 };
204 258
205 i2c_1: i2c@12C70000 { 259 i2c_1: i2c@12C70000 {
@@ -210,6 +264,8 @@
210 #size-cells = <0>; 264 #size-cells = <0>;
211 clocks = <&clock 295>; 265 clocks = <&clock 295>;
212 clock-names = "i2c"; 266 clock-names = "i2c";
267 pinctrl-names = "default";
268 pinctrl-0 = <&i2c1_bus>;
213 }; 269 };
214 270
215 i2c_2: i2c@12C80000 { 271 i2c_2: i2c@12C80000 {
@@ -220,6 +276,8 @@
220 #size-cells = <0>; 276 #size-cells = <0>;
221 clocks = <&clock 296>; 277 clocks = <&clock 296>;
222 clock-names = "i2c"; 278 clock-names = "i2c";
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c2_bus>;
223 }; 281 };
224 282
225 i2c_3: i2c@12C90000 { 283 i2c_3: i2c@12C90000 {
@@ -230,6 +288,8 @@
230 #size-cells = <0>; 288 #size-cells = <0>;
231 clocks = <&clock 297>; 289 clocks = <&clock 297>;
232 clock-names = "i2c"; 290 clock-names = "i2c";
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c3_bus>;
233 }; 293 };
234 294
235 i2c_4: i2c@12CA0000 { 295 i2c_4: i2c@12CA0000 {
@@ -240,6 +300,8 @@
240 #size-cells = <0>; 300 #size-cells = <0>;
241 clocks = <&clock 298>; 301 clocks = <&clock 298>;
242 clock-names = "i2c"; 302 clock-names = "i2c";
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c4_bus>;
243 }; 305 };
244 306
245 i2c_5: i2c@12CB0000 { 307 i2c_5: i2c@12CB0000 {
@@ -250,6 +312,8 @@
250 #size-cells = <0>; 312 #size-cells = <0>;
251 clocks = <&clock 299>; 313 clocks = <&clock 299>;
252 clock-names = "i2c"; 314 clock-names = "i2c";
315 pinctrl-names = "default";
316 pinctrl-0 = <&i2c5_bus>;
253 }; 317 };
254 318
255 i2c_6: i2c@12CC0000 { 319 i2c_6: i2c@12CC0000 {
@@ -260,6 +324,8 @@
260 #size-cells = <0>; 324 #size-cells = <0>;
261 clocks = <&clock 300>; 325 clocks = <&clock 300>;
262 clock-names = "i2c"; 326 clock-names = "i2c";
327 pinctrl-names = "default";
328 pinctrl-0 = <&i2c6_bus>;
263 }; 329 };
264 330
265 i2c_7: i2c@12CD0000 { 331 i2c_7: i2c@12CD0000 {
@@ -270,6 +336,8 @@
270 #size-cells = <0>; 336 #size-cells = <0>;
271 clocks = <&clock 301>; 337 clocks = <&clock 301>;
272 clock-names = "i2c"; 338 clock-names = "i2c";
339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c7_bus>;
273 }; 341 };
274 342
275 i2c_8: i2c@12CE0000 { 343 i2c_8: i2c@12CE0000 {
@@ -302,6 +370,8 @@
302 #size-cells = <0>; 370 #size-cells = <0>;
303 clocks = <&clock 304>, <&clock 154>; 371 clocks = <&clock 304>, <&clock 154>;
304 clock-names = "spi", "spi_busclk0"; 372 clock-names = "spi", "spi_busclk0";
373 pinctrl-names = "default";
374 pinctrl-0 = <&spi0_bus>;
305 }; 375 };
306 376
307 spi_1: spi@12d30000 { 377 spi_1: spi@12d30000 {
@@ -315,6 +385,8 @@
315 #size-cells = <0>; 385 #size-cells = <0>;
316 clocks = <&clock 305>, <&clock 155>; 386 clocks = <&clock 305>, <&clock 155>;
317 clock-names = "spi", "spi_busclk0"; 387 clock-names = "spi", "spi_busclk0";
388 pinctrl-names = "default";
389 pinctrl-0 = <&spi1_bus>;
318 }; 390 };
319 391
320 spi_2: spi@12d40000 { 392 spi_2: spi@12d40000 {
@@ -328,6 +400,8 @@
328 #size-cells = <0>; 400 #size-cells = <0>;
329 clocks = <&clock 306>, <&clock 156>; 401 clocks = <&clock 306>, <&clock 156>;
330 clock-names = "spi", "spi_busclk0"; 402 clock-names = "spi", "spi_busclk0";
403 pinctrl-names = "default";
404 pinctrl-0 = <&spi2_bus>;
331 }; 405 };
332 406
333 dwmmc_0: dwmmc0@12200000 { 407 dwmmc_0: dwmmc0@12200000 {
@@ -381,6 +455,8 @@
381 samsung,supports-rstclr; 455 samsung,supports-rstclr;
382 samsung,supports-secdai; 456 samsung,supports-secdai;
383 samsung,idma-addr = <0x03000000>; 457 samsung,idma-addr = <0x03000000>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&i2s0_bus>;
384 }; 460 };
385 461
386 i2s1: i2s@12D60000 { 462 i2s1: i2s@12D60000 {
@@ -389,6 +465,8 @@
389 dmas = <&pdma1 12 465 dmas = <&pdma1 12
390 &pdma1 11>; 466 &pdma1 11>;
391 dma-names = "tx", "rx"; 467 dma-names = "tx", "rx";
468 pinctrl-names = "default";
469 pinctrl-0 = <&i2s1_bus>;
392 }; 470 };
393 471
394 i2s2: i2s@12D70000 { 472 i2s2: i2s@12D70000 {
@@ -397,18 +475,26 @@
397 dmas = <&pdma0 12 475 dmas = <&pdma0 12
398 &pdma0 11>; 476 &pdma0 11>;
399 dma-names = "tx", "rx"; 477 dma-names = "tx", "rx";
478 pinctrl-names = "default";
479 pinctrl-0 = <&i2s2_bus>;
400 }; 480 };
401 481
402 usb@12110000 { 482 usb@12110000 {
403 compatible = "samsung,exynos4210-ehci"; 483 compatible = "samsung,exynos4210-ehci";
404 reg = <0x12110000 0x100>; 484 reg = <0x12110000 0x100>;
405 interrupts = <0 71 0>; 485 interrupts = <0 71 0>;
486
487 clocks = <&clock 285>;
488 clock-names = "usbhost";
406 }; 489 };
407 490
408 usb@12120000 { 491 usb@12120000 {
409 compatible = "samsung,exynos4210-ohci"; 492 compatible = "samsung,exynos4210-ohci";
410 reg = <0x12120000 0x100>; 493 reg = <0x12120000 0x100>;
411 interrupts = <0 71 0>; 494 interrupts = <0 71 0>;
495
496 clocks = <&clock 285>;
497 clock-names = "usbhost";
412 }; 498 };
413 499
414 amba { 500 amba {
@@ -463,254 +549,6 @@
463 }; 549 };
464 }; 550 };
465 551
466 gpio-controllers {
467 #address-cells = <1>;
468 #size-cells = <1>;
469 gpio-controller;
470 ranges;
471
472 gpa0: gpio-controller@11400000 {
473 compatible = "samsung,exynos4-gpio";
474 reg = <0x11400000 0x20>;
475 #gpio-cells = <4>;
476 };
477
478 gpa1: gpio-controller@11400020 {
479 compatible = "samsung,exynos4-gpio";
480 reg = <0x11400020 0x20>;
481 #gpio-cells = <4>;
482 };
483
484 gpa2: gpio-controller@11400040 {
485 compatible = "samsung,exynos4-gpio";
486 reg = <0x11400040 0x20>;
487 #gpio-cells = <4>;
488 };
489
490 gpb0: gpio-controller@11400060 {
491 compatible = "samsung,exynos4-gpio";
492 reg = <0x11400060 0x20>;
493 #gpio-cells = <4>;
494 };
495
496 gpb1: gpio-controller@11400080 {
497 compatible = "samsung,exynos4-gpio";
498 reg = <0x11400080 0x20>;
499 #gpio-cells = <4>;
500 };
501
502 gpb2: gpio-controller@114000A0 {
503 compatible = "samsung,exynos4-gpio";
504 reg = <0x114000A0 0x20>;
505 #gpio-cells = <4>;
506 };
507
508 gpb3: gpio-controller@114000C0 {
509 compatible = "samsung,exynos4-gpio";
510 reg = <0x114000C0 0x20>;
511 #gpio-cells = <4>;
512 };
513
514 gpc0: gpio-controller@114000E0 {
515 compatible = "samsung,exynos4-gpio";
516 reg = <0x114000E0 0x20>;
517 #gpio-cells = <4>;
518 };
519
520 gpc1: gpio-controller@11400100 {
521 compatible = "samsung,exynos4-gpio";
522 reg = <0x11400100 0x20>;
523 #gpio-cells = <4>;
524 };
525
526 gpc2: gpio-controller@11400120 {
527 compatible = "samsung,exynos4-gpio";
528 reg = <0x11400120 0x20>;
529 #gpio-cells = <4>;
530 };
531
532 gpc3: gpio-controller@11400140 {
533 compatible = "samsung,exynos4-gpio";
534 reg = <0x11400140 0x20>;
535 #gpio-cells = <4>;
536 };
537
538 gpc4: gpio-controller@114002E0 {
539 compatible = "samsung,exynos4-gpio";
540 reg = <0x114002E0 0x20>;
541 #gpio-cells = <4>;
542 };
543
544 gpd0: gpio-controller@11400160 {
545 compatible = "samsung,exynos4-gpio";
546 reg = <0x11400160 0x20>;
547 #gpio-cells = <4>;
548 };
549
550 gpd1: gpio-controller@11400180 {
551 compatible = "samsung,exynos4-gpio";
552 reg = <0x11400180 0x20>;
553 #gpio-cells = <4>;
554 };
555
556 gpy0: gpio-controller@114001A0 {
557 compatible = "samsung,exynos4-gpio";
558 reg = <0x114001A0 0x20>;
559 #gpio-cells = <4>;
560 };
561
562 gpy1: gpio-controller@114001C0 {
563 compatible = "samsung,exynos4-gpio";
564 reg = <0x114001C0 0x20>;
565 #gpio-cells = <4>;
566 };
567
568 gpy2: gpio-controller@114001E0 {
569 compatible = "samsung,exynos4-gpio";
570 reg = <0x114001E0 0x20>;
571 #gpio-cells = <4>;
572 };
573
574 gpy3: gpio-controller@11400200 {
575 compatible = "samsung,exynos4-gpio";
576 reg = <0x11400200 0x20>;
577 #gpio-cells = <4>;
578 };
579
580 gpy4: gpio-controller@11400220 {
581 compatible = "samsung,exynos4-gpio";
582 reg = <0x11400220 0x20>;
583 #gpio-cells = <4>;
584 };
585
586 gpy5: gpio-controller@11400240 {
587 compatible = "samsung,exynos4-gpio";
588 reg = <0x11400240 0x20>;
589 #gpio-cells = <4>;
590 };
591
592 gpy6: gpio-controller@11400260 {
593 compatible = "samsung,exynos4-gpio";
594 reg = <0x11400260 0x20>;
595 #gpio-cells = <4>;
596 };
597
598 gpx0: gpio-controller@11400C00 {
599 compatible = "samsung,exynos4-gpio";
600 reg = <0x11400C00 0x20>;
601 #gpio-cells = <4>;
602 };
603
604 gpx1: gpio-controller@11400C20 {
605 compatible = "samsung,exynos4-gpio";
606 reg = <0x11400C20 0x20>;
607 #gpio-cells = <4>;
608 };
609
610 gpx2: gpio-controller@11400C40 {
611 compatible = "samsung,exynos4-gpio";
612 reg = <0x11400C40 0x20>;
613 #gpio-cells = <4>;
614 };
615
616 gpx3: gpio-controller@11400C60 {
617 compatible = "samsung,exynos4-gpio";
618 reg = <0x11400C60 0x20>;
619 #gpio-cells = <4>;
620 };
621
622 gpe0: gpio-controller@13400000 {
623 compatible = "samsung,exynos4-gpio";
624 reg = <0x13400000 0x20>;
625 #gpio-cells = <4>;
626 };
627
628 gpe1: gpio-controller@13400020 {
629 compatible = "samsung,exynos4-gpio";
630 reg = <0x13400020 0x20>;
631 #gpio-cells = <4>;
632 };
633
634 gpf0: gpio-controller@13400040 {
635 compatible = "samsung,exynos4-gpio";
636 reg = <0x13400040 0x20>;
637 #gpio-cells = <4>;
638 };
639
640 gpf1: gpio-controller@13400060 {
641 compatible = "samsung,exynos4-gpio";
642 reg = <0x13400060 0x20>;
643 #gpio-cells = <4>;
644 };
645
646 gpg0: gpio-controller@13400080 {
647 compatible = "samsung,exynos4-gpio";
648 reg = <0x13400080 0x20>;
649 #gpio-cells = <4>;
650 };
651
652 gpg1: gpio-controller@134000A0 {
653 compatible = "samsung,exynos4-gpio";
654 reg = <0x134000A0 0x20>;
655 #gpio-cells = <4>;
656 };
657
658 gpg2: gpio-controller@134000C0 {
659 compatible = "samsung,exynos4-gpio";
660 reg = <0x134000C0 0x20>;
661 #gpio-cells = <4>;
662 };
663
664 gph0: gpio-controller@134000E0 {
665 compatible = "samsung,exynos4-gpio";
666 reg = <0x134000E0 0x20>;
667 #gpio-cells = <4>;
668 };
669
670 gph1: gpio-controller@13400100 {
671 compatible = "samsung,exynos4-gpio";
672 reg = <0x13400100 0x20>;
673 #gpio-cells = <4>;
674 };
675
676 gpv0: gpio-controller@10D10000 {
677 compatible = "samsung,exynos4-gpio";
678 reg = <0x10D10000 0x20>;
679 #gpio-cells = <4>;
680 };
681
682 gpv1: gpio-controller@10D10020 {
683 compatible = "samsung,exynos4-gpio";
684 reg = <0x10D10020 0x20>;
685 #gpio-cells = <4>;
686 };
687
688 gpv2: gpio-controller@10D10040 {
689 compatible = "samsung,exynos4-gpio";
690 reg = <0x10D10060 0x20>;
691 #gpio-cells = <4>;
692 };
693
694 gpv3: gpio-controller@10D10060 {
695 compatible = "samsung,exynos4-gpio";
696 reg = <0x10D10080 0x20>;
697 #gpio-cells = <4>;
698 };
699
700 gpv4: gpio-controller@10D10080 {
701 compatible = "samsung,exynos4-gpio";
702 reg = <0x10D100C0 0x20>;
703 #gpio-cells = <4>;
704 };
705
706 gpz: gpio-controller@03860000 {
707 compatible = "samsung,exynos4-gpio";
708 reg = <0x03860000 0x20>;
709 #gpio-cells = <4>;
710 };
711 };
712
713
714 gsc_0: gsc@0x13e00000 { 552 gsc_0: gsc@0x13e00000 {
715 compatible = "samsung,exynos5-gsc"; 553 compatible = "samsung,exynos5-gsc";
716 reg = <0x13e00000 0x1000>; 554 reg = <0x13e00000 0x1000>;
@@ -776,4 +614,14 @@
776 samsung,enable-mask = <1>; 614 samsung,enable-mask = <1>;
777 }; 615 };
778 }; 616 };
617
618 fimd {
619 compatible = "samsung,exynos5250-fimd";
620 interrupt-parent = <&combiner>;
621 reg = <0x14400000 0x40000>;
622 interrupt-names = "fifo", "vsync", "lcd_sys";
623 interrupts = <18 4>, <18 5>, <18 6>;
624 clocks = <&clock 133>, <&clock 339>;
625 clock-names = "sclk_fimd", "fimd";
626 };
779}; 627};
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
new file mode 100644
index 000000000000..ef747b52b674
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -0,0 +1,39 @@
1/*
2 * SAMSUNG SD5v1 board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13/include/ "exynos5440.dtsi"
14
15/ {
16 model = "SAMSUNG SD5v1 board based on EXYNOS5440";
17 compatible = "samsung,sd5v1", "samsung,exynos5440";
18
19 chosen {
20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
21 };
22
23 fixed-rate-clocks {
24 xtal {
25 compatible = "samsung,clock-xtal";
26 clock-frequency = <50000000>;
27 };
28 };
29
30 gmac: ethernet@00230000 {
31 fixed_phy;
32 phy_addr = <1>;
33 };
34
35 spi {
36 status = "disabled";
37 };
38
39};
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index a21eb4cbe893..d55042beb5c5 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -16,12 +16,8 @@
16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; 16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
17 compatible = "samsung,ssdk5440", "samsung,exynos5440"; 17 compatible = "samsung,ssdk5440", "samsung,exynos5440";
18 18
19 memory {
20 reg = <0x80000000 0x80000000>;
21 };
22
23 chosen { 19 chosen {
24 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc"; 20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
25 }; 21 };
26 22
27 spi { 23 spi {
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 48cc96aa0b5f..f6b1c8973845 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -26,7 +26,11 @@
26 compatible = "arm,cortex-a15-gic"; 26 compatible = "arm,cortex-a15-gic";
27 #interrupt-cells = <3>; 27 #interrupt-cells = <3>;
28 interrupt-controller; 28 interrupt-controller;
29 reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>; 29 reg = <0x2E1000 0x1000>,
30 <0x2E2000 0x1000>,
31 <0x2E4000 0x2000>,
32 <0x2E6000 0x2000>;
33 interrupts = <1 9 0xf04>;
30 }; 34 };
31 35
32 cpus { 36 cpus {
@@ -51,6 +55,14 @@
51 }; 55 };
52 }; 56 };
53 57
58 arm-pmu {
59 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
60 interrupts = <0 52 4>,
61 <0 53 4>,
62 <0 54 4>,
63 <0 55 4>;
64 };
65
54 timer { 66 timer {
55 compatible = "arm,cortex-a15-timer", 67 compatible = "arm,cortex-a15-timer",
56 "arm,armv7-timer"; 68 "arm,armv7-timer";
@@ -61,6 +73,18 @@
61 clock-frequency = <50000000>; 73 clock-frequency = <50000000>;
62 }; 74 };
63 75
76 cpufreq@160000 {
77 compatible = "samsung,exynos5440-cpufreq";
78 reg = <0x160000 0x1000>;
79 interrupts = <0 57 0>;
80 operating-points = <
81 /* KHz uV */
82 1200000 1025000
83 1000000 975000
84 800000 925000
85 >;
86 };
87
64 serial@B0000 { 88 serial@B0000 {
65 compatible = "samsung,exynos4210-uart"; 89 compatible = "samsung,exynos4210-uart";
66 reg = <0xB0000 0x1000>; 90 reg = <0xB0000 0x1000>;
@@ -92,6 +116,8 @@
92 pinctrl { 116 pinctrl {
93 compatible = "samsung,exynos5440-pinctrl"; 117 compatible = "samsung,exynos5440-pinctrl";
94 reg = <0xE0000 0x1000>; 118 reg = <0xE0000 0x1000>;
119 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
120 <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
95 interrupt-controller; 121 interrupt-controller;
96 #interrupt-cells = <2>; 122 #interrupt-cells = <2>;
97 #gpio-cells = <2>; 123 #gpio-cells = <2>;
@@ -141,6 +167,17 @@
141 clock-names = "watchdog"; 167 clock-names = "watchdog";
142 }; 168 };
143 169
170 gmac: ethernet@00230000 {
171 compatible = "snps,dwmac-3.70a";
172 reg = <0x00230000 0x8000>;
173 interrupt-parent = <&gic>;
174 interrupts = <0 31 4>;
175 interrupt-names = "macirq";
176 phy-mode = "sgmii";
177 clocks = <&clock 25>;
178 clock-names = "stmmaceth";
179 };
180
144 amba { 181 amba {
145 #address-cells = <1>; 182 #address-cells = <1>;
146 #size-cells = <1>; 183 #size-cells = <1>;
@@ -148,22 +185,22 @@
148 interrupt-parent = <&gic>; 185 interrupt-parent = <&gic>;
149 ranges; 186 ranges;
150 187
151 pdma0: pdma@121A0000 { 188 pdma0: pdma@00121000 {
152 compatible = "arm,pl330", "arm,primecell"; 189 compatible = "arm,pl330", "arm,primecell";
153 reg = <0x120000 0x1000>; 190 reg = <0x121000 0x1000>;
154 interrupts = <0 34 0>; 191 interrupts = <0 46 0>;
155 clocks = <&clock 21>; 192 clocks = <&clock 8>;
156 clock-names = "apb_pclk"; 193 clock-names = "apb_pclk";
157 #dma-cells = <1>; 194 #dma-cells = <1>;
158 #dma-channels = <8>; 195 #dma-channels = <8>;
159 #dma-requests = <32>; 196 #dma-requests = <32>;
160 }; 197 };
161 198
162 pdma1: pdma@121B0000 { 199 pdma1: pdma@00120000 {
163 compatible = "arm,pl330", "arm,primecell"; 200 compatible = "arm,pl330", "arm,primecell";
164 reg = <0x121000 0x1000>; 201 reg = <0x120000 0x1000>;
165 interrupts = <0 35 0>; 202 interrupts = <0 47 0>;
166 clocks = <&clock 21>; 203 clocks = <&clock 8>;
167 clock-names = "apb_pclk"; 204 clock-names = "apb_pclk";
168 #dma-cells = <1>; 205 #dma-cells = <1>;
169 #dma-channels = <8>; 206 #dma-channels = <8>;
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 035c13f9d3c0..da0588a04131 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -59,8 +59,33 @@
59 lcdif@80030000 { 59 lcdif@80030000 {
60 pinctrl-names = "default"; 60 pinctrl-names = "default";
61 pinctrl-0 = <&lcdif_24bit_pins_a>; 61 pinctrl-0 = <&lcdif_24bit_pins_a>;
62 panel-enable-gpios = <&gpio1 18 0>; 62 lcd-supply = <&reg_lcd_3v3>;
63 display = <&display>;
63 status = "okay"; 64 status = "okay";
65
66 display: display {
67 bits-per-pixel = <32>;
68 bus-width = <24>;
69
70 display-timings {
71 native-mode = <&timing0>;
72 timing0: timing0 {
73 clock-frequency = <9200000>;
74 hactive = <480>;
75 vactive = <272>;
76 hback-porch = <15>;
77 hfront-porch = <8>;
78 vback-porch = <12>;
79 vfront-porch = <4>;
80 hsync-len = <1>;
81 vsync-len = <1>;
82 hsync-active = <0>;
83 vsync-active = <0>;
84 de-active = <1>;
85 pixelclk-active = <0>;
86 };
87 };
88 };
64 }; 89 };
65 }; 90 };
66 91
@@ -95,6 +120,15 @@
95 regulator-max-microvolt = <3300000>; 120 regulator-max-microvolt = <3300000>;
96 gpio = <&gpio1 29 0>; 121 gpio = <&gpio1 29 0>;
97 }; 122 };
123
124 reg_lcd_3v3: lcd-3v3 {
125 compatible = "regulator-fixed";
126 regulator-name = "lcd-3v3";
127 regulator-min-microvolt = <3300000>;
128 regulator-max-microvolt = <3300000>;
129 gpio = <&gpio1 18 0>;
130 enable-active-high;
131 };
98 }; 132 };
99 133
100 backlight { 134 backlight {
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index e7484e4ea659..d107c4af321f 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -29,6 +29,7 @@
29 pinctrl-names = "default"; 29 pinctrl-names = "default";
30 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; 30 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
31 bus-width = <4>; 31 bus-width = <4>;
32 broken-cd;
32 status = "okay"; 33 status = "okay";
33 }; 34 };
34 35
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index ad2d79324cd3..73fd7d0887b5 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -49,9 +49,15 @@
49 reg = <0x80000000 0x2000>; 49 reg = <0x80000000 0x2000>;
50 }; 50 };
51 51
52 dma-apbh@80004000 { 52 dma_apbh: dma-apbh@80004000 {
53 compatible = "fsl,imx23-dma-apbh"; 53 compatible = "fsl,imx23-dma-apbh";
54 reg = <0x80004000 0x2000>; 54 reg = <0x80004000 0x2000>;
55 interrupts = <0 14 20 0
56 13 13 13 13>;
57 interrupt-names = "empty", "ssp0", "ssp1", "empty",
58 "gpmi0", "gpmi1", "gpmi2", "gpmi3";
59 #dma-cells = <1>;
60 dma-channels = <8>;
55 clocks = <&clks 15>; 61 clocks = <&clks 15>;
56 }; 62 };
57 63
@@ -70,6 +76,8 @@
70 interrupt-names = "gpmi-dma", "bch"; 76 interrupt-names = "gpmi-dma", "bch";
71 clocks = <&clks 34>; 77 clocks = <&clks 34>;
72 clock-names = "gpmi_io"; 78 clock-names = "gpmi_io";
79 dmas = <&dma_apbh 4>;
80 dma-names = "rx-tx";
73 fsl,gpmi-dma-channel = <4>; 81 fsl,gpmi-dma-channel = <4>;
74 status = "disabled"; 82 status = "disabled";
75 }; 83 };
@@ -78,6 +86,8 @@
78 reg = <0x80010000 0x2000>; 86 reg = <0x80010000 0x2000>;
79 interrupts = <15 14>; 87 interrupts = <15 14>;
80 clocks = <&clks 33>; 88 clocks = <&clks 33>;
89 dmas = <&dma_apbh 1>;
90 dma-names = "rx-tx";
81 fsl,ssp-dma-channel = <1>; 91 fsl,ssp-dma-channel = <1>;
82 status = "disabled"; 92 status = "disabled";
83 }; 93 };
@@ -305,9 +315,19 @@
305 status = "disabled"; 315 status = "disabled";
306 }; 316 };
307 317
308 dma-apbx@80024000 { 318 dma_apbx: dma-apbx@80024000 {
309 compatible = "fsl,imx23-dma-apbx"; 319 compatible = "fsl,imx23-dma-apbx";
310 reg = <0x80024000 0x2000>; 320 reg = <0x80024000 0x2000>;
321 interrupts = <7 5 9 26
322 19 0 25 23
323 60 58 9 0
324 0 0 0 0>;
325 interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
326 "saif0", "empty", "auart0-rx", "auart0-tx",
327 "auart1-rx", "auart1-tx", "saif1", "empty",
328 "empty", "empty", "empty", "empty";
329 #dma-cells = <1>;
330 dma-channels = <16>;
311 clocks = <&clks 16>; 331 clocks = <&clks 16>;
312 }; 332 };
313 333
@@ -344,6 +364,8 @@
344 reg = <0x80034000 0x2000>; 364 reg = <0x80034000 0x2000>;
345 interrupts = <2 20>; 365 interrupts = <2 20>;
346 clocks = <&clks 33>; 366 clocks = <&clks 33>;
367 dmas = <&dma_apbh 2>;
368 dma-names = "rx-tx";
347 fsl,ssp-dma-channel = <2>; 369 fsl,ssp-dma-channel = <2>;
348 status = "disabled"; 370 status = "disabled";
349 }; 371 };
@@ -369,6 +391,8 @@
369 391
370 saif0: saif@80042000 { 392 saif0: saif@80042000 {
371 reg = <0x80042000 0x2000>; 393 reg = <0x80042000 0x2000>;
394 dmas = <&dma_apbx 4>;
395 dma-names = "rx-tx";
372 status = "disabled"; 396 status = "disabled";
373 }; 397 };
374 398
@@ -379,16 +403,22 @@
379 403
380 saif1: saif@80046000 { 404 saif1: saif@80046000 {
381 reg = <0x80046000 0x2000>; 405 reg = <0x80046000 0x2000>;
406 dmas = <&dma_apbx 10>;
407 dma-names = "rx-tx";
382 status = "disabled"; 408 status = "disabled";
383 }; 409 };
384 410
385 audio-out@80048000 { 411 audio-out@80048000 {
386 reg = <0x80048000 0x2000>; 412 reg = <0x80048000 0x2000>;
413 dmas = <&dma_apbx 1>;
414 dma-names = "tx";
387 status = "disabled"; 415 status = "disabled";
388 }; 416 };
389 417
390 audio-in@8004c000 { 418 audio-in@8004c000 {
391 reg = <0x8004c000 0x2000>; 419 reg = <0x8004c000 0x2000>;
420 dmas = <&dma_apbx 0>;
421 dma-names = "rx";
392 status = "disabled"; 422 status = "disabled";
393 }; 423 };
394 424
@@ -401,11 +431,15 @@
401 431
402 spdif@80054000 { 432 spdif@80054000 {
403 reg = <0x80054000 2000>; 433 reg = <0x80054000 2000>;
434 dmas = <&dma_apbx 2>;
435 dma-names = "tx";
404 status = "disabled"; 436 status = "disabled";
405 }; 437 };
406 438
407 i2c@80058000 { 439 i2c@80058000 {
408 reg = <0x80058000 0x2000>; 440 reg = <0x80058000 0x2000>;
441 dmas = <&dma_apbx 3>;
442 dma-names = "rx-tx";
409 status = "disabled"; 443 status = "disabled";
410 }; 444 };
411 445
@@ -436,6 +470,8 @@
436 reg = <0x8006c000 0x2000>; 470 reg = <0x8006c000 0x2000>;
437 interrupts = <24 25 23>; 471 interrupts = <24 25 23>;
438 clocks = <&clks 32>; 472 clocks = <&clks 32>;
473 dmas = <&dma_apbx 6>, <&dma_apbx 7>;
474 dma-names = "rx", "tx";
439 status = "disabled"; 475 status = "disabled";
440 }; 476 };
441 477
@@ -444,6 +480,8 @@
444 reg = <0x8006e000 0x2000>; 480 reg = <0x8006e000 0x2000>;
445 interrupts = <59 60 58>; 481 interrupts = <59 60 58>;
446 clocks = <&clks 32>; 482 clocks = <&clks 32>;
483 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
484 dma-names = "rx", "tx";
447 status = "disabled"; 485 status = "disabled";
448 }; 486 };
449 487
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 6d8865bfb4b7..3d905d16cbec 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -72,7 +72,32 @@
72 pinctrl-names = "default"; 72 pinctrl-names = "default";
73 pinctrl-0 = <&lcdif_16bit_pins_a 73 pinctrl-0 = <&lcdif_16bit_pins_a
74 &lcdif_pins_apf28dev>; 74 &lcdif_pins_apf28dev>;
75 display = <&display>;
75 status = "okay"; 76 status = "okay";
77
78 display: display {
79 bits-per-pixel = <16>;
80 bus-width = <16>;
81
82 display-timings {
83 native-mode = <&timing0>;
84 timing0: timing0 {
85 clock-frequency = <33000033>;
86 hactive = <800>;
87 vactive = <480>;
88 hback-porch = <96>;
89 hfront-porch = <96>;
90 vback-porch = <20>;
91 vfront-porch = <21>;
92 hsync-len = <64>;
93 vsync-len = <4>;
94 hsync-active = <1>;
95 vsync-active = <1>;
96 de-active = <1>;
97 pixelclk-active = <0>;
98 };
99 };
100 };
76 }; 101 };
77 }; 102 };
78 103
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index 5171667a7763..43bf3c796cba 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -94,7 +94,32 @@
94 pinctrl-names = "default"; 94 pinctrl-names = "default";
95 pinctrl-0 = <&lcdif_24bit_pins_a 95 pinctrl-0 = <&lcdif_24bit_pins_a
96 &lcdif_pins_apx4>; 96 &lcdif_pins_apx4>;
97 display = <&display>;
97 status = "okay"; 98 status = "okay";
99
100 display: display {
101 bits-per-pixel = <32>;
102 bus-width = <24>;
103
104 display-timings {
105 native-mode = <&timing0>;
106 timing0: timing0 {
107 clock-frequency = <30000000>;
108 hactive = <800>;
109 vactive = <480>;
110 hback-porch = <88>;
111 hfront-porch = <40>;
112 vback-porch = <32>;
113 vfront-porch = <13>;
114 hsync-len = <48>;
115 vsync-len = <3>;
116 hsync-active = <1>;
117 vsync-active = <1>;
118 de-active = <1>;
119 pixelclk-active = <0>;
120 };
121 };
122 };
98 }; 123 };
99 }; 124 };
100 125
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index a0d3e9f1738e..063e62059890 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -30,7 +30,6 @@
30 reg = <0>; 30 reg = <0>;
31 fsl,pinmux-ids = < 31 fsl,pinmux-ids = <
32 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ 32 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
33 0x1153 /* MX28_PAD_LCD_D22__GPIO_1_21 */
34 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ 33 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
35 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ 34 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
36 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ 35 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
@@ -120,13 +119,48 @@
120 fsl,voltage = <1>; 119 fsl,voltage = <1>;
121 fsl,pull-up = <0>; 120 fsl,pull-up = <0>;
122 }; 121 };
122
123 w1_gpio_pins: w1-gpio@0 {
124 reg = <0>;
125 fsl,pinmux-ids = <
126 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */
127 >;
128 fsl,drive-strength = <1>;
129 fsl,voltage = <1>;
130 fsl,pull-up = <0>; /* 0 will enable the keeper */
131 };
123 }; 132 };
124 133
125 lcdif@80030000 { 134 lcdif@80030000 {
126 pinctrl-names = "default"; 135 pinctrl-names = "default";
127 pinctrl-0 = <&lcdif_18bit_pins_cfa10049 136 pinctrl-0 = <&lcdif_18bit_pins_cfa10049
128 &lcdif_pins_cfa10049>; 137 &lcdif_pins_cfa10049>;
138 display = <&display>;
129 status = "okay"; 139 status = "okay";
140
141 display: display {
142 bits-per-pixel = <32>;
143 bus-width = <18>;
144
145 display-timings {
146 native-mode = <&timing0>;
147 timing0: timing0 {
148 clock-frequency = <9216000>;
149 hactive = <320>;
150 vactive = <480>;
151 hback-porch = <2>;
152 hfront-porch = <2>;
153 vback-porch = <2>;
154 vfront-porch = <2>;
155 hsync-len = <15>;
156 vsync-len = <15>;
157 hsync-active = <0>;
158 vsync-active = <0>;
159 de-active = <1>;
160 pixelclk-active = <1>;
161 };
162 };
163 };
130 }; 164 };
131 }; 165 };
132 166
@@ -183,6 +217,11 @@
183 usbphy1: usbphy@8007e000 { 217 usbphy1: usbphy@8007e000 {
184 status = "okay"; 218 status = "okay";
185 }; 219 };
220
221 lradc@80050000 {
222 status = "okay";
223 fsl,lradc-touchscreen-wires = <4>;
224 };
186 }; 225 };
187 }; 226 };
188 227
@@ -304,5 +343,14 @@
304 pwms = <&pwm 3 5000000>; 343 pwms = <&pwm 3 5000000>;
305 brightness-levels = <0 4 8 16 32 64 128 255>; 344 brightness-levels = <0 4 8 16 32 64 128 255>;
306 default-brightness-level = <6>; 345 default-brightness-level = <6>;
346
347 };
348
349 onewire@0 {
350 compatible = "w1-gpio";
351 pinctrl-names = "default";
352 pinctrl-0 = <&w1_gpio_pins>;
353 status = "okay";
354 gpios = <&gpio1 21 0>;
307 }; 355 };
308}; 356};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 2da316e04409..3637bf3b1d59 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -123,8 +123,33 @@
123 pinctrl-names = "default"; 123 pinctrl-names = "default";
124 pinctrl-0 = <&lcdif_24bit_pins_a 124 pinctrl-0 = <&lcdif_24bit_pins_a
125 &lcdif_pins_evk>; 125 &lcdif_pins_evk>;
126 panel-enable-gpios = <&gpio3 30 0>; 126 lcd-supply = <&reg_lcd_3v3>;
127 display = <&display>;
127 status = "okay"; 128 status = "okay";
129
130 display: display {
131 bits-per-pixel = <32>;
132 bus-width = <24>;
133
134 display-timings {
135 native-mode = <&timing0>;
136 timing0: timing0 {
137 clock-frequency = <33500000>;
138 hactive = <800>;
139 vactive = <480>;
140 hback-porch = <89>;
141 hfront-porch = <164>;
142 vback-porch = <23>;
143 vfront-porch = <10>;
144 hsync-len = <10>;
145 vsync-len = <10>;
146 hsync-active = <0>;
147 vsync-active = <0>;
148 de-active = <1>;
149 pixelclk-active = <0>;
150 };
151 };
152 };
128 }; 153 };
129 154
130 can0: can@80032000 { 155 can0: can@80032000 {
@@ -285,6 +310,15 @@
285 gpio = <&gpio3 8 0>; 310 gpio = <&gpio3 8 0>;
286 enable-active-high; 311 enable-active-high;
287 }; 312 };
313
314 reg_lcd_3v3: lcd-3v3 {
315 compatible = "regulator-fixed";
316 regulator-name = "lcd-3v3";
317 regulator-min-microvolt = <3300000>;
318 regulator-max-microvolt = <3300000>;
319 gpio = <&gpio3 30 0>;
320 enable-active-high;
321 };
288 }; 322 };
289 323
290 sound { 324 sound {
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index fd36e1cca104..5aa44e05c9f5 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -119,7 +119,32 @@
119 pinctrl-names = "default"; 119 pinctrl-names = "default";
120 pinctrl-0 = <&lcdif_24bit_pins_a 120 pinctrl-0 = <&lcdif_24bit_pins_a
121 &lcdif_pins_m28>; 121 &lcdif_pins_m28>;
122 display = <&display>;
122 status = "okay"; 123 status = "okay";
124
125 display: display {
126 bits-per-pixel = <16>;
127 bus-width = <18>;
128
129 display-timings {
130 native-mode = <&timing0>;
131 timing0: timing0 {
132 clock-frequency = <33260000>;
133 hactive = <800>;
134 vactive = <480>;
135 hback-porch = <0>;
136 hfront-porch = <256>;
137 vback-porch = <0>;
138 vfront-porch = <45>;
139 hsync-len = <1>;
140 vsync-len = <1>;
141 hsync-active = <0>;
142 vsync-active = <0>;
143 de-active = <1>;
144 pixelclk-active = <1>;
145 };
146 };
147 };
123 }; 148 };
124 149
125 can0: can@80032000 { 150 can0: can@80032000 {
@@ -220,6 +245,8 @@
220 phy-mode = "rmii"; 245 phy-mode = "rmii";
221 pinctrl-names = "default"; 246 pinctrl-names = "default";
222 pinctrl-0 = <&mac0_pins_a>; 247 pinctrl-0 = <&mac0_pins_a>;
248 clocks = <&clks 57>, <&clks 57>;
249 clock-names = "ipg", "ahb";
223 status = "okay"; 250 status = "okay";
224 }; 251 };
225 252
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 64af2381c1b0..600f7cb51f3e 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -61,12 +61,24 @@
61 hsadc@80002000 { 61 hsadc@80002000 {
62 reg = <0x80002000 0x2000>; 62 reg = <0x80002000 0x2000>;
63 interrupts = <13 87>; 63 interrupts = <13 87>;
64 dmas = <&dma_apbh 12>;
65 dma-names = "rx";
64 status = "disabled"; 66 status = "disabled";
65 }; 67 };
66 68
67 dma-apbh@80004000 { 69 dma_apbh: dma-apbh@80004000 {
68 compatible = "fsl,imx28-dma-apbh"; 70 compatible = "fsl,imx28-dma-apbh";
69 reg = <0x80004000 0x2000>; 71 reg = <0x80004000 0x2000>;
72 interrupts = <82 83 84 85
73 88 88 88 88
74 88 88 88 88
75 87 86 0 0>;
76 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
77 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
78 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
79 "hsadc", "lcdif", "empty", "empty";
80 #dma-cells = <1>;
81 dma-channels = <16>;
70 clocks = <&clks 25>; 82 clocks = <&clks 25>;
71 }; 83 };
72 84
@@ -86,6 +98,8 @@
86 interrupt-names = "gpmi-dma", "bch"; 98 interrupt-names = "gpmi-dma", "bch";
87 clocks = <&clks 50>; 99 clocks = <&clks 50>;
88 clock-names = "gpmi_io"; 100 clock-names = "gpmi_io";
101 dmas = <&dma_apbh 4>;
102 dma-names = "rx-tx";
89 fsl,gpmi-dma-channel = <4>; 103 fsl,gpmi-dma-channel = <4>;
90 status = "disabled"; 104 status = "disabled";
91 }; 105 };
@@ -96,6 +110,8 @@
96 reg = <0x80010000 0x2000>; 110 reg = <0x80010000 0x2000>;
97 interrupts = <96 82>; 111 interrupts = <96 82>;
98 clocks = <&clks 46>; 112 clocks = <&clks 46>;
113 dmas = <&dma_apbh 0>;
114 dma-names = "rx-tx";
99 fsl,ssp-dma-channel = <0>; 115 fsl,ssp-dma-channel = <0>;
100 status = "disabled"; 116 status = "disabled";
101 }; 117 };
@@ -106,6 +122,8 @@
106 reg = <0x80012000 0x2000>; 122 reg = <0x80012000 0x2000>;
107 interrupts = <97 83>; 123 interrupts = <97 83>;
108 clocks = <&clks 47>; 124 clocks = <&clks 47>;
125 dmas = <&dma_apbh 1>;
126 dma-names = "rx-tx";
109 fsl,ssp-dma-channel = <1>; 127 fsl,ssp-dma-channel = <1>;
110 status = "disabled"; 128 status = "disabled";
111 }; 129 };
@@ -116,6 +134,8 @@
116 reg = <0x80014000 0x2000>; 134 reg = <0x80014000 0x2000>;
117 interrupts = <98 84>; 135 interrupts = <98 84>;
118 clocks = <&clks 48>; 136 clocks = <&clks 48>;
137 dmas = <&dma_apbh 2>;
138 dma-names = "rx-tx";
119 fsl,ssp-dma-channel = <2>; 139 fsl,ssp-dma-channel = <2>;
120 status = "disabled"; 140 status = "disabled";
121 }; 141 };
@@ -126,6 +146,8 @@
126 reg = <0x80016000 0x2000>; 146 reg = <0x80016000 0x2000>;
127 interrupts = <99 85>; 147 interrupts = <99 85>;
128 clocks = <&clks 49>; 148 clocks = <&clks 49>;
149 dmas = <&dma_apbh 3>;
150 dma-names = "rx-tx";
129 fsl,ssp-dma-channel = <3>; 151 fsl,ssp-dma-channel = <3>;
130 status = "disabled"; 152 status = "disabled";
131 }; 153 };
@@ -658,9 +680,19 @@
658 status = "disabled"; 680 status = "disabled";
659 }; 681 };
660 682
661 dma-apbx@80024000 { 683 dma_apbx: dma-apbx@80024000 {
662 compatible = "fsl,imx28-dma-apbx"; 684 compatible = "fsl,imx28-dma-apbx";
663 reg = <0x80024000 0x2000>; 685 reg = <0x80024000 0x2000>;
686 interrupts = <78 79 66 0
687 80 81 68 69
688 70 71 72 73
689 74 75 76 77>;
690 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
691 "saif0", "saif1", "i2c0", "i2c1",
692 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
693 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
694 #dma-cells = <1>;
695 dma-channels = <16>;
664 clocks = <&clks 26>; 696 clocks = <&clks 26>;
665 }; 697 };
666 698
@@ -692,6 +724,8 @@
692 reg = <0x80030000 0x2000>; 724 reg = <0x80030000 0x2000>;
693 interrupts = <38 86>; 725 interrupts = <38 86>;
694 clocks = <&clks 55>; 726 clocks = <&clks 55>;
727 dmas = <&dma_apbh 13>;
728 dma-names = "rx";
695 status = "disabled"; 729 status = "disabled";
696 }; 730 };
697 731
@@ -767,6 +801,8 @@
767 reg = <0x80042000 0x2000>; 801 reg = <0x80042000 0x2000>;
768 interrupts = <59 80>; 802 interrupts = <59 80>;
769 clocks = <&clks 53>; 803 clocks = <&clks 53>;
804 dmas = <&dma_apbx 4>;
805 dma-names = "rx-tx";
770 fsl,saif-dma-channel = <4>; 806 fsl,saif-dma-channel = <4>;
771 status = "disabled"; 807 status = "disabled";
772 }; 808 };
@@ -781,6 +817,8 @@
781 reg = <0x80046000 0x2000>; 817 reg = <0x80046000 0x2000>;
782 interrupts = <58 81>; 818 interrupts = <58 81>;
783 clocks = <&clks 54>; 819 clocks = <&clks 54>;
820 dmas = <&dma_apbx 5>;
821 dma-names = "rx-tx";
784 fsl,saif-dma-channel = <5>; 822 fsl,saif-dma-channel = <5>;
785 status = "disabled"; 823 status = "disabled";
786 }; 824 };
@@ -796,6 +834,8 @@
796 spdif@80054000 { 834 spdif@80054000 {
797 reg = <0x80054000 0x2000>; 835 reg = <0x80054000 0x2000>;
798 interrupts = <45 66>; 836 interrupts = <45 66>;
837 dmas = <&dma_apbx 2>;
838 dma-names = "tx";
799 status = "disabled"; 839 status = "disabled";
800 }; 840 };
801 841
@@ -812,6 +852,8 @@
812 reg = <0x80058000 0x2000>; 852 reg = <0x80058000 0x2000>;
813 interrupts = <111 68>; 853 interrupts = <111 68>;
814 clock-frequency = <100000>; 854 clock-frequency = <100000>;
855 dmas = <&dma_apbx 6>;
856 dma-names = "rx-tx";
815 fsl,i2c-dma-channel = <6>; 857 fsl,i2c-dma-channel = <6>;
816 status = "disabled"; 858 status = "disabled";
817 }; 859 };
@@ -823,6 +865,8 @@
823 reg = <0x8005a000 0x2000>; 865 reg = <0x8005a000 0x2000>;
824 interrupts = <110 69>; 866 interrupts = <110 69>;
825 clock-frequency = <100000>; 867 clock-frequency = <100000>;
868 dmas = <&dma_apbx 7>;
869 dma-names = "rx-tx";
826 fsl,i2c-dma-channel = <7>; 870 fsl,i2c-dma-channel = <7>;
827 status = "disabled"; 871 status = "disabled";
828 }; 872 };
@@ -847,6 +891,8 @@
847 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 891 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
848 reg = <0x8006a000 0x2000>; 892 reg = <0x8006a000 0x2000>;
849 interrupts = <112 70 71>; 893 interrupts = <112 70 71>;
894 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
895 dma-names = "rx", "tx";
850 fsl,auart-dma-channel = <8 9>; 896 fsl,auart-dma-channel = <8 9>;
851 clocks = <&clks 45>; 897 clocks = <&clks 45>;
852 status = "disabled"; 898 status = "disabled";
@@ -856,6 +902,8 @@
856 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 902 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
857 reg = <0x8006c000 0x2000>; 903 reg = <0x8006c000 0x2000>;
858 interrupts = <113 72 73>; 904 interrupts = <113 72 73>;
905 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
906 dma-names = "rx", "tx";
859 clocks = <&clks 45>; 907 clocks = <&clks 45>;
860 status = "disabled"; 908 status = "disabled";
861 }; 909 };
@@ -864,6 +912,8 @@
864 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 912 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
865 reg = <0x8006e000 0x2000>; 913 reg = <0x8006e000 0x2000>;
866 interrupts = <114 74 75>; 914 interrupts = <114 74 75>;
915 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
916 dma-names = "rx", "tx";
867 clocks = <&clks 45>; 917 clocks = <&clks 45>;
868 status = "disabled"; 918 status = "disabled";
869 }; 919 };
@@ -872,6 +922,8 @@
872 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 922 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
873 reg = <0x80070000 0x2000>; 923 reg = <0x80070000 0x2000>;
874 interrupts = <115 76 77>; 924 interrupts = <115 76 77>;
925 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
926 dma-names = "rx", "tx";
875 clocks = <&clks 45>; 927 clocks = <&clks 45>;
876 status = "disabled"; 928 status = "disabled";
877 }; 929 };
@@ -880,6 +932,8 @@
880 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 932 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
881 reg = <0x80072000 0x2000>; 933 reg = <0x80072000 0x2000>;
882 interrupts = <116 78 79>; 934 interrupts = <116 78 79>;
935 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
936 dma-names = "rx", "tx";
883 clocks = <&clks 45>; 937 clocks = <&clks 45>;
884 status = "disabled"; 938 status = "disabled";
885 }; 939 };
@@ -943,8 +997,8 @@
943 compatible = "fsl,imx28-fec"; 997 compatible = "fsl,imx28-fec";
944 reg = <0x800f0000 0x4000>; 998 reg = <0x800f0000 0x4000>;
945 interrupts = <101>; 999 interrupts = <101>;
946 clocks = <&clks 57>, <&clks 57>; 1000 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
947 clock-names = "ipg", "ahb"; 1001 clock-names = "ipg", "ahb", "enet_out";
948 status = "disabled"; 1002 status = "disabled";
949 }; 1003 };
950 1004
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 3cca7d39529d..9e8296e4c343 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -65,9 +65,13 @@
65 interrupt-parent = <&intc>; 65 interrupt-parent = <&intc>;
66 ranges; 66 ranges;
67 67
68 dma-apbh@00110000 { 68 dma_apbh: dma-apbh@00110000 {
69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>; 70 reg = <0x00110000 0x2000>;
71 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
72 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
73 #dma-cells = <1>;
74 dma-channels = <4>;
71 clocks = <&clks 106>; 75 clocks = <&clks 106>;
72 }; 76 };
73 77
@@ -83,6 +87,8 @@
83 <&clks 150>, <&clks 149>; 87 <&clks 150>, <&clks 149>;
84 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
85 "gpmi_bch_apb", "per1_bch"; 89 "gpmi_bch_apb", "per1_bch";
90 dmas = <&dma_apbh 0>;
91 dma-names = "rx-tx";
86 fsl,gpmi-dma-channel = <0>; 92 fsl,gpmi-dma-channel = <0>;
87 status = "disabled"; 93 status = "disabled";
88 }; 94 };
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 761c4b69b25b..37aa7487d4d8 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -26,6 +26,11 @@
26 }; 26 };
27 }; 27 };
28 28
29 pmu {
30 compatible = "arm,arm1136-pmu";
31 interrupts = <3>;
32 };
33
29 soc { 34 soc {
30 compatible = "ti,omap-infra"; 35 compatible = "ti,omap-infra";
31 mpu { 36 mpu {
@@ -49,6 +54,18 @@
49 reg = <0x480FE000 0x1000>; 54 reg = <0x480FE000 0x1000>;
50 }; 55 };
51 56
57 sdma: dma-controller@48056000 {
58 compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
59 reg = <0x48056000 0x1000>;
60 interrupts = <12>,
61 <13>,
62 <14>,
63 <15>;
64 #dma-cells = <1>;
65 #dma-channels = <32>;
66 #dma-requests = <64>;
67 };
68
52 uart1: serial@4806a000 { 69 uart1: serial@4806a000 {
53 compatible = "ti,omap2-uart"; 70 compatible = "ti,omap2-uart";
54 ti,hwmods = "uart1"; 71 ti,hwmods = "uart1";
@@ -68,28 +85,28 @@
68 }; 85 };
69 86
70 timer2: timer@4802a000 { 87 timer2: timer@4802a000 {
71 compatible = "ti,omap2-timer"; 88 compatible = "ti,omap2420-timer";
72 reg = <0x4802a000 0x400>; 89 reg = <0x4802a000 0x400>;
73 interrupts = <38>; 90 interrupts = <38>;
74 ti,hwmods = "timer2"; 91 ti,hwmods = "timer2";
75 }; 92 };
76 93
77 timer3: timer@48078000 { 94 timer3: timer@48078000 {
78 compatible = "ti,omap2-timer"; 95 compatible = "ti,omap2420-timer";
79 reg = <0x48078000 0x400>; 96 reg = <0x48078000 0x400>;
80 interrupts = <39>; 97 interrupts = <39>;
81 ti,hwmods = "timer3"; 98 ti,hwmods = "timer3";
82 }; 99 };
83 100
84 timer4: timer@4807a000 { 101 timer4: timer@4807a000 {
85 compatible = "ti,omap2-timer"; 102 compatible = "ti,omap2420-timer";
86 reg = <0x4807a000 0x400>; 103 reg = <0x4807a000 0x400>;
87 interrupts = <40>; 104 interrupts = <40>;
88 ti,hwmods = "timer4"; 105 ti,hwmods = "timer4";
89 }; 106 };
90 107
91 timer5: timer@4807c000 { 108 timer5: timer@4807c000 {
92 compatible = "ti,omap2-timer"; 109 compatible = "ti,omap2420-timer";
93 reg = <0x4807c000 0x400>; 110 reg = <0x4807c000 0x400>;
94 interrupts = <41>; 111 interrupts = <41>;
95 ti,hwmods = "timer5"; 112 ti,hwmods = "timer5";
@@ -97,7 +114,7 @@
97 }; 114 };
98 115
99 timer6: timer@4807e000 { 116 timer6: timer@4807e000 {
100 compatible = "ti,omap2-timer"; 117 compatible = "ti,omap2420-timer";
101 reg = <0x4807e000 0x400>; 118 reg = <0x4807e000 0x400>;
102 interrupts = <42>; 119 interrupts = <42>;
103 ti,hwmods = "timer6"; 120 ti,hwmods = "timer6";
@@ -105,7 +122,7 @@
105 }; 122 };
106 123
107 timer7: timer@48080000 { 124 timer7: timer@48080000 {
108 compatible = "ti,omap2-timer"; 125 compatible = "ti,omap2420-timer";
109 reg = <0x48080000 0x400>; 126 reg = <0x48080000 0x400>;
110 interrupts = <43>; 127 interrupts = <43>;
111 ti,hwmods = "timer7"; 128 ti,hwmods = "timer7";
@@ -113,7 +130,7 @@
113 }; 130 };
114 131
115 timer8: timer@48082000 { 132 timer8: timer@48082000 {
116 compatible = "ti,omap2-timer"; 133 compatible = "ti,omap2420-timer";
117 reg = <0x48082000 0x400>; 134 reg = <0x48082000 0x400>;
118 interrupts = <44>; 135 interrupts = <44>;
119 ti,hwmods = "timer8"; 136 ti,hwmods = "timer8";
@@ -121,7 +138,7 @@
121 }; 138 };
122 139
123 timer9: timer@48084000 { 140 timer9: timer@48084000 {
124 compatible = "ti,omap2-timer"; 141 compatible = "ti,omap2420-timer";
125 reg = <0x48084000 0x400>; 142 reg = <0x48084000 0x400>;
126 interrupts = <45>; 143 interrupts = <45>;
127 ti,hwmods = "timer9"; 144 ti,hwmods = "timer9";
@@ -129,7 +146,7 @@
129 }; 146 };
130 147
131 timer10: timer@48086000 { 148 timer10: timer@48086000 {
132 compatible = "ti,omap2-timer"; 149 compatible = "ti,omap2420-timer";
133 reg = <0x48086000 0x400>; 150 reg = <0x48086000 0x400>;
134 interrupts = <46>; 151 interrupts = <46>;
135 ti,hwmods = "timer10"; 152 ti,hwmods = "timer10";
@@ -137,7 +154,7 @@
137 }; 154 };
138 155
139 timer11: timer@48088000 { 156 timer11: timer@48088000 {
140 compatible = "ti,omap2-timer"; 157 compatible = "ti,omap2420-timer";
141 reg = <0x48088000 0x400>; 158 reg = <0x48088000 0x400>;
142 interrupts = <47>; 159 interrupts = <47>;
143 ti,hwmods = "timer11"; 160 ti,hwmods = "timer11";
@@ -145,7 +162,7 @@
145 }; 162 };
146 163
147 timer12: timer@4808a000 { 164 timer12: timer@4808a000 {
148 compatible = "ti,omap2-timer"; 165 compatible = "ti,omap2420-timer";
149 reg = <0x4808a000 0x400>; 166 reg = <0x4808a000 0x400>;
150 interrupts = <48>; 167 interrupts = <48>;
151 ti,hwmods = "timer12"; 168 ti,hwmods = "timer12";
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 9b0d07746cba..68282ee13e26 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -18,3 +18,49 @@
18 reg = <0x80000000 0x4000000>; /* 64 MB */ 18 reg = <0x80000000 0x4000000>; /* 64 MB */
19 }; 19 };
20}; 20};
21
22&gpmc {
23 ranges = <0 0 0x08000000 0x04000000>;
24
25 nor@0,0 {
26 compatible = "cfi-flash";
27 linux,mtd-name= "intel,ge28f256l18b85";
28 #address-cells = <1>;
29 #size-cells = <1>;
30 reg = <0 0 0x04000000>;
31 bank-width = <2>;
32
33 gpmc,mux-add-data = <2>;
34 gpmc,cs-on-ns = <10>;
35 gpmc,cs-rd-off-ns = <160>;
36 gpmc,cs-wr-off-ns = <160>;
37 gpmc,adv-on-ns = <20>;
38 gpmc,adv-rd-off-ns = <50>;
39 gpmc,adv-wr-off-ns = <50>;
40 gpmc,oe-on-ns = <60>;
41 gpmc,oe-off-ns = <120>;
42 gpmc,we-on-ns = <60>;
43 gpmc,we-off-ns = <120>;
44 gpmc,rd-cycle-ns = <170>;
45 gpmc,wr-cycle-ns = <170>;
46 gpmc,access-ns = <150>;
47 gpmc,page-burst-access-ns = <10>;
48
49 partition@0 {
50 label = "bootloader";
51 reg = <0 0x20000>;
52 };
53 partition@0x20000 {
54 label = "params";
55 reg = <0x20000 0x20000>;
56 };
57 partition@0x40000 {
58 label = "kernel";
59 reg = <0x40000 0x200000>;
60 };
61 partition@0x240000 {
62 label = "file-system";
63 reg = <0x240000 0x3dc0000>;
64 };
65 };
66};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index af6560908905..da5b285b73be 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -29,6 +29,65 @@
29 pinctrl-single,function-mask = <0x3f>; 29 pinctrl-single,function-mask = <0x3f>;
30 }; 30 };
31 31
32 gpio1: gpio@48018000 {
33 compatible = "ti,omap2-gpio";
34 reg = <0x48018000 0x200>;
35 interrupts = <29>;
36 ti,hwmods = "gpio1";
37 ti,gpio-always-on;
38 #gpio-cells = <2>;
39 gpio-controller;
40 #interrupt-cells = <2>;
41 interrupt-controller;
42 };
43
44 gpio2: gpio@4801a000 {
45 compatible = "ti,omap2-gpio";
46 reg = <0x4801a000 0x200>;
47 interrupts = <30>;
48 ti,hwmods = "gpio2";
49 ti,gpio-always-on;
50 #gpio-cells = <2>;
51 gpio-controller;
52 #interrupt-cells = <2>;
53 interrupt-controller;
54 };
55
56 gpio3: gpio@4801c000 {
57 compatible = "ti,omap2-gpio";
58 reg = <0x4801c000 0x200>;
59 interrupts = <31>;
60 ti,hwmods = "gpio3";
61 ti,gpio-always-on;
62 #gpio-cells = <2>;
63 gpio-controller;
64 #interrupt-cells = <2>;
65 interrupt-controller;
66 };
67
68 gpio4: gpio@4801e000 {
69 compatible = "ti,omap2-gpio";
70 reg = <0x4801e000 0x200>;
71 interrupts = <32>;
72 ti,hwmods = "gpio4";
73 ti,gpio-always-on;
74 #gpio-cells = <2>;
75 gpio-controller;
76 #interrupt-cells = <2>;
77 interrupt-controller;
78 };
79
80 gpmc: gpmc@6800a000 {
81 compatible = "ti,omap2420-gpmc";
82 reg = <0x6800a000 0x1000>;
83 #address-cells = <2>;
84 #size-cells = <1>;
85 interrupts = <20>;
86 gpmc,num-cs = <8>;
87 gpmc,num-waitpins = <4>;
88 ti,hwmods = "gpmc";
89 };
90
32 mcbsp1: mcbsp@48074000 { 91 mcbsp1: mcbsp@48074000 {
33 compatible = "ti,omap2420-mcbsp"; 92 compatible = "ti,omap2420-mcbsp";
34 reg = <0x48074000 0xff>; 93 reg = <0x48074000 0xff>;
@@ -37,6 +96,9 @@
37 <60>; /* RX interrupt */ 96 <60>; /* RX interrupt */
38 interrupt-names = "tx", "rx"; 97 interrupt-names = "tx", "rx";
39 ti,hwmods = "mcbsp1"; 98 ti,hwmods = "mcbsp1";
99 dmas = <&sdma 31>,
100 <&sdma 32>;
101 dma-names = "tx", "rx";
40 }; 102 };
41 103
42 mcbsp2: mcbsp@48076000 { 104 mcbsp2: mcbsp@48076000 {
@@ -47,10 +109,13 @@
47 <63>; /* RX interrupt */ 109 <63>; /* RX interrupt */
48 interrupt-names = "tx", "rx"; 110 interrupt-names = "tx", "rx";
49 ti,hwmods = "mcbsp2"; 111 ti,hwmods = "mcbsp2";
112 dmas = <&sdma 33>,
113 <&sdma 34>;
114 dma-names = "tx", "rx";
50 }; 115 };
51 116
52 timer1: timer@48028000 { 117 timer1: timer@48028000 {
53 compatible = "ti,omap2-timer"; 118 compatible = "ti,omap2420-timer";
54 reg = <0x48028000 0x400>; 119 reg = <0x48028000 0x400>;
55 interrupts = <37>; 120 interrupts = <37>;
56 ti,hwmods = "timer1"; 121 ti,hwmods = "timer1";
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index c3924457c9b6..054bc4439568 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -29,6 +29,76 @@
29 pinctrl-single,function-mask = <0x3f>; 29 pinctrl-single,function-mask = <0x3f>;
30 }; 30 };
31 31
32 gpio1: gpio@4900c000 {
33 compatible = "ti,omap2-gpio";
34 reg = <0x4900c000 0x200>;
35 interrupts = <29>;
36 ti,hwmods = "gpio1";
37 ti,gpio-always-on;
38 #gpio-cells = <2>;
39 gpio-controller;
40 #interrupt-cells = <2>;
41 interrupt-controller;
42 };
43
44 gpio2: gpio@4900e000 {
45 compatible = "ti,omap2-gpio";
46 reg = <0x4900e000 0x200>;
47 interrupts = <30>;
48 ti,hwmods = "gpio2";
49 ti,gpio-always-on;
50 #gpio-cells = <2>;
51 gpio-controller;
52 #interrupt-cells = <2>;
53 interrupt-controller;
54 };
55
56 gpio3: gpio@49010000 {
57 compatible = "ti,omap2-gpio";
58 reg = <0x49010000 0x200>;
59 interrupts = <31>;
60 ti,hwmods = "gpio3";
61 ti,gpio-always-on;
62 #gpio-cells = <2>;
63 gpio-controller;
64 #interrupt-cells = <2>;
65 interrupt-controller;
66 };
67
68 gpio4: gpio@49012000 {
69 compatible = "ti,omap2-gpio";
70 reg = <0x49012000 0x200>;
71 interrupts = <32>;
72 ti,hwmods = "gpio4";
73 ti,gpio-always-on;
74 #gpio-cells = <2>;
75 gpio-controller;
76 #interrupt-cells = <2>;
77 interrupt-controller;
78 };
79
80 gpio5: gpio@480b6000 {
81 compatible = "ti,omap2-gpio";
82 reg = <0x480b6000 0x200>;
83 interrupts = <33>;
84 ti,hwmods = "gpio5";
85 #gpio-cells = <2>;
86 gpio-controller;
87 #interrupt-cells = <2>;
88 interrupt-controller;
89 };
90
91 gpmc: gpmc@6e000000 {
92 compatible = "ti,omap2430-gpmc";
93 reg = <0x6e000000 0x1000>;
94 #address-cells = <2>;
95 #size-cells = <1>;
96 interrupts = <20>;
97 gpmc,num-cs = <8>;
98 gpmc,num-waitpins = <4>;
99 ti,hwmods = "gpmc";
100 };
101
32 mcbsp1: mcbsp@48074000 { 102 mcbsp1: mcbsp@48074000 {
33 compatible = "ti,omap2430-mcbsp"; 103 compatible = "ti,omap2430-mcbsp";
34 reg = <0x48074000 0xff>; 104 reg = <0x48074000 0xff>;
@@ -40,6 +110,9 @@
40 interrupt-names = "common", "tx", "rx", "rx_overflow"; 110 interrupt-names = "common", "tx", "rx", "rx_overflow";
41 ti,buffer-size = <128>; 111 ti,buffer-size = <128>;
42 ti,hwmods = "mcbsp1"; 112 ti,hwmods = "mcbsp1";
113 dmas = <&sdma 31>,
114 <&sdma 32>;
115 dma-names = "tx", "rx";
43 }; 116 };
44 117
45 mcbsp2: mcbsp@48076000 { 118 mcbsp2: mcbsp@48076000 {
@@ -52,6 +125,9 @@
52 interrupt-names = "common", "tx", "rx"; 125 interrupt-names = "common", "tx", "rx";
53 ti,buffer-size = <128>; 126 ti,buffer-size = <128>;
54 ti,hwmods = "mcbsp2"; 127 ti,hwmods = "mcbsp2";
128 dmas = <&sdma 33>,
129 <&sdma 34>;
130 dma-names = "tx", "rx";
55 }; 131 };
56 132
57 mcbsp3: mcbsp@4808c000 { 133 mcbsp3: mcbsp@4808c000 {
@@ -64,6 +140,9 @@
64 interrupt-names = "common", "tx", "rx"; 140 interrupt-names = "common", "tx", "rx";
65 ti,buffer-size = <128>; 141 ti,buffer-size = <128>;
66 ti,hwmods = "mcbsp3"; 142 ti,hwmods = "mcbsp3";
143 dmas = <&sdma 17>,
144 <&sdma 18>;
145 dma-names = "tx", "rx";
67 }; 146 };
68 147
69 mcbsp4: mcbsp@4808e000 { 148 mcbsp4: mcbsp@4808e000 {
@@ -76,6 +155,9 @@
76 interrupt-names = "common", "tx", "rx"; 155 interrupt-names = "common", "tx", "rx";
77 ti,buffer-size = <128>; 156 ti,buffer-size = <128>;
78 ti,hwmods = "mcbsp4"; 157 ti,hwmods = "mcbsp4";
158 dmas = <&sdma 19>,
159 <&sdma 20>;
160 dma-names = "tx", "rx";
79 }; 161 };
80 162
81 mcbsp5: mcbsp@48096000 { 163 mcbsp5: mcbsp@48096000 {
@@ -88,10 +170,13 @@
88 interrupt-names = "common", "tx", "rx"; 170 interrupt-names = "common", "tx", "rx";
89 ti,buffer-size = <128>; 171 ti,buffer-size = <128>;
90 ti,hwmods = "mcbsp5"; 172 ti,hwmods = "mcbsp5";
173 dmas = <&sdma 21>,
174 <&sdma 22>;
175 dma-names = "tx", "rx";
91 }; 176 };
92 177
93 timer1: timer@49018000 { 178 timer1: timer@49018000 {
94 compatible = "ti,omap2-timer"; 179 compatible = "ti,omap2420-timer";
95 reg = <0x49018000 0x400>; 180 reg = <0x49018000 0x400>;
96 interrupts = <37>; 181 interrupts = <37>;
97 ti,hwmods = "timer1"; 182 ti,hwmods = "timer1";
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3705a81c1fc2..5a31964ae339 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -13,6 +13,12 @@
13 model = "TI OMAP3 BeagleBoard xM"; 13 model = "TI OMAP3 BeagleBoard xM";
14 compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3"; 14 compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
15 15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vcc>;
19 };
20 };
21
16 memory { 22 memory {
17 device_type = "memory"; 23 device_type = "memory";
18 reg = <0x80000000 0x20000000>; /* 512 MB */ 24 reg = <0x80000000 0x20000000>; /* 512 MB */
@@ -20,10 +26,6 @@
20 26
21 leds { 27 leds {
22 compatible = "gpio-leds"; 28 compatible = "gpio-leds";
23 pmu_stat {
24 label = "beagleboard::pmu_stat";
25 gpios = <&twl_gpio 19 0>; /* LEDB */
26 };
27 29
28 heartbeat { 30 heartbeat {
29 label = "beagleboard::usr0"; 31 label = "beagleboard::usr0";
@@ -38,6 +40,16 @@
38 }; 40 };
39 }; 41 };
40 42
43 pwmleds {
44 compatible = "pwm-leds";
45
46 pmu_stat {
47 label = "beagleboard::pmu_stat";
48 pwms = <&twl_pwmled 1 7812500>;
49 max-brightness = <127>;
50 };
51 };
52
41 sound { 53 sound {
42 compatible = "ti,omap-twl4030"; 54 compatible = "ti,omap-twl4030";
43 ti,model = "omap3beagle"; 55 ti,model = "omap3beagle";
@@ -107,3 +119,9 @@
107 */ 119 */
108 ti,pulldowns = <0x03a1c4>; 120 ti,pulldowns = <0x03a1c4>;
109}; 121};
122
123&usb_otg_hs {
124 interface-type = <0>;
125 mode = <3>;
126 power = <50>;
127};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 02d23f15fd86..6eec69997607 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -7,12 +7,18 @@
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap3.dtsi" 10/include/ "omap34xx.dtsi"
11 11
12/ { 12/ {
13 model = "TI OMAP3 BeagleBoard"; 13 model = "TI OMAP3 BeagleBoard";
14 compatible = "ti,omap3-beagle", "ti,omap3"; 14 compatible = "ti,omap3-beagle", "ti,omap3";
15 15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vcc>;
19 };
20 };
21
16 memory { 22 memory {
17 device_type = "memory"; 23 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */ 24 reg = <0x80000000 0x10000000>; /* 256 MB */
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
new file mode 100644
index 000000000000..8a5cdcc6debd
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -0,0 +1,169 @@
1/*
2 * Author: Anil Kumar <anilk4.v@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap34xx.dtsi"
11/ {
12 model = "TimLL OMAP3 Devkit8000";
13 compatible = "timll,omap3-devkit8000", "ti,omap3";
14
15 memory {
16 device_type = "memory";
17 reg = <0x80000000 0x10000000>; /* 256 MB */
18 };
19
20 leds {
21 compatible = "gpio-leds";
22
23 heartbeat {
24 label = "devkit8000::led1";
25 gpios = <&gpio6 26 0>; /* 186 -> LED1 */
26 default-state = "on";
27 linux,default-trigger = "heartbeat";
28 };
29
30 mmc {
31 label = "devkit8000::led2";
32 gpios = <&gpio6 3 0>; /* 163 -> LED2 */
33 default-state = "on";
34 linux,default-trigger = "none";
35 };
36
37 usr {
38 label = "devkit8000::led3";
39 gpios = <&gpio6 4 0>; /* 164 -> LED3 */
40 default-state = "on";
41 linux,default-trigger = "usr";
42 };
43
44 };
45
46 sound {
47 compatible = "ti,omap-twl4030";
48 ti,model = "devkit8000";
49
50 ti,mcbsp = <&mcbsp2>;
51 ti,codec = <&twl_audio>;
52 ti,audio-routing =
53 "Ext Spk", "PREDRIVEL",
54 "Ext Spk", "PREDRIVER",
55 "MAINMIC", "Main Mic",
56 "Main Mic", "Mic Bias 1";
57 };
58};
59
60&i2c1 {
61 clock-frequency = <2600000>;
62
63 twl: twl@48 {
64 reg = <0x48>;
65 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
66
67 twl_audio: audio {
68 compatible = "ti,twl4030-audio";
69 codec {
70 };
71 };
72 };
73};
74
75&i2c2 {
76 status = "disabled";
77};
78
79&i2c3 {
80 status = "disabled";
81};
82
83/include/ "twl4030.dtsi"
84
85&mmc1 {
86 vmmc-supply = <&vmmc1>;
87 vmmc_aux-supply = <&vsim>;
88 bus-width = <8>;
89};
90
91&mmc2 {
92 status = "disabled";
93};
94
95&mmc3 {
96 status = "disabled";
97};
98
99&wdt2 {
100 status = "disabled";
101};
102
103&mcbsp1 {
104 status = "disabled";
105};
106
107&mcbsp3 {
108 status = "disabled";
109};
110
111&mcbsp4 {
112 status = "disabled";
113};
114
115&mcbsp5 {
116 status = "disabled";
117};
118
119&gpmc {
120 ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */
121
122 nand@0,0 {
123 reg = <0 0 0>; /* CS0, offset 0 */
124 nand-bus-width = <16>;
125
126 gpmc,sync-clk = <0>;
127 gpmc,cs-on = <0>;
128 gpmc,cs-rd-off = <44>;
129 gpmc,cs-wr-off = <44>;
130 gpmc,adv-on = <6>;
131 gpmc,adv-rd-off = <34>;
132 gpmc,adv-wr-off = <44>;
133 gpmc,we-off = <40>;
134 gpmc,oe-off = <54>;
135 gpmc,access = <64>;
136 gpmc,rd-cycle = <82>;
137 gpmc,wr-cycle = <82>;
138 gpmc,wr-access = <40>;
139 gpmc,wr-data-mux-bus = <0>;
140
141 #address-cells = <1>;
142 #size-cells = <1>;
143
144 x-loader@0 {
145 label = "X-Loader";
146 reg = <0 0x80000>;
147 };
148
149 bootloaders@80000 {
150 label = "U-Boot";
151 reg = <0x80000 0x1e0000>;
152 };
153
154 bootloaders_env@260000 {
155 label = "U-Boot Env";
156 reg = <0x260000 0x20000>;
157 };
158
159 kernel@280000 {
160 label = "Kernel";
161 reg = <0x280000 0x400000>;
162 };
163
164 filesystem@680000 {
165 label = "File System";
166 reg = <0x680000 0xf980000>;
167 };
168 };
169};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index e8ba1c247a39..05f51e10ddd6 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -7,12 +7,18 @@
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap3.dtsi" 10/include/ "omap34xx.dtsi"
11 11
12/ { 12/ {
13 model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; 13 model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
14 compatible = "ti,omap3-evm", "ti,omap3"; 14 compatible = "ti,omap3-evm", "ti,omap3";
15 15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vcc>;
19 };
20 };
21
16 memory { 22 memory {
17 device_type = "memory"; 23 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */ 24 reg = <0x80000000 0x10000000>; /* 256 MB */
@@ -59,3 +65,9 @@
59&twl_gpio { 65&twl_gpio {
60 ti,use-leds; 66 ti,use-leds;
61}; 67};
68
69&usb_otg_hs {
70 interface-type = <0>;
71 mode = <3>;
72 power = <50>;
73};
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
new file mode 100644
index 000000000000..f8fe3b748c3e
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -0,0 +1,122 @@
1/*
2 * Device Tree Source for IGEP Technology devices
3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11/dts-v1/;
12
13/include/ "omap34xx.dtsi"
14
15/ {
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x20000000>; /* 512 MB */
19 };
20
21 sound {
22 compatible = "ti,omap-twl4030";
23 ti,model = "igep2";
24 ti,mcbsp = <&mcbsp2>;
25 ti,codec = <&twl_audio>;
26 };
27};
28
29&omap3_pmx_core {
30 uart1_pins: pinmux_uart1_pins {
31 pinctrl-single,pins = <
32 0x152 0x100 /* uart1_rx.uart1_rx INPUT | MODE0 */
33 0x14c 0 /* uart1_tx.uart1_tx OUTPUT | MODE0 */
34 >;
35 };
36
37 uart2_pins: pinmux_uart2_pins {
38 pinctrl-single,pins = <
39 0x14a 0x100 /* uart2_rx.uart2_rx INPUT | MODE0 */
40 0x148 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */
41 >;
42 };
43
44 uart3_pins: pinmux_uart3_pins {
45 pinctrl-single,pins = <
46 0x16e 0x100 /* uart3_rx.uart3_rx INPUT | MODE0 */
47 0x170 0 /* uart3_tx.uart3_tx OUTPUT | MODE0 */
48 >;
49 };
50
51 mmc1_pins: pinmux_mmc1_pins {
52 pinctrl-single,pins = <
53 0x114 0x0118 /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */
54 0x116 0x0118 /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */
55 0x118 0x0118 /* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */
56 0x11a 0x0118 /* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */
57 0x11c 0x0118 /* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */
58 0x11e 0x0118 /* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */
59 0x120 0x0100 /* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */
60 0x122 0x0100 /* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */
61 0x124 0x0100 /* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */
62 0x126 0x0100 /* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */
63 >;
64 };
65};
66
67&i2c1 {
68 clock-frequency = <2600000>;
69
70 twl: twl@48 {
71 reg = <0x48>;
72 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
73 interrupt-parent = <&intc>;
74
75 twl_audio: audio {
76 compatible = "ti,twl4030-audio";
77 codec {
78 };
79 };
80 };
81};
82
83/include/ "twl4030.dtsi"
84
85&i2c2 {
86 clock-frequency = <400000>;
87};
88
89&mmc1 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&mmc1_pins>;
92 vmmc-supply = <&vmmc1>;
93 vmmc_aux-supply = <&vsim>;
94 bus-width = <8>;
95};
96
97&mmc2 {
98 status = "disabled";
99};
100
101&mmc3 {
102 status = "disabled";
103};
104
105&uart1 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&uart1_pins>;
108};
109
110&uart2 {
111 pinctrl-names = "default";
112 pinctrl-0 = <&uart2_pins>;
113};
114
115&uart3 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&uart3_pins>;
118};
119
120&twl_gpio {
121 ti,use-leds;
122};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
new file mode 100644
index 000000000000..e2b98490cc9a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -0,0 +1,56 @@
1/*
2 * Device Tree Source for IGEPv2 board
3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12/include/ "omap3-igep.dtsi"
13
14/ {
15 model = "IGEPv2";
16 compatible = "isee,omap3-igep0020", "ti,omap3";
17
18 leds {
19 compatible = "gpio-leds";
20 boot {
21 label = "omap3:green:boot";
22 gpios = <&gpio1 26 0>;
23 default-state = "on";
24 };
25
26 user0 {
27 label = "omap3:red:user0";
28 gpios = <&gpio1 27 0>;
29 default-state = "off";
30 };
31
32 user1 {
33 label = "omap3:red:user1";
34 gpios = <&gpio1 28 0>;
35 default-state = "off";
36 };
37
38 user2 {
39 label = "omap3:green:user1";
40 gpios = <&twl_gpio 19 1>;
41 };
42 };
43};
44
45&i2c3 {
46 clock-frequency = <100000>;
47
48 /*
49 * Display monitor features are burnt in the EEPROM
50 * as EDID data.
51 */
52 eeprom@50 {
53 compatible = "ti,eeprom";
54 reg = <0x50>;
55 };
56};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
new file mode 100644
index 000000000000..9dc48d262ffb
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -0,0 +1,44 @@
1/*
2 * Device Tree Source for IGEP COM Module
3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12/include/ "omap3-igep.dtsi"
13
14/ {
15 model = "IGEP COM Module";
16 compatible = "isee,omap3-igep0030", "ti,omap3";
17
18 leds {
19 compatible = "gpio-leds";
20 boot {
21 label = "omap3:green:boot";
22 gpios = <&twl_gpio 13 1>;
23 default-state = "on";
24 };
25
26 user0 {
27 label = "omap3:red:user0";
28 gpios = <&twl_gpio 18 1>; /* LEDA */
29 default-state = "off";
30 };
31
32 user1 {
33 label = "omap3:green:user1";
34 gpios = <&twl_gpio 19 1>; /* LEDB */
35 default-state = "off";
36 };
37
38 user2 {
39 label = "omap3:red:user1";
40 gpios = <&gpio1 16 1>;
41 default-state = "off";
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index 89808ce01673..d4a7280d18b7 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -11,17 +11,26 @@
11 */ 11 */
12/dts-v1/; 12/dts-v1/;
13 13
14/include/ "omap3.dtsi" 14/include/ "omap34xx.dtsi"
15 15
16/ { 16/ {
17 leds { 17 pwmleds {
18 compatible = "gpio-leds"; 18 compatible = "pwm-leds";
19
19 overo { 20 overo {
20 label = "overo:blue:COM"; 21 label = "overo:blue:COM";
21 gpios = <&twl_gpio 19 0>; 22 pwms = <&twl_pwmled 1 7812500>;
22 linux,default-trigger = "mmc0"; 23 max-brightness = <127>;
23 }; 24 };
24 }; 25 };
26
27 sound {
28 compatible = "ti,omap-twl4030";
29 ti,model = "overo";
30
31 ti,mcbsp = <&mcbsp2>;
32 ti,codec = <&twl_audio>;
33 };
25}; 34};
26 35
27&i2c1 { 36&i2c1 {
@@ -31,6 +40,12 @@
31 reg = <0x48>; 40 reg = <0x48>;
32 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 41 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
33 interrupt-parent = <&intc>; 42 interrupt-parent = <&intc>;
43
44 twl_audio: audio {
45 compatible = "ti,twl4030-audio";
46 codec {
47 };
48 };
34 }; 49 };
35}; 50};
36 51
@@ -55,3 +70,9 @@
55&twl_gpio { 70&twl_gpio {
56 ti,use-leds; 71 ti,use-leds;
57}; 72};
73
74&usb_otg_hs {
75 interface-type = <0>;
76 mode = <3>;
77 power = <50>;
78};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index a14f74bbce7c..4ad03d9dbf0c 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -26,8 +26,14 @@
26 }; 26 };
27 }; 27 };
28 28
29 pmu {
30 compatible = "arm,cortex-a8-pmu";
31 interrupts = <3>;
32 ti,hwmods = "debugss";
33 };
34
29 /* 35 /*
30 * The soc node represents the soc top level view. It is uses for IPs 36 * The soc node represents the soc top level view. It is used for IPs
31 * that are not memory mapped in the MPU view or for the MPU itself. 37 * that are not memory mapped in the MPU view or for the MPU itself.
32 */ 38 */
33 soc { 39 soc {
@@ -75,76 +81,101 @@
75 reg = <0x48200000 0x1000>; 81 reg = <0x48200000 0x1000>;
76 }; 82 };
77 83
84 sdma: dma-controller@48056000 {
85 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
86 reg = <0x48056000 0x1000>;
87 interrupts = <12>,
88 <13>,
89 <14>,
90 <15>;
91 #dma-cells = <1>;
92 #dma-channels = <32>;
93 #dma-requests = <96>;
94 };
95
78 omap3_pmx_core: pinmux@48002030 { 96 omap3_pmx_core: pinmux@48002030 {
79 compatible = "ti,omap3-padconf", "pinctrl-single"; 97 compatible = "ti,omap3-padconf", "pinctrl-single";
80 reg = <0x48002030 0x05cc>; 98 reg = <0x48002030 0x05cc>;
81 #address-cells = <1>; 99 #address-cells = <1>;
82 #size-cells = <0>; 100 #size-cells = <0>;
83 pinctrl-single,register-width = <16>; 101 pinctrl-single,register-width = <16>;
84 pinctrl-single,function-mask = <0x7fff>; 102 pinctrl-single,function-mask = <0x7f1f>;
85 }; 103 };
86 104
87 omap3_pmx_wkup: pinmux@0x48002a58 { 105 omap3_pmx_wkup: pinmux@0x48002a00 {
88 compatible = "ti,omap3-padconf", "pinctrl-single"; 106 compatible = "ti,omap3-padconf", "pinctrl-single";
89 reg = <0x48002a58 0x5c>; 107 reg = <0x48002a00 0x5c>;
90 #address-cells = <1>; 108 #address-cells = <1>;
91 #size-cells = <0>; 109 #size-cells = <0>;
92 pinctrl-single,register-width = <16>; 110 pinctrl-single,register-width = <16>;
93 pinctrl-single,function-mask = <0x7fff>; 111 pinctrl-single,function-mask = <0x7f1f>;
94 }; 112 };
95 113
96 gpio1: gpio@48310000 { 114 gpio1: gpio@48310000 {
97 compatible = "ti,omap3-gpio"; 115 compatible = "ti,omap3-gpio";
116 reg = <0x48310000 0x200>;
117 interrupts = <29>;
98 ti,hwmods = "gpio1"; 118 ti,hwmods = "gpio1";
119 ti,gpio-always-on;
99 gpio-controller; 120 gpio-controller;
100 #gpio-cells = <2>; 121 #gpio-cells = <2>;
101 interrupt-controller; 122 interrupt-controller;
102 #interrupt-cells = <1>; 123 #interrupt-cells = <2>;
103 }; 124 };
104 125
105 gpio2: gpio@49050000 { 126 gpio2: gpio@49050000 {
106 compatible = "ti,omap3-gpio"; 127 compatible = "ti,omap3-gpio";
128 reg = <0x49050000 0x200>;
129 interrupts = <30>;
107 ti,hwmods = "gpio2"; 130 ti,hwmods = "gpio2";
108 gpio-controller; 131 gpio-controller;
109 #gpio-cells = <2>; 132 #gpio-cells = <2>;
110 interrupt-controller; 133 interrupt-controller;
111 #interrupt-cells = <1>; 134 #interrupt-cells = <2>;
112 }; 135 };
113 136
114 gpio3: gpio@49052000 { 137 gpio3: gpio@49052000 {
115 compatible = "ti,omap3-gpio"; 138 compatible = "ti,omap3-gpio";
139 reg = <0x49052000 0x200>;
140 interrupts = <31>;
116 ti,hwmods = "gpio3"; 141 ti,hwmods = "gpio3";
117 gpio-controller; 142 gpio-controller;
118 #gpio-cells = <2>; 143 #gpio-cells = <2>;
119 interrupt-controller; 144 interrupt-controller;
120 #interrupt-cells = <1>; 145 #interrupt-cells = <2>;
121 }; 146 };
122 147
123 gpio4: gpio@49054000 { 148 gpio4: gpio@49054000 {
124 compatible = "ti,omap3-gpio"; 149 compatible = "ti,omap3-gpio";
150 reg = <0x49054000 0x200>;
151 interrupts = <32>;
125 ti,hwmods = "gpio4"; 152 ti,hwmods = "gpio4";
126 gpio-controller; 153 gpio-controller;
127 #gpio-cells = <2>; 154 #gpio-cells = <2>;
128 interrupt-controller; 155 interrupt-controller;
129 #interrupt-cells = <1>; 156 #interrupt-cells = <2>;
130 }; 157 };
131 158
132 gpio5: gpio@49056000 { 159 gpio5: gpio@49056000 {
133 compatible = "ti,omap3-gpio"; 160 compatible = "ti,omap3-gpio";
161 reg = <0x49056000 0x200>;
162 interrupts = <33>;
134 ti,hwmods = "gpio5"; 163 ti,hwmods = "gpio5";
135 gpio-controller; 164 gpio-controller;
136 #gpio-cells = <2>; 165 #gpio-cells = <2>;
137 interrupt-controller; 166 interrupt-controller;
138 #interrupt-cells = <1>; 167 #interrupt-cells = <2>;
139 }; 168 };
140 169
141 gpio6: gpio@49058000 { 170 gpio6: gpio@49058000 {
142 compatible = "ti,omap3-gpio"; 171 compatible = "ti,omap3-gpio";
172 reg = <0x49058000 0x200>;
173 interrupts = <34>;
143 ti,hwmods = "gpio6"; 174 ti,hwmods = "gpio6";
144 gpio-controller; 175 gpio-controller;
145 #gpio-cells = <2>; 176 #gpio-cells = <2>;
146 interrupt-controller; 177 interrupt-controller;
147 #interrupt-cells = <1>; 178 #interrupt-cells = <2>;
148 }; 179 };
149 180
150 uart1: serial@4806a000 { 181 uart1: serial@4806a000 {
@@ -192,6 +223,16 @@
192 #size-cells = <0>; 223 #size-cells = <0>;
193 ti,hwmods = "mcspi1"; 224 ti,hwmods = "mcspi1";
194 ti,spi-num-cs = <4>; 225 ti,spi-num-cs = <4>;
226 dmas = <&sdma 35>,
227 <&sdma 36>,
228 <&sdma 37>,
229 <&sdma 38>,
230 <&sdma 39>,
231 <&sdma 40>,
232 <&sdma 41>,
233 <&sdma 42>;
234 dma-names = "tx0", "rx0", "tx1", "rx1",
235 "tx2", "rx2", "tx3", "rx3";
195 }; 236 };
196 237
197 mcspi2: spi@4809a000 { 238 mcspi2: spi@4809a000 {
@@ -200,6 +241,11 @@
200 #size-cells = <0>; 241 #size-cells = <0>;
201 ti,hwmods = "mcspi2"; 242 ti,hwmods = "mcspi2";
202 ti,spi-num-cs = <2>; 243 ti,spi-num-cs = <2>;
244 dmas = <&sdma 43>,
245 <&sdma 44>,
246 <&sdma 45>,
247 <&sdma 46>;
248 dma-names = "tx0", "rx0", "tx1", "rx1";
203 }; 249 };
204 250
205 mcspi3: spi@480b8000 { 251 mcspi3: spi@480b8000 {
@@ -208,6 +254,11 @@
208 #size-cells = <0>; 254 #size-cells = <0>;
209 ti,hwmods = "mcspi3"; 255 ti,hwmods = "mcspi3";
210 ti,spi-num-cs = <2>; 256 ti,spi-num-cs = <2>;
257 dmas = <&sdma 15>,
258 <&sdma 16>,
259 <&sdma 23>,
260 <&sdma 24>;
261 dma-names = "tx0", "rx0", "tx1", "rx1";
211 }; 262 };
212 263
213 mcspi4: spi@480ba000 { 264 mcspi4: spi@480ba000 {
@@ -216,22 +267,30 @@
216 #size-cells = <0>; 267 #size-cells = <0>;
217 ti,hwmods = "mcspi4"; 268 ti,hwmods = "mcspi4";
218 ti,spi-num-cs = <1>; 269 ti,spi-num-cs = <1>;
270 dmas = <&sdma 70>, <&sdma 71>;
271 dma-names = "tx0", "rx0";
219 }; 272 };
220 273
221 mmc1: mmc@4809c000 { 274 mmc1: mmc@4809c000 {
222 compatible = "ti,omap3-hsmmc"; 275 compatible = "ti,omap3-hsmmc";
223 ti,hwmods = "mmc1"; 276 ti,hwmods = "mmc1";
224 ti,dual-volt; 277 ti,dual-volt;
278 dmas = <&sdma 61>, <&sdma 62>;
279 dma-names = "tx", "rx";
225 }; 280 };
226 281
227 mmc2: mmc@480b4000 { 282 mmc2: mmc@480b4000 {
228 compatible = "ti,omap3-hsmmc"; 283 compatible = "ti,omap3-hsmmc";
229 ti,hwmods = "mmc2"; 284 ti,hwmods = "mmc2";
285 dmas = <&sdma 47>, <&sdma 48>;
286 dma-names = "tx", "rx";
230 }; 287 };
231 288
232 mmc3: mmc@480ad000 { 289 mmc3: mmc@480ad000 {
233 compatible = "ti,omap3-hsmmc"; 290 compatible = "ti,omap3-hsmmc";
234 ti,hwmods = "mmc3"; 291 ti,hwmods = "mmc3";
292 dmas = <&sdma 77>, <&sdma 78>;
293 dma-names = "tx", "rx";
235 }; 294 };
236 295
237 wdt2: wdt@48314000 { 296 wdt2: wdt@48314000 {
@@ -249,6 +308,9 @@
249 interrupt-names = "common", "tx", "rx"; 308 interrupt-names = "common", "tx", "rx";
250 ti,buffer-size = <128>; 309 ti,buffer-size = <128>;
251 ti,hwmods = "mcbsp1"; 310 ti,hwmods = "mcbsp1";
311 dmas = <&sdma 31>,
312 <&sdma 32>;
313 dma-names = "tx", "rx";
252 }; 314 };
253 315
254 mcbsp2: mcbsp@49022000 { 316 mcbsp2: mcbsp@49022000 {
@@ -263,6 +325,9 @@
263 interrupt-names = "common", "tx", "rx", "sidetone"; 325 interrupt-names = "common", "tx", "rx", "sidetone";
264 ti,buffer-size = <1280>; 326 ti,buffer-size = <1280>;
265 ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; 327 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
328 dmas = <&sdma 33>,
329 <&sdma 34>;
330 dma-names = "tx", "rx";
266 }; 331 };
267 332
268 mcbsp3: mcbsp@49024000 { 333 mcbsp3: mcbsp@49024000 {
@@ -277,6 +342,9 @@
277 interrupt-names = "common", "tx", "rx", "sidetone"; 342 interrupt-names = "common", "tx", "rx", "sidetone";
278 ti,buffer-size = <128>; 343 ti,buffer-size = <128>;
279 ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; 344 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
345 dmas = <&sdma 17>,
346 <&sdma 18>;
347 dma-names = "tx", "rx";
280 }; 348 };
281 349
282 mcbsp4: mcbsp@49026000 { 350 mcbsp4: mcbsp@49026000 {
@@ -289,6 +357,9 @@
289 interrupt-names = "common", "tx", "rx"; 357 interrupt-names = "common", "tx", "rx";
290 ti,buffer-size = <128>; 358 ti,buffer-size = <128>;
291 ti,hwmods = "mcbsp4"; 359 ti,hwmods = "mcbsp4";
360 dmas = <&sdma 19>,
361 <&sdma 20>;
362 dma-names = "tx", "rx";
292 }; 363 };
293 364
294 mcbsp5: mcbsp@48096000 { 365 mcbsp5: mcbsp@48096000 {
@@ -301,10 +372,13 @@
301 interrupt-names = "common", "tx", "rx"; 372 interrupt-names = "common", "tx", "rx";
302 ti,buffer-size = <128>; 373 ti,buffer-size = <128>;
303 ti,hwmods = "mcbsp5"; 374 ti,hwmods = "mcbsp5";
375 dmas = <&sdma 21>,
376 <&sdma 22>;
377 dma-names = "tx", "rx";
304 }; 378 };
305 379
306 timer1: timer@48318000 { 380 timer1: timer@48318000 {
307 compatible = "ti,omap2-timer"; 381 compatible = "ti,omap3430-timer";
308 reg = <0x48318000 0x400>; 382 reg = <0x48318000 0x400>;
309 interrupts = <37>; 383 interrupts = <37>;
310 ti,hwmods = "timer1"; 384 ti,hwmods = "timer1";
@@ -312,28 +386,28 @@
312 }; 386 };
313 387
314 timer2: timer@49032000 { 388 timer2: timer@49032000 {
315 compatible = "ti,omap2-timer"; 389 compatible = "ti,omap3430-timer";
316 reg = <0x49032000 0x400>; 390 reg = <0x49032000 0x400>;
317 interrupts = <38>; 391 interrupts = <38>;
318 ti,hwmods = "timer2"; 392 ti,hwmods = "timer2";
319 }; 393 };
320 394
321 timer3: timer@49034000 { 395 timer3: timer@49034000 {
322 compatible = "ti,omap2-timer"; 396 compatible = "ti,omap3430-timer";
323 reg = <0x49034000 0x400>; 397 reg = <0x49034000 0x400>;
324 interrupts = <39>; 398 interrupts = <39>;
325 ti,hwmods = "timer3"; 399 ti,hwmods = "timer3";
326 }; 400 };
327 401
328 timer4: timer@49036000 { 402 timer4: timer@49036000 {
329 compatible = "ti,omap2-timer"; 403 compatible = "ti,omap3430-timer";
330 reg = <0x49036000 0x400>; 404 reg = <0x49036000 0x400>;
331 interrupts = <40>; 405 interrupts = <40>;
332 ti,hwmods = "timer4"; 406 ti,hwmods = "timer4";
333 }; 407 };
334 408
335 timer5: timer@49038000 { 409 timer5: timer@49038000 {
336 compatible = "ti,omap2-timer"; 410 compatible = "ti,omap3430-timer";
337 reg = <0x49038000 0x400>; 411 reg = <0x49038000 0x400>;
338 interrupts = <41>; 412 interrupts = <41>;
339 ti,hwmods = "timer5"; 413 ti,hwmods = "timer5";
@@ -341,7 +415,7 @@
341 }; 415 };
342 416
343 timer6: timer@4903a000 { 417 timer6: timer@4903a000 {
344 compatible = "ti,omap2-timer"; 418 compatible = "ti,omap3430-timer";
345 reg = <0x4903a000 0x400>; 419 reg = <0x4903a000 0x400>;
346 interrupts = <42>; 420 interrupts = <42>;
347 ti,hwmods = "timer6"; 421 ti,hwmods = "timer6";
@@ -349,7 +423,7 @@
349 }; 423 };
350 424
351 timer7: timer@4903c000 { 425 timer7: timer@4903c000 {
352 compatible = "ti,omap2-timer"; 426 compatible = "ti,omap3430-timer";
353 reg = <0x4903c000 0x400>; 427 reg = <0x4903c000 0x400>;
354 interrupts = <43>; 428 interrupts = <43>;
355 ti,hwmods = "timer7"; 429 ti,hwmods = "timer7";
@@ -357,7 +431,7 @@
357 }; 431 };
358 432
359 timer8: timer@4903e000 { 433 timer8: timer@4903e000 {
360 compatible = "ti,omap2-timer"; 434 compatible = "ti,omap3430-timer";
361 reg = <0x4903e000 0x400>; 435 reg = <0x4903e000 0x400>;
362 interrupts = <44>; 436 interrupts = <44>;
363 ti,hwmods = "timer8"; 437 ti,hwmods = "timer8";
@@ -366,7 +440,7 @@
366 }; 440 };
367 441
368 timer9: timer@49040000 { 442 timer9: timer@49040000 {
369 compatible = "ti,omap2-timer"; 443 compatible = "ti,omap3430-timer";
370 reg = <0x49040000 0x400>; 444 reg = <0x49040000 0x400>;
371 interrupts = <45>; 445 interrupts = <45>;
372 ti,hwmods = "timer9"; 446 ti,hwmods = "timer9";
@@ -374,7 +448,7 @@
374 }; 448 };
375 449
376 timer10: timer@48086000 { 450 timer10: timer@48086000 {
377 compatible = "ti,omap2-timer"; 451 compatible = "ti,omap3430-timer";
378 reg = <0x48086000 0x400>; 452 reg = <0x48086000 0x400>;
379 interrupts = <46>; 453 interrupts = <46>;
380 ti,hwmods = "timer10"; 454 ti,hwmods = "timer10";
@@ -382,7 +456,7 @@
382 }; 456 };
383 457
384 timer11: timer@48088000 { 458 timer11: timer@48088000 {
385 compatible = "ti,omap2-timer"; 459 compatible = "ti,omap3430-timer";
386 reg = <0x48088000 0x400>; 460 reg = <0x48088000 0x400>;
387 interrupts = <47>; 461 interrupts = <47>;
388 ti,hwmods = "timer11"; 462 ti,hwmods = "timer11";
@@ -390,7 +464,7 @@
390 }; 464 };
391 465
392 timer12: timer@48304000 { 466 timer12: timer@48304000 {
393 compatible = "ti,omap2-timer"; 467 compatible = "ti,omap3430-timer";
394 reg = <0x48304000 0x400>; 468 reg = <0x48304000 0x400>;
395 interrupts = <95>; 469 interrupts = <95>;
396 ti,hwmods = "timer12"; 470 ti,hwmods = "timer12";
@@ -428,5 +502,27 @@
428 }; 502 };
429 }; 503 };
430 504
505 gpmc: gpmc@6e000000 {
506 compatible = "ti,omap3430-gpmc";
507 ti,hwmods = "gpmc";
508 reg = <0x6e000000 0x02d0>;
509 interrupts = <20>;
510 gpmc,num-cs = <8>;
511 gpmc,num-waitpins = <4>;
512 #address-cells = <2>;
513 #size-cells = <1>;
514 };
515
516 usb_otg_hs: usb_otg_hs@480ab000 {
517 compatible = "ti,omap3-musb";
518 reg = <0x480ab000 0x1000>;
519 interrupts = <0 92 0x4>, <0 93 0x4>;
520 interrupt-names = "mc", "dma";
521 ti,hwmods = "usb_otg_hs";
522 usb-phy = <&usb2_phy>;
523 multipoint = <1>;
524 num-eps = <16>;
525 ram-bits = <12>;
526 };
431 }; 527 };
432}; 528};
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
new file mode 100644
index 000000000000..144ae43453c4
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -0,0 +1,190 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap34xx.dtsi"
11
12/ {
13 model = "TI OMAP3430 SDP";
14 compatible = "ti,omap3430-sdp", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20};
21
22&i2c1 {
23 clock-frequency = <2600000>;
24
25 twl: twl@48 {
26 reg = <0x48>;
27 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
28 };
29};
30
31/include/ "twl4030.dtsi"
32
33&mmc1 {
34 vmmc-supply = <&vmmc1>;
35 vmmc_aux-supply = <&vsim>;
36 bus-width = <8>;
37};
38
39&mmc2 {
40 status = "disabled";
41};
42
43&mmc3 {
44 status = "disabled";
45};
46
47&gpmc {
48 ranges = <0 0 0x10000000 0x08000000>,
49 <1 0 0x28000000 0x08000000>,
50 <2 0 0x20000000 0x10000000>;
51
52 nor@0,0 {
53 compatible = "cfi-flash";
54 linux,mtd-name= "intel,pf48f6000m0y1be";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 reg = <0 0 0x08000000>;
58 bank-width = <2>;
59
60 gpmc,mux-add-data = <2>;
61 gpmc,cs-on-ns = <0>;
62 gpmc,cs-rd-off-ns = <186>;
63 gpmc,cs-wr-off-ns = <186>;
64 gpmc,adv-on-ns = <12>;
65 gpmc,adv-rd-off-ns = <48>;
66 gpmc,adv-wr-off-ns = <48>;
67 gpmc,oe-on-ns = <54>;
68 gpmc,oe-off-ns = <168>;
69 gpmc,we-on-ns = <54>;
70 gpmc,we-off-ns = <168>;
71 gpmc,rd-cycle-ns = <186>;
72 gpmc,wr-cycle-ns = <186>;
73 gpmc,access-ns = <114>;
74 gpmc,page-burst-access-ns = <6>;
75 gpmc,bus-turnaround-ns = <12>;
76 gpmc,cycle2cycle-delay-ns = <18>;
77 gpmc,wr-data-mux-bus-ns = <90>;
78 gpmc,wr-access-ns = <186>;
79 gpmc,cycle2cycle-samecsen;
80 gpmc,cycle2cycle-diffcsen;
81
82 partition@0 {
83 label = "bootloader-nor";
84 reg = <0 0x40000>;
85 };
86 partition@0x40000 {
87 label = "params-nor";
88 reg = <0x40000 0x40000>;
89 };
90 partition@0x80000 {
91 label = "kernel-nor";
92 reg = <0x80000 0x200000>;
93 };
94 partition@0x280000 {
95 label = "filesystem-nor";
96 reg = <0x240000 0x7d80000>;
97 };
98 };
99
100 nand@1,0 {
101 linux,mtd-name= "micron,mt29f1g08abb";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 reg = <1 0 0x08000000>;
105 nand-bus-width = <8>;
106
107 ti,nand-ecc-opt = "sw";
108 gpmc,device-nand;
109 gpmc,cs-on-ns = <0>;
110 gpmc,cs-rd-off-ns = <36>;
111 gpmc,cs-wr-off-ns = <36>;
112 gpmc,adv-on-ns = <6>;
113 gpmc,adv-rd-off-ns = <24>;
114 gpmc,adv-wr-off-ns = <36>;
115 gpmc,oe-on-ns = <6>;
116 gpmc,oe-off-ns = <48>;
117 gpmc,we-on-ns = <6>;
118 gpmc,we-off-ns = <30>;
119 gpmc,rd-cycle-ns = <72>;
120 gpmc,wr-cycle-ns = <72>;
121 gpmc,access-ns = <54>;
122 gpmc,wr-access-ns = <30>;
123
124 partition@0 {
125 label = "xloader-nand";
126 reg = <0 0x80000>;
127 };
128 partition@0x80000 {
129 label = "bootloader-nand";
130 reg = <0x80000 0x140000>;
131 };
132 partition@0x1c0000 {
133 label = "params-nand";
134 reg = <0x1c0000 0xc0000>;
135 };
136 partition@0x280000 {
137 label = "kernel-nand";
138 reg = <0x280000 0x500000>;
139 };
140 partition@0x780000 {
141 label = "filesystem-nand";
142 reg = <0x780000 0x7880000>;
143 };
144 };
145
146 onenand@2,0 {
147 linux,mtd-name= "samsung,kfm2g16q2m-deb8";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 reg = <2 0 0x10000000>;
151
152 gpmc,device-width = <2>;
153 gpmc,mux-add-data = <2>;
154 gpmc,cs-on-ns = <0>;
155 gpmc,cs-rd-off-ns = <84>;
156 gpmc,cs-wr-off-ns = <72>;
157 gpmc,adv-on-ns = <0>;
158 gpmc,adv-rd-off-ns = <18>;
159 gpmc,adv-wr-off-ns = <18>;
160 gpmc,oe-on-ns = <30>;
161 gpmc,oe-off-ns = <84>;
162 gpmc,we-on-ns = <0>;
163 gpmc,we-off-ns = <42>;
164 gpmc,rd-cycle-ns = <108>;
165 gpmc,wr-cycle-ns = <96>;
166 gpmc,access-ns = <78>;
167 gpmc,wr-data-mux-bus-ns = <30>;
168
169 partition@0 {
170 label = "xloader-onenand";
171 reg = <0 0x80000>;
172 };
173 partition@0x80000 {
174 label = "bootloader-onenand";
175 reg = <0x80000 0x40000>;
176 };
177 partition@0xc0000 {
178 label = "params-onenand";
179 reg = <0xc0000 0x20000>;
180 };
181 partition@0xe0000 {
182 label = "kernel-onenand";
183 reg = <0xe0000 0x200000>;
184 };
185 partition@0x2e0000 {
186 label = "filesystem-onenand";
187 reg = <0x2e0000 0xfd20000>;
188 };
189 };
190};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
new file mode 100644
index 000000000000..75ed4ae2e631
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -0,0 +1,28 @@
1/*
2 * Device Tree Source for OMAP34xx/OMAP35xx SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "omap3.dtsi"
12
13/ {
14 cpus {
15 cpu@0 {
16 /* OMAP343x/OMAP35xx variants OPP1-5 */
17 operating-points = <
18 /* kHz uV */
19 125000 975000
20 250000 1075000
21 500000 1200000
22 550000 1270000
23 600000 1350000
24 >;
25 clock-latency = <300000>; /* From legacy driver */
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 96bf0287cb9f..b89233e43b0f 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -15,6 +15,19 @@
15 serial3 = &uart4; 15 serial3 = &uart4;
16 }; 16 };
17 17
18 cpus {
19 /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
20 cpu@0 {
21 operating-points = <
22 /* kHz uV */
23 300000 975000
24 600000 1075000
25 800000 1200000
26 >;
27 clock-latency = <300000>; /* From legacy driver */
28 };
29 };
30
18 ocp { 31 ocp {
19 uart4: serial@49042000 { 32 uart4: serial@49042000 {
20 compatible = "ti,omap3-uart"; 33 compatible = "ti,omap3-uart";
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index 75466d2abfb5..e30cdf0f5ac1 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -5,7 +5,10 @@
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8/include/ "omap4-panda.dts" 8/dts-v1/;
9
10/include/ "omap443x.dtsi"
11/include/ "omap4-panda-common.dtsi"
9 12
10/* Pandaboard Rev A4+ have external pullups on SCL & SDA */ 13/* Pandaboard Rev A4+ have external pullups on SCL & SDA */
11&dss_hdmi_pins { 14&dss_hdmi_pins {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
new file mode 100644
index 000000000000..03bd60deb52b
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -0,0 +1,251 @@
1/*
2 * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/include/ "elpida_ecb240abacn.dtsi"
9
10/ {
11 model = "TI OMAP4 PandaBoard";
12 compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
13
14 memory {
15 device_type = "memory";
16 reg = <0x80000000 0x40000000>; /* 1 GB */
17 };
18
19 leds {
20 compatible = "gpio-leds";
21 heartbeat {
22 label = "pandaboard::status1";
23 gpios = <&gpio1 7 0>;
24 linux,default-trigger = "heartbeat";
25 };
26
27 mmc {
28 label = "pandaboard::status2";
29 gpios = <&gpio1 8 0>;
30 linux,default-trigger = "mmc0";
31 };
32 };
33
34 sound: sound {
35 compatible = "ti,abe-twl6040";
36 ti,model = "PandaBoard";
37
38 ti,mclk-freq = <38400000>;
39
40 ti,mcpdm = <&mcpdm>;
41
42 ti,twl6040 = <&twl6040>;
43
44 /* Audio routing */
45 ti,audio-routing =
46 "Headset Stereophone", "HSOL",
47 "Headset Stereophone", "HSOR",
48 "Ext Spk", "HFL",
49 "Ext Spk", "HFR",
50 "Line Out", "AUXL",
51 "Line Out", "AUXR",
52 "HSMIC", "Headset Mic",
53 "Headset Mic", "Headset Mic Bias",
54 "AFML", "Line In",
55 "AFMR", "Line In";
56 };
57};
58
59&omap4_pmx_core {
60 pinctrl-names = "default";
61 pinctrl-0 = <
62 &twl6040_pins
63 &mcpdm_pins
64 &mcbsp1_pins
65 &dss_hdmi_pins
66 &tpd12s015_pins
67 >;
68
69 twl6040_pins: pinmux_twl6040_pins {
70 pinctrl-single,pins = <
71 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */
72 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
73 >;
74 };
75
76 mcpdm_pins: pinmux_mcpdm_pins {
77 pinctrl-single,pins = <
78 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
79 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
80 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
81 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
82 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
83 >;
84 };
85
86 mcbsp1_pins: pinmux_mcbsp1_pins {
87 pinctrl-single,pins = <
88 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
89 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
90 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
91 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
92 >;
93 };
94
95 dss_hdmi_pins: pinmux_dss_hdmi_pins {
96 pinctrl-single,pins = <
97 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
98 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
99 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
100 >;
101 };
102
103 tpd12s015_pins: pinmux_tpd12s015_pins {
104 pinctrl-single,pins = <
105 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
106 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
107 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
108 >;
109 };
110
111 i2c1_pins: pinmux_i2c1_pins {
112 pinctrl-single,pins = <
113 0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
114 0xe4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
115 >;
116 };
117
118 i2c2_pins: pinmux_i2c2_pins {
119 pinctrl-single,pins = <
120 0xe6 0x118 /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
121 0xe8 0x118 /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
122 >;
123 };
124
125 i2c3_pins: pinmux_i2c3_pins {
126 pinctrl-single,pins = <
127 0xea 0x118 /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
128 0xec 0x118 /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
129 >;
130 };
131
132 i2c4_pins: pinmux_i2c4_pins {
133 pinctrl-single,pins = <
134 0xee 0x118 /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
135 0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
136 >;
137 };
138};
139
140&i2c1 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&i2c1_pins>;
143
144 clock-frequency = <400000>;
145
146 twl: twl@48 {
147 reg = <0x48>;
148 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
149 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
150 interrupt-parent = <&gic>;
151 };
152
153 twl6040: twl@4b {
154 compatible = "ti,twl6040";
155 reg = <0x4b>;
156 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
157 interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
158 interrupt-parent = <&gic>;
159 ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */
160
161 vio-supply = <&v1v8>;
162 v2v1-supply = <&v2v1>;
163 enable-active-high;
164 };
165};
166
167/include/ "twl6030.dtsi"
168
169&i2c2 {
170 pinctrl-names = "default";
171 pinctrl-0 = <&i2c2_pins>;
172
173 clock-frequency = <400000>;
174};
175
176&i2c3 {
177 pinctrl-names = "default";
178 pinctrl-0 = <&i2c3_pins>;
179
180 clock-frequency = <100000>;
181
182 /*
183 * Display monitor features are burnt in their EEPROM as EDID data.
184 * The EEPROM is connected as I2C slave device.
185 */
186 eeprom@50 {
187 compatible = "ti,eeprom";
188 reg = <0x50>;
189 };
190};
191
192&i2c4 {
193 pinctrl-names = "default";
194 pinctrl-0 = <&i2c4_pins>;
195
196 clock-frequency = <400000>;
197};
198
199&mmc1 {
200 vmmc-supply = <&vmmc>;
201 bus-width = <8>;
202};
203
204&mmc2 {
205 status = "disabled";
206};
207
208&mmc3 {
209 status = "disabled";
210};
211
212&mmc4 {
213 status = "disabled";
214};
215
216&mmc5 {
217 ti,non-removable;
218 bus-width = <4>;
219};
220
221&emif1 {
222 cs1-used;
223 device-handle = <&elpida_ECB240ABACN>;
224};
225
226&emif2 {
227 cs1-used;
228 device-handle = <&elpida_ECB240ABACN>;
229};
230
231&mcbsp2 {
232 status = "disabled";
233};
234
235&mcbsp3 {
236 status = "disabled";
237};
238
239&dmic {
240 status = "disabled";
241};
242
243&twl_usb_comparator {
244 usb-supply = <&vusb>;
245};
246
247&usb_otg_hs {
248 interface-type = <1>;
249 mode = <3>;
250 power = <50>;
251};
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index 73bc1a67e444..f1d8c217ce12 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -5,7 +5,10 @@
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8/include/ "omap4-panda.dts" 8/dts-v1/;
9
10/include/ "omap4460.dtsi"
11/include/ "omap4-panda-common.dtsi"
9 12
10/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ 13/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
11&sound { 14&sound {
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 4122efe31cfd..f8b221f0168e 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -7,202 +7,5 @@
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap4.dtsi" 10/include/ "omap443x.dtsi"
11/include/ "elpida_ecb240abacn.dtsi" 11/include/ "omap4-panda-common.dtsi"
12
13/ {
14 model = "TI OMAP4 PandaBoard";
15 compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
16
17 memory {
18 device_type = "memory";
19 reg = <0x80000000 0x40000000>; /* 1 GB */
20 };
21
22 leds {
23 compatible = "gpio-leds";
24 heartbeat {
25 label = "pandaboard::status1";
26 gpios = <&gpio1 7 0>;
27 linux,default-trigger = "heartbeat";
28 };
29
30 mmc {
31 label = "pandaboard::status2";
32 gpios = <&gpio1 8 0>;
33 linux,default-trigger = "mmc0";
34 };
35 };
36
37 sound: sound {
38 compatible = "ti,abe-twl6040";
39 ti,model = "PandaBoard";
40
41 ti,mclk-freq = <38400000>;
42
43 ti,mcpdm = <&mcpdm>;
44
45 ti,twl6040 = <&twl6040>;
46
47 /* Audio routing */
48 ti,audio-routing =
49 "Headset Stereophone", "HSOL",
50 "Headset Stereophone", "HSOR",
51 "Ext Spk", "HFL",
52 "Ext Spk", "HFR",
53 "Line Out", "AUXL",
54 "Line Out", "AUXR",
55 "HSMIC", "Headset Mic",
56 "Headset Mic", "Headset Mic Bias",
57 "AFML", "Line In",
58 "AFMR", "Line In";
59 };
60};
61
62&omap4_pmx_core {
63 pinctrl-names = "default";
64 pinctrl-0 = <
65 &twl6040_pins
66 &mcpdm_pins
67 &mcbsp1_pins
68 &dss_hdmi_pins
69 &tpd12s015_pins
70 >;
71
72 twl6040_pins: pinmux_twl6040_pins {
73 pinctrl-single,pins = <
74 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */
75 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
76 >;
77 };
78
79 mcpdm_pins: pinmux_mcpdm_pins {
80 pinctrl-single,pins = <
81 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
82 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
83 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
84 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
85 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
86 >;
87 };
88
89 mcbsp1_pins: pinmux_mcbsp1_pins {
90 pinctrl-single,pins = <
91 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
92 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
93 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
94 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
95 >;
96 };
97
98 dss_hdmi_pins: pinmux_dss_hdmi_pins {
99 pinctrl-single,pins = <
100 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
101 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
102 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
103 >;
104 };
105
106 tpd12s015_pins: pinmux_tpd12s015_pins {
107 pinctrl-single,pins = <
108 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
109 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
110 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
111 >;
112 };
113};
114
115&i2c1 {
116 clock-frequency = <400000>;
117
118 twl: twl@48 {
119 reg = <0x48>;
120 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
121 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
122 interrupt-parent = <&gic>;
123 };
124
125 twl6040: twl@4b {
126 compatible = "ti,twl6040";
127 reg = <0x4b>;
128 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
129 interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
130 interrupt-parent = <&gic>;
131 ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */
132
133 vio-supply = <&v1v8>;
134 v2v1-supply = <&v2v1>;
135 enable-active-high;
136 };
137};
138
139/include/ "twl6030.dtsi"
140
141&i2c2 {
142 clock-frequency = <400000>;
143};
144
145&i2c3 {
146 clock-frequency = <100000>;
147
148 /*
149 * Display monitor features are burnt in their EEPROM as EDID data.
150 * The EEPROM is connected as I2C slave device.
151 */
152 eeprom@50 {
153 compatible = "ti,eeprom";
154 reg = <0x50>;
155 };
156};
157
158&i2c4 {
159 clock-frequency = <400000>;
160};
161
162&mmc1 {
163 vmmc-supply = <&vmmc>;
164 bus-width = <8>;
165};
166
167&mmc2 {
168 status = "disabled";
169};
170
171&mmc3 {
172 status = "disabled";
173};
174
175&mmc4 {
176 status = "disabled";
177};
178
179&mmc5 {
180 ti,non-removable;
181 bus-width = <4>;
182};
183
184&emif1 {
185 cs1-used;
186 device-handle = <&elpida_ECB240ABACN>;
187};
188
189&emif2 {
190 cs1-used;
191 device-handle = <&elpida_ECB240ABACN>;
192};
193
194&mcbsp2 {
195 status = "disabled";
196};
197
198&mcbsp3 {
199 status = "disabled";
200};
201
202&dmic {
203 status = "disabled";
204};
205
206&twl_usb_comparator {
207 usb-supply = <&vusb>;
208};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 43e5258a9372..c387bdc1b1d1 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -7,7 +7,7 @@
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap4.dtsi" 10/include/ "omap443x.dtsi"
11/include/ "elpida_ecb240abacn.dtsi" 11/include/ "elpida_ecb240abacn.dtsi"
12 12
13/ { 13/ {
@@ -80,6 +80,32 @@
80 }; 80 };
81 }; 81 };
82 82
83 pwmleds {
84 compatible = "pwm-leds";
85 kpad {
86 label = "omap4::keypad";
87 pwms = <&twl_pwm 0 7812500>;
88 max-brightness = <127>;
89 };
90
91 charging {
92 label = "omap4:green:chrg";
93 pwms = <&twl_pwmled 0 7812500>;
94 max-brightness = <255>;
95 };
96 };
97
98 backlight {
99 compatible = "pwm-backlight";
100 pwms = <&twl_pwm 1 7812500>;
101 brightness-levels = <
102 0 10 20 30 40
103 50 60 70 80 90
104 100 110 120 127
105 >;
106 default-brightness-level = <13>;
107 };
108
83 sound { 109 sound {
84 compatible = "ti,abe-twl6040"; 110 compatible = "ti,abe-twl6040";
85 ti,model = "SDP4430"; 111 ti,model = "SDP4430";
@@ -212,9 +238,40 @@
212 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */ 238 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
213 >; 239 >;
214 }; 240 };
241
242 i2c1_pins: pinmux_i2c1_pins {
243 pinctrl-single,pins = <
244 0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
245 0xe4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
246 >;
247 };
248
249 i2c2_pins: pinmux_i2c2_pins {
250 pinctrl-single,pins = <
251 0xe6 0x118 /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
252 0xe8 0x118 /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
253 >;
254 };
255
256 i2c3_pins: pinmux_i2c3_pins {
257 pinctrl-single,pins = <
258 0xea 0x118 /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
259 0xec 0x118 /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
260 >;
261 };
262
263 i2c4_pins: pinmux_i2c4_pins {
264 pinctrl-single,pins = <
265 0xee 0x118 /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
266 0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
267 >;
268 };
215}; 269};
216 270
217&i2c1 { 271&i2c1 {
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c1_pins>;
274
218 clock-frequency = <400000>; 275 clock-frequency = <400000>;
219 276
220 twl: twl@48 { 277 twl: twl@48 {
@@ -253,10 +310,16 @@
253/include/ "twl6030.dtsi" 310/include/ "twl6030.dtsi"
254 311
255&i2c2 { 312&i2c2 {
313 pinctrl-names = "default";
314 pinctrl-0 = <&i2c2_pins>;
315
256 clock-frequency = <400000>; 316 clock-frequency = <400000>;
257}; 317};
258 318
259&i2c3 { 319&i2c3 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c3_pins>;
322
260 clock-frequency = <400000>; 323 clock-frequency = <400000>;
261 324
262 /* 325 /*
@@ -279,6 +342,9 @@
279}; 342};
280 343
281&i2c4 { 344&i2c4 {
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c4_pins>;
347
282 clock-frequency = <400000>; 348 clock-frequency = <400000>;
283 349
284 /* 350 /*
@@ -428,3 +494,9 @@
428&twl_usb_comparator { 494&twl_usb_comparator {
429 usb-supply = <&vusb>; 495 usb-supply = <&vusb>;
430}; 496};
497
498&usb_otg_hs {
499 interface-type = <1>;
500 mode = <3>;
501 power = <50>;
502};
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 6601e6af6092..222a413c2c51 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -7,7 +7,7 @@
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap4.dtsi" 10/include/ "omap443x.dtsi"
11 11
12/ { 12/ {
13 model = "Variscite OMAP4 SOM"; 13 model = "Variscite OMAP4 SOM";
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index b7db1a2b6ca7..2a5642882c8a 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -94,6 +94,11 @@
94 #size-cells = <1>; 94 #size-cells = <1>;
95 ranges; 95 ranges;
96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
97 reg = <0x44000000 0x1000>,
98 <0x44800000 0x2000>,
99 <0x45000000 0x1000>;
100 interrupts = <0 9 0x4>,
101 <0 10 0x4>;
97 102
98 counter32k: counter@4a304000 { 103 counter32k: counter@4a304000 {
99 compatible = "ti,omap-counter32k"; 104 compatible = "ti,omap-counter32k";
@@ -118,15 +123,28 @@
118 pinctrl-single,function-mask = <0x7fff>; 123 pinctrl-single,function-mask = <0x7fff>;
119 }; 124 };
120 125
126 sdma: dma-controller@4a056000 {
127 compatible = "ti,omap4430-sdma";
128 reg = <0x4a056000 0x1000>;
129 interrupts = <0 12 0x4>,
130 <0 13 0x4>,
131 <0 14 0x4>,
132 <0 15 0x4>;
133 #dma-cells = <1>;
134 #dma-channels = <32>;
135 #dma-requests = <127>;
136 };
137
121 gpio1: gpio@4a310000 { 138 gpio1: gpio@4a310000 {
122 compatible = "ti,omap4-gpio"; 139 compatible = "ti,omap4-gpio";
123 reg = <0x4a310000 0x200>; 140 reg = <0x4a310000 0x200>;
124 interrupts = <0 29 0x4>; 141 interrupts = <0 29 0x4>;
125 ti,hwmods = "gpio1"; 142 ti,hwmods = "gpio1";
143 ti,gpio-always-on;
126 gpio-controller; 144 gpio-controller;
127 #gpio-cells = <2>; 145 #gpio-cells = <2>;
128 interrupt-controller; 146 interrupt-controller;
129 #interrupt-cells = <1>; 147 #interrupt-cells = <2>;
130 }; 148 };
131 149
132 gpio2: gpio@48055000 { 150 gpio2: gpio@48055000 {
@@ -137,7 +155,7 @@
137 gpio-controller; 155 gpio-controller;
138 #gpio-cells = <2>; 156 #gpio-cells = <2>;
139 interrupt-controller; 157 interrupt-controller;
140 #interrupt-cells = <1>; 158 #interrupt-cells = <2>;
141 }; 159 };
142 160
143 gpio3: gpio@48057000 { 161 gpio3: gpio@48057000 {
@@ -148,7 +166,7 @@
148 gpio-controller; 166 gpio-controller;
149 #gpio-cells = <2>; 167 #gpio-cells = <2>;
150 interrupt-controller; 168 interrupt-controller;
151 #interrupt-cells = <1>; 169 #interrupt-cells = <2>;
152 }; 170 };
153 171
154 gpio4: gpio@48059000 { 172 gpio4: gpio@48059000 {
@@ -159,7 +177,7 @@
159 gpio-controller; 177 gpio-controller;
160 #gpio-cells = <2>; 178 #gpio-cells = <2>;
161 interrupt-controller; 179 interrupt-controller;
162 #interrupt-cells = <1>; 180 #interrupt-cells = <2>;
163 }; 181 };
164 182
165 gpio5: gpio@4805b000 { 183 gpio5: gpio@4805b000 {
@@ -170,7 +188,7 @@
170 gpio-controller; 188 gpio-controller;
171 #gpio-cells = <2>; 189 #gpio-cells = <2>;
172 interrupt-controller; 190 interrupt-controller;
173 #interrupt-cells = <1>; 191 #interrupt-cells = <2>;
174 }; 192 };
175 193
176 gpio6: gpio@4805d000 { 194 gpio6: gpio@4805d000 {
@@ -181,7 +199,18 @@
181 gpio-controller; 199 gpio-controller;
182 #gpio-cells = <2>; 200 #gpio-cells = <2>;
183 interrupt-controller; 201 interrupt-controller;
184 #interrupt-cells = <1>; 202 #interrupt-cells = <2>;
203 };
204
205 gpmc: gpmc@50000000 {
206 compatible = "ti,omap4430-gpmc";
207 reg = <0x50000000 0x1000>;
208 #address-cells = <2>;
209 #size-cells = <1>;
210 interrupts = <0 20 0x4>;
211 gpmc,num-cs = <8>;
212 gpmc,num-waitpins = <4>;
213 ti,hwmods = "gpmc";
185 }; 214 };
186 215
187 uart1: serial@4806a000 { 216 uart1: serial@4806a000 {
@@ -260,6 +289,16 @@
260 #size-cells = <0>; 289 #size-cells = <0>;
261 ti,hwmods = "mcspi1"; 290 ti,hwmods = "mcspi1";
262 ti,spi-num-cs = <4>; 291 ti,spi-num-cs = <4>;
292 dmas = <&sdma 35>,
293 <&sdma 36>,
294 <&sdma 37>,
295 <&sdma 38>,
296 <&sdma 39>,
297 <&sdma 40>,
298 <&sdma 41>,
299 <&sdma 42>;
300 dma-names = "tx0", "rx0", "tx1", "rx1",
301 "tx2", "rx2", "tx3", "rx3";
263 }; 302 };
264 303
265 mcspi2: spi@4809a000 { 304 mcspi2: spi@4809a000 {
@@ -270,6 +309,11 @@
270 #size-cells = <0>; 309 #size-cells = <0>;
271 ti,hwmods = "mcspi2"; 310 ti,hwmods = "mcspi2";
272 ti,spi-num-cs = <2>; 311 ti,spi-num-cs = <2>;
312 dmas = <&sdma 43>,
313 <&sdma 44>,
314 <&sdma 45>,
315 <&sdma 46>;
316 dma-names = "tx0", "rx0", "tx1", "rx1";
273 }; 317 };
274 318
275 mcspi3: spi@480b8000 { 319 mcspi3: spi@480b8000 {
@@ -280,6 +324,8 @@
280 #size-cells = <0>; 324 #size-cells = <0>;
281 ti,hwmods = "mcspi3"; 325 ti,hwmods = "mcspi3";
282 ti,spi-num-cs = <2>; 326 ti,spi-num-cs = <2>;
327 dmas = <&sdma 15>, <&sdma 16>;
328 dma-names = "tx0", "rx0";
283 }; 329 };
284 330
285 mcspi4: spi@480ba000 { 331 mcspi4: spi@480ba000 {
@@ -290,6 +336,8 @@
290 #size-cells = <0>; 336 #size-cells = <0>;
291 ti,hwmods = "mcspi4"; 337 ti,hwmods = "mcspi4";
292 ti,spi-num-cs = <1>; 338 ti,spi-num-cs = <1>;
339 dmas = <&sdma 70>, <&sdma 71>;
340 dma-names = "tx0", "rx0";
293 }; 341 };
294 342
295 mmc1: mmc@4809c000 { 343 mmc1: mmc@4809c000 {
@@ -299,6 +347,8 @@
299 ti,hwmods = "mmc1"; 347 ti,hwmods = "mmc1";
300 ti,dual-volt; 348 ti,dual-volt;
301 ti,needs-special-reset; 349 ti,needs-special-reset;
350 dmas = <&sdma 61>, <&sdma 62>;
351 dma-names = "tx", "rx";
302 }; 352 };
303 353
304 mmc2: mmc@480b4000 { 354 mmc2: mmc@480b4000 {
@@ -307,6 +357,8 @@
307 interrupts = <0 86 0x4>; 357 interrupts = <0 86 0x4>;
308 ti,hwmods = "mmc2"; 358 ti,hwmods = "mmc2";
309 ti,needs-special-reset; 359 ti,needs-special-reset;
360 dmas = <&sdma 47>, <&sdma 48>;
361 dma-names = "tx", "rx";
310 }; 362 };
311 363
312 mmc3: mmc@480ad000 { 364 mmc3: mmc@480ad000 {
@@ -315,6 +367,8 @@
315 interrupts = <0 94 0x4>; 367 interrupts = <0 94 0x4>;
316 ti,hwmods = "mmc3"; 368 ti,hwmods = "mmc3";
317 ti,needs-special-reset; 369 ti,needs-special-reset;
370 dmas = <&sdma 77>, <&sdma 78>;
371 dma-names = "tx", "rx";
318 }; 372 };
319 373
320 mmc4: mmc@480d1000 { 374 mmc4: mmc@480d1000 {
@@ -323,6 +377,8 @@
323 interrupts = <0 96 0x4>; 377 interrupts = <0 96 0x4>;
324 ti,hwmods = "mmc4"; 378 ti,hwmods = "mmc4";
325 ti,needs-special-reset; 379 ti,needs-special-reset;
380 dmas = <&sdma 57>, <&sdma 58>;
381 dma-names = "tx", "rx";
326 }; 382 };
327 383
328 mmc5: mmc@480d5000 { 384 mmc5: mmc@480d5000 {
@@ -331,6 +387,8 @@
331 interrupts = <0 59 0x4>; 387 interrupts = <0 59 0x4>;
332 ti,hwmods = "mmc5"; 388 ti,hwmods = "mmc5";
333 ti,needs-special-reset; 389 ti,needs-special-reset;
390 dmas = <&sdma 59>, <&sdma 60>;
391 dma-names = "tx", "rx";
334 }; 392 };
335 393
336 wdt2: wdt@4a314000 { 394 wdt2: wdt@4a314000 {
@@ -347,6 +405,9 @@
347 reg-names = "mpu", "dma"; 405 reg-names = "mpu", "dma";
348 interrupts = <0 112 0x4>; 406 interrupts = <0 112 0x4>;
349 ti,hwmods = "mcpdm"; 407 ti,hwmods = "mcpdm";
408 dmas = <&sdma 65>,
409 <&sdma 66>;
410 dma-names = "up_link", "dn_link";
350 }; 411 };
351 412
352 dmic: dmic@4012e000 { 413 dmic: dmic@4012e000 {
@@ -356,6 +417,8 @@
356 reg-names = "mpu", "dma"; 417 reg-names = "mpu", "dma";
357 interrupts = <0 114 0x4>; 418 interrupts = <0 114 0x4>;
358 ti,hwmods = "dmic"; 419 ti,hwmods = "dmic";
420 dmas = <&sdma 67>;
421 dma-names = "up_link";
359 }; 422 };
360 423
361 mcbsp1: mcbsp@40122000 { 424 mcbsp1: mcbsp@40122000 {
@@ -367,6 +430,9 @@
367 interrupt-names = "common"; 430 interrupt-names = "common";
368 ti,buffer-size = <128>; 431 ti,buffer-size = <128>;
369 ti,hwmods = "mcbsp1"; 432 ti,hwmods = "mcbsp1";
433 dmas = <&sdma 33>,
434 <&sdma 34>;
435 dma-names = "tx", "rx";
370 }; 436 };
371 437
372 mcbsp2: mcbsp@40124000 { 438 mcbsp2: mcbsp@40124000 {
@@ -378,6 +444,9 @@
378 interrupt-names = "common"; 444 interrupt-names = "common";
379 ti,buffer-size = <128>; 445 ti,buffer-size = <128>;
380 ti,hwmods = "mcbsp2"; 446 ti,hwmods = "mcbsp2";
447 dmas = <&sdma 17>,
448 <&sdma 18>;
449 dma-names = "tx", "rx";
381 }; 450 };
382 451
383 mcbsp3: mcbsp@40126000 { 452 mcbsp3: mcbsp@40126000 {
@@ -389,6 +458,9 @@
389 interrupt-names = "common"; 458 interrupt-names = "common";
390 ti,buffer-size = <128>; 459 ti,buffer-size = <128>;
391 ti,hwmods = "mcbsp3"; 460 ti,hwmods = "mcbsp3";
461 dmas = <&sdma 19>,
462 <&sdma 20>;
463 dma-names = "tx", "rx";
392 }; 464 };
393 465
394 mcbsp4: mcbsp@48096000 { 466 mcbsp4: mcbsp@48096000 {
@@ -399,6 +471,9 @@
399 interrupt-names = "common"; 471 interrupt-names = "common";
400 ti,buffer-size = <128>; 472 ti,buffer-size = <128>;
401 ti,hwmods = "mcbsp4"; 473 ti,hwmods = "mcbsp4";
474 dmas = <&sdma 31>,
475 <&sdma 32>;
476 dma-names = "tx", "rx";
402 }; 477 };
403 478
404 keypad: keypad@4a31c000 { 479 keypad: keypad@4a31c000 {
@@ -438,10 +513,15 @@
438 #size-cells = <1>; 513 #size-cells = <1>;
439 ranges; 514 ranges;
440 ti,hwmods = "ocp2scp_usb_phy"; 515 ti,hwmods = "ocp2scp_usb_phy";
516 usb2_phy: usb2phy@4a0ad080 {
517 compatible = "ti,omap-usb2";
518 reg = <0x4a0ad080 0x58>;
519 ctrl-module = <&omap_control_usb>;
520 };
441 }; 521 };
442 522
443 timer1: timer@4a318000 { 523 timer1: timer@4a318000 {
444 compatible = "ti,omap2-timer"; 524 compatible = "ti,omap3430-timer";
445 reg = <0x4a318000 0x80>; 525 reg = <0x4a318000 0x80>;
446 interrupts = <0 37 0x4>; 526 interrupts = <0 37 0x4>;
447 ti,hwmods = "timer1"; 527 ti,hwmods = "timer1";
@@ -449,28 +529,28 @@
449 }; 529 };
450 530
451 timer2: timer@48032000 { 531 timer2: timer@48032000 {
452 compatible = "ti,omap2-timer"; 532 compatible = "ti,omap3430-timer";
453 reg = <0x48032000 0x80>; 533 reg = <0x48032000 0x80>;
454 interrupts = <0 38 0x4>; 534 interrupts = <0 38 0x4>;
455 ti,hwmods = "timer2"; 535 ti,hwmods = "timer2";
456 }; 536 };
457 537
458 timer3: timer@48034000 { 538 timer3: timer@48034000 {
459 compatible = "ti,omap2-timer"; 539 compatible = "ti,omap4430-timer";
460 reg = <0x48034000 0x80>; 540 reg = <0x48034000 0x80>;
461 interrupts = <0 39 0x4>; 541 interrupts = <0 39 0x4>;
462 ti,hwmods = "timer3"; 542 ti,hwmods = "timer3";
463 }; 543 };
464 544
465 timer4: timer@48036000 { 545 timer4: timer@48036000 {
466 compatible = "ti,omap2-timer"; 546 compatible = "ti,omap4430-timer";
467 reg = <0x48036000 0x80>; 547 reg = <0x48036000 0x80>;
468 interrupts = <0 40 0x4>; 548 interrupts = <0 40 0x4>;
469 ti,hwmods = "timer4"; 549 ti,hwmods = "timer4";
470 }; 550 };
471 551
472 timer5: timer@40138000 { 552 timer5: timer@40138000 {
473 compatible = "ti,omap2-timer"; 553 compatible = "ti,omap4430-timer";
474 reg = <0x40138000 0x80>, 554 reg = <0x40138000 0x80>,
475 <0x49038000 0x80>; 555 <0x49038000 0x80>;
476 interrupts = <0 41 0x4>; 556 interrupts = <0 41 0x4>;
@@ -479,7 +559,7 @@
479 }; 559 };
480 560
481 timer6: timer@4013a000 { 561 timer6: timer@4013a000 {
482 compatible = "ti,omap2-timer"; 562 compatible = "ti,omap4430-timer";
483 reg = <0x4013a000 0x80>, 563 reg = <0x4013a000 0x80>,
484 <0x4903a000 0x80>; 564 <0x4903a000 0x80>;
485 interrupts = <0 42 0x4>; 565 interrupts = <0 42 0x4>;
@@ -488,7 +568,7 @@
488 }; 568 };
489 569
490 timer7: timer@4013c000 { 570 timer7: timer@4013c000 {
491 compatible = "ti,omap2-timer"; 571 compatible = "ti,omap4430-timer";
492 reg = <0x4013c000 0x80>, 572 reg = <0x4013c000 0x80>,
493 <0x4903c000 0x80>; 573 <0x4903c000 0x80>;
494 interrupts = <0 43 0x4>; 574 interrupts = <0 43 0x4>;
@@ -497,7 +577,7 @@
497 }; 577 };
498 578
499 timer8: timer@4013e000 { 579 timer8: timer@4013e000 {
500 compatible = "ti,omap2-timer"; 580 compatible = "ti,omap4430-timer";
501 reg = <0x4013e000 0x80>, 581 reg = <0x4013e000 0x80>,
502 <0x4903e000 0x80>; 582 <0x4903e000 0x80>;
503 interrupts = <0 44 0x4>; 583 interrupts = <0 44 0x4>;
@@ -507,7 +587,7 @@
507 }; 587 };
508 588
509 timer9: timer@4803e000 { 589 timer9: timer@4803e000 {
510 compatible = "ti,omap2-timer"; 590 compatible = "ti,omap4430-timer";
511 reg = <0x4803e000 0x80>; 591 reg = <0x4803e000 0x80>;
512 interrupts = <0 45 0x4>; 592 interrupts = <0 45 0x4>;
513 ti,hwmods = "timer9"; 593 ti,hwmods = "timer9";
@@ -515,7 +595,7 @@
515 }; 595 };
516 596
517 timer10: timer@48086000 { 597 timer10: timer@48086000 {
518 compatible = "ti,omap2-timer"; 598 compatible = "ti,omap3430-timer";
519 reg = <0x48086000 0x80>; 599 reg = <0x48086000 0x80>;
520 interrupts = <0 46 0x4>; 600 interrupts = <0 46 0x4>;
521 ti,hwmods = "timer10"; 601 ti,hwmods = "timer10";
@@ -523,7 +603,7 @@
523 }; 603 };
524 604
525 timer11: timer@48088000 { 605 timer11: timer@48088000 {
526 compatible = "ti,omap2-timer"; 606 compatible = "ti,omap4430-timer";
527 reg = <0x48088000 0x80>; 607 reg = <0x48088000 0x80>;
528 interrupts = <0 47 0x4>; 608 interrupts = <0 47 0x4>;
529 ti,hwmods = "timer11"; 609 ti,hwmods = "timer11";
@@ -559,5 +639,26 @@
559 interrupts = <0 77 0x4>; 639 interrupts = <0 77 0x4>;
560 }; 640 };
561 }; 641 };
642
643 omap_control_usb: omap-control-usb@4a002300 {
644 compatible = "ti,omap-control-usb";
645 reg = <0x4a002300 0x4>,
646 <0x4a00233c 0x4>;
647 reg-names = "control_dev_conf", "otghs_control";
648 ti,type = <1>;
649 };
650
651 usb_otg_hs: usb_otg_hs@4a0ab000 {
652 compatible = "ti,omap4-musb";
653 reg = <0x4a0ab000 0x7ff>;
654 interrupts = <0 92 0x4>, <0 93 0x4>;
655 interrupt-names = "mc", "dma";
656 ti,hwmods = "usb_otg_hs";
657 usb-phy = <&usb2_phy>;
658 multipoint = <1>;
659 num-eps = <16>;
660 ram-bits = <12>;
661 ti,has-mailbox;
662 };
562 }; 663 };
563}; 664};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
new file mode 100644
index 000000000000..cccf39af4925
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -0,0 +1,27 @@
1/*
2 * Device Tree Source for OMAP443x SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "omap4.dtsi"
12
13/ {
14 cpus {
15 cpu@0 {
16 /* OMAP443x variants OPP50-OPPNT */
17 operating-points = <
18 /* kHz uV */
19 300000 1025000
20 600000 1200000
21 800000 1313000
22 1008000 1375000
23 >;
24 clock-latency = <300000>; /* From legacy driver */
25 };
26 };
27};
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
new file mode 100644
index 000000000000..7c2c23cc17ef
--- /dev/null
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -0,0 +1,32 @@
1/*
2 * Device Tree Source for OMAP4460 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10/include/ "omap4.dtsi"
11
12/ {
13 cpus {
14 /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
15 cpu@0 {
16 operating-points = <
17 /* kHz uV */
18 350000 975000
19 700000 1075000
20 920000 1200000
21 >;
22 clock-latency = <300000>; /* From legacy driver */
23 };
24 };
25
26 pmu {
27 compatible = "arm,cortex-a9-pmu";
28 interrupts = <0 54 0x4>,
29 <0 55 0x4>;
30 ti,hwmods = "debugss";
31 };
32};
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 8722c15bbba2..982acd19477d 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -16,7 +16,7 @@
16 16
17 memory { 17 memory {
18 device_type = "memory"; 18 device_type = "memory";
19 reg = <0x80000000 0x80000000>; /* 2 GB */ 19 reg = <0x80000000 0x7F000000>; /* 2032 MB */
20 }; 20 };
21 21
22 vmmcsd_fixed: fixedregulator-mmcsd { 22 vmmcsd_fixed: fixedregulator-mmcsd {
@@ -80,6 +80,68 @@
80 0x15a 0x100 /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */ 80 0x15a 0x100 /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
81 >; 81 >;
82 }; 82 };
83
84 i2c1_pins: pinmux_i2c1_pins {
85 pinctrl-single,pins = <
86 0x1b2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
87 0x1b4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
88 >;
89 };
90
91 i2c2_pins: pinmux_i2c2_pins {
92 pinctrl-single,pins = <
93 0x178 0x100 /* i2c2_scl INPUTENABLE | MODE0 */
94 0x17a 0x100 /* i2c2_sda INPUTENABLE | MODE0 */
95 >;
96 };
97
98 i2c3_pins: pinmux_i2c3_pins {
99 pinctrl-single,pins = <
100 0x13a 0x100 /* i2c3_scl INPUTENABLE | MODE0 */
101 0x13c 0x100 /* i2c3_sda INPUTENABLE | MODE0 */
102 >;
103 };
104
105 i2c4_pins: pinmux_i2c4_pins {
106 pinctrl-single,pins = <
107 0xb8 0x100 /* i2c4_scl INPUTENABLE | MODE0 */
108 0xba 0x100 /* i2c4_sda INPUTENABLE | MODE0 */
109 >;
110 };
111
112 i2c5_pins: pinmux_i2c5_pins {
113 pinctrl-single,pins = <
114 0x184 0x100 /* i2c5_scl INPUTENABLE | MODE0 */
115 0x186 0x100 /* i2c5_sda INPUTENABLE | MODE0 */
116 >;
117 };
118
119 mcspi2_pins: pinmux_mcspi2_pins {
120 pinctrl-single,pins = <
121 0xbc 0x100 /* MCSPI2_CLK INPUTENABLE | MODE0 */
122 0xbe 0x100 /* MCSPI2_SIMO INPUTENABLE | MODE0 */
123 0xc0 0x118 /* MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/
124 0xc2 0x0 /* MCSPI2_CS MODE0*/
125 >;
126 };
127
128 mcspi3_pins: pinmux_mcspi3_pins {
129 pinctrl-single,pins = <
130 0x78 0x101 /* MCSPI2_SOMI INPUTENABLE | MODE1 */
131 0x7a 0x101 /* MCSPI2_CS INPUTENABLE | MODE1 */
132 0x7c 0x101 /* MCSPI2_SIMO INPUTENABLE | MODE1 */
133 0x7e 0x101 /* MCSPI2_CLK INPUTENABLE | MODE1 */
134 >;
135 };
136
137 mcspi4_pins: pinmux_mcspi4_pins {
138 pinctrl-single,pins = <
139 0x164 0x101 /* MCSPI2_CLK INPUTENABLE | MODE1 */
140 0x168 0x101 /* MCSPI2_SIMO INPUTENABLE | MODE1 */
141 0x16a 0x101 /* MCSPI2_SOMI INPUTENABLE | MODE1 */
142 0x16c 0x101 /* MCSPI2_CS INPUTENABLE | MODE1 */
143 >;
144 };
83}; 145};
84 146
85&mmc1 { 147&mmc1 {
@@ -106,7 +168,17 @@
106 status = "disabled"; 168 status = "disabled";
107}; 169};
108 170
171&i2c1 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&i2c1_pins>;
174
175 clock-frequency = <400000>;
176};
177
109&i2c2 { 178&i2c2 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&i2c2_pins>;
181
110 clock-frequency = <400000>; 182 clock-frequency = <400000>;
111 183
112 /* Pressure Sensor */ 184 /* Pressure Sensor */
@@ -116,7 +188,17 @@
116 }; 188 };
117}; 189};
118 190
191&i2c3 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&i2c3_pins>;
194
195 clock-frequency = <400000>;
196};
197
119&i2c4 { 198&i2c4 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&i2c4_pins>;
201
120 clock-frequency = <400000>; 202 clock-frequency = <400000>;
121 203
122 /* Temperature Sensor */ 204 /* Temperature Sensor */
@@ -126,6 +208,13 @@
126 }; 208 };
127}; 209};
128 210
211&i2c5 {
212 pinctrl-names = "default";
213 pinctrl-0 = <&i2c5_pins>;
214
215 clock-frequency = <400000>;
216};
217
129&keypad { 218&keypad {
130 keypad,num-rows = <8>; 219 keypad,num-rows = <8>;
131 keypad,num-columns = <8>; 220 keypad,num-columns = <8>;
@@ -151,3 +240,22 @@
151 cs1-used; 240 cs1-used;
152 device-handle = <&samsung_K3PE0E000B>; 241 device-handle = <&samsung_K3PE0E000B>;
153}; 242};
243
244&mcspi1 {
245
246};
247
248&mcspi2 {
249 pinctrl-names = "default";
250 pinctrl-0 = <&mcspi2_pins>;
251};
252
253&mcspi3 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&mcspi3_pins>;
256};
257
258&mcspi4 {
259 pinctrl-names = "default";
260 pinctrl-0 = <&mcspi4_pins>;
261};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 790bb2a4b343..3dd7ff825828 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -18,6 +18,9 @@
18/include/ "skeleton.dtsi" 18/include/ "skeleton.dtsi"
19 19
20/ { 20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
21 compatible = "ti,omap5"; 24 compatible = "ti,omap5";
22 interrupt-parent = <&gic>; 25 interrupt-parent = <&gic>;
23 26
@@ -33,24 +36,32 @@
33 cpus { 36 cpus {
34 cpu@0 { 37 cpu@0 {
35 compatible = "arm,cortex-a15"; 38 compatible = "arm,cortex-a15";
36 timer {
37 compatible = "arm,armv7-timer";
38 /* 14th PPI IRQ, active low level-sensitive */
39 interrupts = <1 14 0x308>;
40 clock-frequency = <6144000>;
41 };
42 }; 39 };
43 cpu@1 { 40 cpu@1 {
44 compatible = "arm,cortex-a15"; 41 compatible = "arm,cortex-a15";
45 timer {
46 compatible = "arm,armv7-timer";
47 /* 14th PPI IRQ, active low level-sensitive */
48 interrupts = <1 14 0x308>;
49 clock-frequency = <6144000>;
50 };
51 }; 42 };
52 }; 43 };
53 44
45 timer {
46 compatible = "arm,armv7-timer";
47 /* PPI secure/nonsecure IRQ, active low level-sensitive */
48 interrupts = <1 13 0x308>,
49 <1 14 0x308>,
50 <1 11 0x308>,
51 <1 10 0x308>;
52 clock-frequency = <6144000>;
53 };
54
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 reg = <0x48211000 0x1000>,
60 <0x48212000 0x1000>,
61 <0x48214000 0x2000>,
62 <0x48216000 0x2000>;
63 };
64
54 /* 65 /*
55 * The soc node represents the soc top level view. It is uses for IPs 66 * The soc node represents the soc top level view. It is uses for IPs
56 * that are not memory mapped in the MPU view or for the MPU itself. 67 * that are not memory mapped in the MPU view or for the MPU itself.
@@ -76,6 +87,11 @@
76 #size-cells = <1>; 87 #size-cells = <1>;
77 ranges; 88 ranges;
78 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 89 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
90 reg = <0x44000000 0x2000>,
91 <0x44800000 0x3000>,
92 <0x45000000 0x4000>;
93 interrupts = <0 9 0x4>,
94 <0 10 0x4>;
79 95
80 counter32k: counter@4ae04000 { 96 counter32k: counter@4ae04000 {
81 compatible = "ti,omap-counter32k"; 97 compatible = "ti,omap-counter32k";
@@ -100,12 +116,16 @@
100 pinctrl-single,function-mask = <0x7fff>; 116 pinctrl-single,function-mask = <0x7fff>;
101 }; 117 };
102 118
103 gic: interrupt-controller@48211000 { 119 sdma: dma-controller@4a056000 {
104 compatible = "arm,cortex-a15-gic"; 120 compatible = "ti,omap4430-sdma";
105 interrupt-controller; 121 reg = <0x4a056000 0x1000>;
106 #interrupt-cells = <3>; 122 interrupts = <0 12 0x4>,
107 reg = <0x48211000 0x1000>, 123 <0 13 0x4>,
108 <0x48212000 0x1000>; 124 <0 14 0x4>,
125 <0 15 0x4>;
126 #dma-cells = <1>;
127 #dma-channels = <32>;
128 #dma-requests = <127>;
109 }; 129 };
110 130
111 gpio1: gpio@4ae10000 { 131 gpio1: gpio@4ae10000 {
@@ -113,10 +133,11 @@
113 reg = <0x4ae10000 0x200>; 133 reg = <0x4ae10000 0x200>;
114 interrupts = <0 29 0x4>; 134 interrupts = <0 29 0x4>;
115 ti,hwmods = "gpio1"; 135 ti,hwmods = "gpio1";
136 ti,gpio-always-on;
116 gpio-controller; 137 gpio-controller;
117 #gpio-cells = <2>; 138 #gpio-cells = <2>;
118 interrupt-controller; 139 interrupt-controller;
119 #interrupt-cells = <1>; 140 #interrupt-cells = <2>;
120 }; 141 };
121 142
122 gpio2: gpio@48055000 { 143 gpio2: gpio@48055000 {
@@ -127,7 +148,7 @@
127 gpio-controller; 148 gpio-controller;
128 #gpio-cells = <2>; 149 #gpio-cells = <2>;
129 interrupt-controller; 150 interrupt-controller;
130 #interrupt-cells = <1>; 151 #interrupt-cells = <2>;
131 }; 152 };
132 153
133 gpio3: gpio@48057000 { 154 gpio3: gpio@48057000 {
@@ -138,7 +159,7 @@
138 gpio-controller; 159 gpio-controller;
139 #gpio-cells = <2>; 160 #gpio-cells = <2>;
140 interrupt-controller; 161 interrupt-controller;
141 #interrupt-cells = <1>; 162 #interrupt-cells = <2>;
142 }; 163 };
143 164
144 gpio4: gpio@48059000 { 165 gpio4: gpio@48059000 {
@@ -149,7 +170,7 @@
149 gpio-controller; 170 gpio-controller;
150 #gpio-cells = <2>; 171 #gpio-cells = <2>;
151 interrupt-controller; 172 interrupt-controller;
152 #interrupt-cells = <1>; 173 #interrupt-cells = <2>;
153 }; 174 };
154 175
155 gpio5: gpio@4805b000 { 176 gpio5: gpio@4805b000 {
@@ -160,7 +181,7 @@
160 gpio-controller; 181 gpio-controller;
161 #gpio-cells = <2>; 182 #gpio-cells = <2>;
162 interrupt-controller; 183 interrupt-controller;
163 #interrupt-cells = <1>; 184 #interrupt-cells = <2>;
164 }; 185 };
165 186
166 gpio6: gpio@4805d000 { 187 gpio6: gpio@4805d000 {
@@ -171,7 +192,7 @@
171 gpio-controller; 192 gpio-controller;
172 #gpio-cells = <2>; 193 #gpio-cells = <2>;
173 interrupt-controller; 194 interrupt-controller;
174 #interrupt-cells = <1>; 195 #interrupt-cells = <2>;
175 }; 196 };
176 197
177 gpio7: gpio@48051000 { 198 gpio7: gpio@48051000 {
@@ -182,7 +203,7 @@
182 gpio-controller; 203 gpio-controller;
183 #gpio-cells = <2>; 204 #gpio-cells = <2>;
184 interrupt-controller; 205 interrupt-controller;
185 #interrupt-cells = <1>; 206 #interrupt-cells = <2>;
186 }; 207 };
187 208
188 gpio8: gpio@48053000 { 209 gpio8: gpio@48053000 {
@@ -193,7 +214,18 @@
193 gpio-controller; 214 gpio-controller;
194 #gpio-cells = <2>; 215 #gpio-cells = <2>;
195 interrupt-controller; 216 interrupt-controller;
196 #interrupt-cells = <1>; 217 #interrupt-cells = <2>;
218 };
219
220 gpmc: gpmc@50000000 {
221 compatible = "ti,omap4430-gpmc";
222 reg = <0x50000000 0x1000>;
223 #address-cells = <2>;
224 #size-cells = <1>;
225 interrupts = <0 20 0x4>;
226 gpmc,num-cs = <8>;
227 gpmc,num-waitpins = <4>;
228 ti,hwmods = "gpmc";
197 }; 229 };
198 230
199 i2c1: i2c@48070000 { 231 i2c1: i2c@48070000 {
@@ -241,6 +273,65 @@
241 ti,hwmods = "i2c5"; 273 ti,hwmods = "i2c5";
242 }; 274 };
243 275
276 mcspi1: spi@48098000 {
277 compatible = "ti,omap4-mcspi";
278 reg = <0x48098000 0x200>;
279 interrupts = <0 65 0x4>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 ti,hwmods = "mcspi1";
283 ti,spi-num-cs = <4>;
284 dmas = <&sdma 35>,
285 <&sdma 36>,
286 <&sdma 37>,
287 <&sdma 38>,
288 <&sdma 39>,
289 <&sdma 40>,
290 <&sdma 41>,
291 <&sdma 42>;
292 dma-names = "tx0", "rx0", "tx1", "rx1",
293 "tx2", "rx2", "tx3", "rx3";
294 };
295
296 mcspi2: spi@4809a000 {
297 compatible = "ti,omap4-mcspi";
298 reg = <0x4809a000 0x200>;
299 interrupts = <0 66 0x4>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 ti,hwmods = "mcspi2";
303 ti,spi-num-cs = <2>;
304 dmas = <&sdma 43>,
305 <&sdma 44>,
306 <&sdma 45>,
307 <&sdma 46>;
308 dma-names = "tx0", "rx0", "tx1", "rx1";
309 };
310
311 mcspi3: spi@480b8000 {
312 compatible = "ti,omap4-mcspi";
313 reg = <0x480b8000 0x200>;
314 interrupts = <0 91 0x4>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 ti,hwmods = "mcspi3";
318 ti,spi-num-cs = <2>;
319 dmas = <&sdma 15>, <&sdma 16>;
320 dma-names = "tx0", "rx0";
321 };
322
323 mcspi4: spi@480ba000 {
324 compatible = "ti,omap4-mcspi";
325 reg = <0x480ba000 0x200>;
326 interrupts = <0 48 0x4>;
327 #address-cells = <1>;
328 #size-cells = <0>;
329 ti,hwmods = "mcspi4";
330 ti,spi-num-cs = <1>;
331 dmas = <&sdma 70>, <&sdma 71>;
332 dma-names = "tx0", "rx0";
333 };
334
244 uart1: serial@4806a000 { 335 uart1: serial@4806a000 {
245 compatible = "ti,omap4-uart"; 336 compatible = "ti,omap4-uart";
246 reg = <0x4806a000 0x100>; 337 reg = <0x4806a000 0x100>;
@@ -296,6 +387,8 @@
296 ti,hwmods = "mmc1"; 387 ti,hwmods = "mmc1";
297 ti,dual-volt; 388 ti,dual-volt;
298 ti,needs-special-reset; 389 ti,needs-special-reset;
390 dmas = <&sdma 61>, <&sdma 62>;
391 dma-names = "tx", "rx";
299 }; 392 };
300 393
301 mmc2: mmc@480b4000 { 394 mmc2: mmc@480b4000 {
@@ -304,6 +397,8 @@
304 interrupts = <0 86 0x4>; 397 interrupts = <0 86 0x4>;
305 ti,hwmods = "mmc2"; 398 ti,hwmods = "mmc2";
306 ti,needs-special-reset; 399 ti,needs-special-reset;
400 dmas = <&sdma 47>, <&sdma 48>;
401 dma-names = "tx", "rx";
307 }; 402 };
308 403
309 mmc3: mmc@480ad000 { 404 mmc3: mmc@480ad000 {
@@ -312,6 +407,8 @@
312 interrupts = <0 94 0x4>; 407 interrupts = <0 94 0x4>;
313 ti,hwmods = "mmc3"; 408 ti,hwmods = "mmc3";
314 ti,needs-special-reset; 409 ti,needs-special-reset;
410 dmas = <&sdma 77>, <&sdma 78>;
411 dma-names = "tx", "rx";
315 }; 412 };
316 413
317 mmc4: mmc@480d1000 { 414 mmc4: mmc@480d1000 {
@@ -320,6 +417,8 @@
320 interrupts = <0 96 0x4>; 417 interrupts = <0 96 0x4>;
321 ti,hwmods = "mmc4"; 418 ti,hwmods = "mmc4";
322 ti,needs-special-reset; 419 ti,needs-special-reset;
420 dmas = <&sdma 57>, <&sdma 58>;
421 dma-names = "tx", "rx";
323 }; 422 };
324 423
325 mmc5: mmc@480d5000 { 424 mmc5: mmc@480d5000 {
@@ -328,10 +427,13 @@
328 interrupts = <0 59 0x4>; 427 interrupts = <0 59 0x4>;
329 ti,hwmods = "mmc5"; 428 ti,hwmods = "mmc5";
330 ti,needs-special-reset; 429 ti,needs-special-reset;
430 dmas = <&sdma 59>, <&sdma 60>;
431 dma-names = "tx", "rx";
331 }; 432 };
332 433
333 keypad: keypad@4ae1c000 { 434 keypad: keypad@4ae1c000 {
334 compatible = "ti,omap4-keypad"; 435 compatible = "ti,omap4-keypad";
436 reg = <0x4ae1c000 0x400>;
335 ti,hwmods = "kbd"; 437 ti,hwmods = "kbd";
336 }; 438 };
337 439
@@ -342,6 +444,9 @@
342 reg-names = "mpu", "dma"; 444 reg-names = "mpu", "dma";
343 interrupts = <0 112 0x4>; 445 interrupts = <0 112 0x4>;
344 ti,hwmods = "mcpdm"; 446 ti,hwmods = "mcpdm";
447 dmas = <&sdma 65>,
448 <&sdma 66>;
449 dma-names = "up_link", "dn_link";
345 }; 450 };
346 451
347 dmic: dmic@4012e000 { 452 dmic: dmic@4012e000 {
@@ -351,6 +456,8 @@
351 reg-names = "mpu", "dma"; 456 reg-names = "mpu", "dma";
352 interrupts = <0 114 0x4>; 457 interrupts = <0 114 0x4>;
353 ti,hwmods = "dmic"; 458 ti,hwmods = "dmic";
459 dmas = <&sdma 67>;
460 dma-names = "up_link";
354 }; 461 };
355 462
356 mcbsp1: mcbsp@40122000 { 463 mcbsp1: mcbsp@40122000 {
@@ -362,6 +469,9 @@
362 interrupt-names = "common"; 469 interrupt-names = "common";
363 ti,buffer-size = <128>; 470 ti,buffer-size = <128>;
364 ti,hwmods = "mcbsp1"; 471 ti,hwmods = "mcbsp1";
472 dmas = <&sdma 33>,
473 <&sdma 34>;
474 dma-names = "tx", "rx";
365 }; 475 };
366 476
367 mcbsp2: mcbsp@40124000 { 477 mcbsp2: mcbsp@40124000 {
@@ -373,6 +483,9 @@
373 interrupt-names = "common"; 483 interrupt-names = "common";
374 ti,buffer-size = <128>; 484 ti,buffer-size = <128>;
375 ti,hwmods = "mcbsp2"; 485 ti,hwmods = "mcbsp2";
486 dmas = <&sdma 17>,
487 <&sdma 18>;
488 dma-names = "tx", "rx";
376 }; 489 };
377 490
378 mcbsp3: mcbsp@40126000 { 491 mcbsp3: mcbsp@40126000 {
@@ -384,10 +497,13 @@
384 interrupt-names = "common"; 497 interrupt-names = "common";
385 ti,buffer-size = <128>; 498 ti,buffer-size = <128>;
386 ti,hwmods = "mcbsp3"; 499 ti,hwmods = "mcbsp3";
500 dmas = <&sdma 19>,
501 <&sdma 20>;
502 dma-names = "tx", "rx";
387 }; 503 };
388 504
389 timer1: timer@4ae18000 { 505 timer1: timer@4ae18000 {
390 compatible = "ti,omap2-timer"; 506 compatible = "ti,omap5430-timer";
391 reg = <0x4ae18000 0x80>; 507 reg = <0x4ae18000 0x80>;
392 interrupts = <0 37 0x4>; 508 interrupts = <0 37 0x4>;
393 ti,hwmods = "timer1"; 509 ti,hwmods = "timer1";
@@ -395,28 +511,28 @@
395 }; 511 };
396 512
397 timer2: timer@48032000 { 513 timer2: timer@48032000 {
398 compatible = "ti,omap2-timer"; 514 compatible = "ti,omap5430-timer";
399 reg = <0x48032000 0x80>; 515 reg = <0x48032000 0x80>;
400 interrupts = <0 38 0x4>; 516 interrupts = <0 38 0x4>;
401 ti,hwmods = "timer2"; 517 ti,hwmods = "timer2";
402 }; 518 };
403 519
404 timer3: timer@48034000 { 520 timer3: timer@48034000 {
405 compatible = "ti,omap2-timer"; 521 compatible = "ti,omap5430-timer";
406 reg = <0x48034000 0x80>; 522 reg = <0x48034000 0x80>;
407 interrupts = <0 39 0x4>; 523 interrupts = <0 39 0x4>;
408 ti,hwmods = "timer3"; 524 ti,hwmods = "timer3";
409 }; 525 };
410 526
411 timer4: timer@48036000 { 527 timer4: timer@48036000 {
412 compatible = "ti,omap2-timer"; 528 compatible = "ti,omap5430-timer";
413 reg = <0x48036000 0x80>; 529 reg = <0x48036000 0x80>;
414 interrupts = <0 40 0x4>; 530 interrupts = <0 40 0x4>;
415 ti,hwmods = "timer4"; 531 ti,hwmods = "timer4";
416 }; 532 };
417 533
418 timer5: timer@40138000 { 534 timer5: timer@40138000 {
419 compatible = "ti,omap2-timer"; 535 compatible = "ti,omap5430-timer";
420 reg = <0x40138000 0x80>, 536 reg = <0x40138000 0x80>,
421 <0x49038000 0x80>; 537 <0x49038000 0x80>;
422 interrupts = <0 41 0x4>; 538 interrupts = <0 41 0x4>;
@@ -425,7 +541,7 @@
425 }; 541 };
426 542
427 timer6: timer@4013a000 { 543 timer6: timer@4013a000 {
428 compatible = "ti,omap2-timer"; 544 compatible = "ti,omap5430-timer";
429 reg = <0x4013a000 0x80>, 545 reg = <0x4013a000 0x80>,
430 <0x4903a000 0x80>; 546 <0x4903a000 0x80>;
431 interrupts = <0 42 0x4>; 547 interrupts = <0 42 0x4>;
@@ -435,7 +551,7 @@
435 }; 551 };
436 552
437 timer7: timer@4013c000 { 553 timer7: timer@4013c000 {
438 compatible = "ti,omap2-timer"; 554 compatible = "ti,omap5430-timer";
439 reg = <0x4013c000 0x80>, 555 reg = <0x4013c000 0x80>,
440 <0x4903c000 0x80>; 556 <0x4903c000 0x80>;
441 interrupts = <0 43 0x4>; 557 interrupts = <0 43 0x4>;
@@ -444,7 +560,7 @@
444 }; 560 };
445 561
446 timer8: timer@4013e000 { 562 timer8: timer@4013e000 {
447 compatible = "ti,omap2-timer"; 563 compatible = "ti,omap5430-timer";
448 reg = <0x4013e000 0x80>, 564 reg = <0x4013e000 0x80>,
449 <0x4903e000 0x80>; 565 <0x4903e000 0x80>;
450 interrupts = <0 44 0x4>; 566 interrupts = <0 44 0x4>;
@@ -454,27 +570,34 @@
454 }; 570 };
455 571
456 timer9: timer@4803e000 { 572 timer9: timer@4803e000 {
457 compatible = "ti,omap2-timer"; 573 compatible = "ti,omap5430-timer";
458 reg = <0x4803e000 0x80>; 574 reg = <0x4803e000 0x80>;
459 interrupts = <0 45 0x4>; 575 interrupts = <0 45 0x4>;
460 ti,hwmods = "timer9"; 576 ti,hwmods = "timer9";
461 }; 577 };
462 578
463 timer10: timer@48086000 { 579 timer10: timer@48086000 {
464 compatible = "ti,omap2-timer"; 580 compatible = "ti,omap5430-timer";
465 reg = <0x48086000 0x80>; 581 reg = <0x48086000 0x80>;
466 interrupts = <0 46 0x4>; 582 interrupts = <0 46 0x4>;
467 ti,hwmods = "timer10"; 583 ti,hwmods = "timer10";
468 }; 584 };
469 585
470 timer11: timer@48088000 { 586 timer11: timer@48088000 {
471 compatible = "ti,omap2-timer"; 587 compatible = "ti,omap5430-timer";
472 reg = <0x48088000 0x80>; 588 reg = <0x48088000 0x80>;
473 interrupts = <0 47 0x4>; 589 interrupts = <0 47 0x4>;
474 ti,hwmods = "timer11"; 590 ti,hwmods = "timer11";
475 ti,timer-pwm; 591 ti,timer-pwm;
476 }; 592 };
477 593
594 wdt2: wdt@4ae14000 {
595 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
596 reg = <0x4ae14000 0x80>;
597 interrupts = <0 80 0x4>;
598 ti,hwmods = "wd_timer2";
599 };
600
478 emif1: emif@0x4c000000 { 601 emif1: emif@0x4c000000 {
479 compatible = "ti,emif-4d5"; 602 compatible = "ti,emif-4d5";
480 ti,hwmods = "emif1"; 603 ti,hwmods = "emif1";
@@ -496,5 +619,53 @@
496 hw-caps-ll-interface; 619 hw-caps-ll-interface;
497 hw-caps-temp-alert; 620 hw-caps-temp-alert;
498 }; 621 };
622
623 omap_control_usb: omap-control-usb@4a002300 {
624 compatible = "ti,omap-control-usb";
625 reg = <0x4a002300 0x4>,
626 <0x4a002370 0x4>;
627 reg-names = "control_dev_conf", "phy_power_usb";
628 ti,type = <2>;
629 };
630
631 omap_dwc3@4a020000 {
632 compatible = "ti,dwc3";
633 ti,hwmods = "usb_otg_ss";
634 reg = <0x4a020000 0x1000>;
635 interrupts = <0 93 4>;
636 #address-cells = <1>;
637 #size-cells = <1>;
638 utmi-mode = <2>;
639 ranges;
640 dwc3@4a030000 {
641 compatible = "synopsys,dwc3";
642 reg = <0x4a030000 0x1000>;
643 interrupts = <0 92 4>;
644 usb-phy = <&usb2_phy>, <&usb3_phy>;
645 tx-fifo-resize;
646 };
647 };
648
649 ocp2scp {
650 compatible = "ti,omap-ocp2scp";
651 #address-cells = <1>;
652 #size-cells = <1>;
653 ranges;
654 ti,hwmods = "ocp2scp1";
655 usb2_phy: usb2phy@4a084000 {
656 compatible = "ti,omap-usb2";
657 reg = <0x4a084000 0x7c>;
658 ctrl-module = <&omap_control_usb>;
659 };
660
661 usb3_phy: usb3phy@4a084400 {
662 compatible = "ti,omap-usb3";
663 reg = <0x4a084400 0x80>,
664 <0x4a084800 0x64>,
665 <0x4a084c00 0x40>;
666 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
667 ctrl-module = <&omap_control_usb>;
668 };
669 };
499 }; 670 };
500}; 671};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 616990dc92db..72c1f27af7f3 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -10,14 +10,835 @@
10 reg = <0x80000000 0x40000000>; 10 reg = <0x80000000 0x40000000>;
11 }; 11 };
12 12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 clk1_out_pw4 {
19 nvidia,pins = "clk1_out_pw4";
20 nvidia,function = "extperiph1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 nvidia,enable-input = <0>;
24 };
25 dap1_din_pn1 {
26 nvidia,pins = "dap1_din_pn1";
27 nvidia,function = "i2s0";
28 nvidia,pull = <0>;
29 nvidia,tristate = <1>;
30 nvidia,enable-input = <1>;
31 };
32 dap1_dout_pn2 {
33 nvidia,pins = "dap1_dout_pn2",
34 "dap1_fs_pn0",
35 "dap1_sclk_pn3";
36 nvidia,function = "i2s0";
37 nvidia,pull = <0>;
38 nvidia,tristate = <0>;
39 nvidia,enable-input = <1>;
40 };
41 dap2_din_pa4 {
42 nvidia,pins = "dap2_din_pa4";
43 nvidia,function = "i2s1";
44 nvidia,pull = <0>;
45 nvidia,tristate = <1>;
46 nvidia,enable-input = <1>;
47 };
48 dap2_dout_pa5 {
49 nvidia,pins = "dap2_dout_pa5",
50 "dap2_fs_pa2",
51 "dap2_sclk_pa3";
52 nvidia,function = "i2s1";
53 nvidia,pull = <0>;
54 nvidia,tristate = <0>;
55 nvidia,enable-input = <1>;
56 };
57 dap4_din_pp5 {
58 nvidia,pins = "dap4_din_pp5",
59 "dap4_dout_pp6",
60 "dap4_fs_pp4",
61 "dap4_sclk_pp7";
62 nvidia,function = "i2s3";
63 nvidia,pull = <0>;
64 nvidia,tristate = <0>;
65 nvidia,enable-input = <1>;
66 };
67 dvfs_pwm_px0 {
68 nvidia,pins = "dvfs_pwm_px0",
69 "dvfs_clk_px2";
70 nvidia,function = "cldvfs";
71 nvidia,pull = <0>;
72 nvidia,tristate = <0>;
73 nvidia,enable-input = <0>;
74 };
75 ulpi_clk_py0 {
76 nvidia,pins = "ulpi_clk_py0",
77 "ulpi_data0_po1",
78 "ulpi_data1_po2",
79 "ulpi_data2_po3",
80 "ulpi_data3_po4",
81 "ulpi_data4_po5",
82 "ulpi_data5_po6",
83 "ulpi_data6_po7",
84 "ulpi_data7_po0";
85 nvidia,function = "ulpi";
86 nvidia,pull = <0>;
87 nvidia,tristate = <0>;
88 nvidia,enable-input = <1>;
89 };
90 ulpi_dir_py1 {
91 nvidia,pins = "ulpi_dir_py1",
92 "ulpi_nxt_py2";
93 nvidia,function = "ulpi";
94 nvidia,pull = <0>;
95 nvidia,tristate = <1>;
96 nvidia,enable-input = <1>;
97 };
98 ulpi_stp_py3 {
99 nvidia,pins = "ulpi_stp_py3";
100 nvidia,function = "ulpi";
101 nvidia,pull = <0>;
102 nvidia,tristate = <0>;
103 nvidia,enable-input = <0>;
104 };
105 cam_i2c_scl_pbb1 {
106 nvidia,pins = "cam_i2c_scl_pbb1",
107 "cam_i2c_sda_pbb2";
108 nvidia,function = "i2c3";
109 nvidia,pull = <0>;
110 nvidia,tristate = <0>;
111 nvidia,enable-input = <1>;
112 nvidia,lock = <0>;
113 nvidia,open-drain = <0>;
114 };
115 cam_mclk_pcc0 {
116 nvidia,pins = "cam_mclk_pcc0",
117 "pbb0";
118 nvidia,function = "vi_alt3";
119 nvidia,pull = <0>;
120 nvidia,tristate = <0>;
121 nvidia,enable-input = <0>;
122 nvidia,lock = <0>;
123 };
124 gen2_i2c_scl_pt5 {
125 nvidia,pins = "gen2_i2c_scl_pt5",
126 "gen2_i2c_sda_pt6";
127 nvidia,function = "i2c2";
128 nvidia,pull = <0>;
129 nvidia,tristate = <0>;
130 nvidia,enable-input = <1>;
131 nvidia,lock = <0>;
132 nvidia,open-drain = <0>;
133 };
134 gmi_a16_pj7 {
135 nvidia,pins = "gmi_a16_pj7";
136 nvidia,function = "uartd";
137 nvidia,pull = <0>;
138 nvidia,tristate = <0>;
139 nvidia,enable-input = <0>;
140 };
141 gmi_a17_pb0 {
142 nvidia,pins = "gmi_a17_pb0",
143 "gmi_a18_pb1";
144 nvidia,function = "uartd";
145 nvidia,pull = <0>;
146 nvidia,tristate = <1>;
147 nvidia,enable-input = <1>;
148 };
149 gmi_a19_pk7 {
150 nvidia,pins = "gmi_a19_pk7";
151 nvidia,function = "uartd";
152 nvidia,pull = <0>;
153 nvidia,tristate = <0>;
154 nvidia,enable-input = <0>;
155 };
156 gmi_ad5_pg5 {
157 nvidia,pins = "gmi_ad5_pg5",
158 "gmi_cs6_n_pi3",
159 "gmi_wr_n_pi0";
160 nvidia,function = "spi4";
161 nvidia,pull = <0>;
162 nvidia,tristate = <0>;
163 nvidia,enable-input = <1>;
164 };
165 gmi_ad6_pg6 {
166 nvidia,pins = "gmi_ad6_pg6",
167 "gmi_ad7_pg7";
168 nvidia,function = "spi4";
169 nvidia,pull = <2>;
170 nvidia,tristate = <0>;
171 nvidia,enable-input = <1>;
172 };
173 gmi_ad12_ph4 {
174 nvidia,pins = "gmi_ad12_ph4";
175 nvidia,function = "rsvd4";
176 nvidia,pull = <0>;
177 nvidia,tristate = <0>;
178 nvidia,enable-input = <0>;
179 };
180 gmi_ad9_ph1 {
181 nvidia,pins = "gmi_ad9_ph1";
182 nvidia,function = "pwm1";
183 nvidia,pull = <0>;
184 nvidia,tristate = <0>;
185 nvidia,enable-input = <0>;
186 };
187 gmi_cs1_n_pj2 {
188 nvidia,pins = "gmi_cs1_n_pj2",
189 "gmi_oe_n_pi1";
190 nvidia,function = "soc";
191 nvidia,pull = <0>;
192 nvidia,tristate = <1>;
193 nvidia,enable-input = <1>;
194 };
195 clk2_out_pw5 {
196 nvidia,pins = "clk2_out_pw5";
197 nvidia,function = "extperiph2";
198 nvidia,pull = <0>;
199 nvidia,tristate = <0>;
200 nvidia,enable-input = <0>;
201 };
202 sdmmc1_clk_pz0 {
203 nvidia,pins = "sdmmc1_clk_pz0";
204 nvidia,function = "sdmmc1";
205 nvidia,pull = <0>;
206 nvidia,tristate = <0>;
207 nvidia,enable-input = <1>;
208 };
209 sdmmc1_cmd_pz1 {
210 nvidia,pins = "sdmmc1_cmd_pz1",
211 "sdmmc1_dat0_py7",
212 "sdmmc1_dat1_py6",
213 "sdmmc1_dat2_py5",
214 "sdmmc1_dat3_py4";
215 nvidia,function = "sdmmc1";
216 nvidia,pull = <2>;
217 nvidia,tristate = <0>;
218 nvidia,enable-input = <1>;
219 };
220 sdmmc1_wp_n_pv3 {
221 nvidia,pins = "sdmmc1_wp_n_pv3";
222 nvidia,function = "spi4";
223 nvidia,pull = <2>;
224 nvidia,tristate = <0>;
225 nvidia,enable-input = <0>;
226 };
227 sdmmc3_clk_pa6 {
228 nvidia,pins = "sdmmc3_clk_pa6";
229 nvidia,function = "sdmmc3";
230 nvidia,pull = <0>;
231 nvidia,tristate = <0>;
232 nvidia,enable-input = <1>;
233 };
234 sdmmc3_cmd_pa7 {
235 nvidia,pins = "sdmmc3_cmd_pa7",
236 "sdmmc3_dat0_pb7",
237 "sdmmc3_dat1_pb6",
238 "sdmmc3_dat2_pb5",
239 "sdmmc3_dat3_pb4",
240 "kb_col4_pq4",
241 "sdmmc3_clk_lb_out_pee4",
242 "sdmmc3_clk_lb_in_pee5";
243 nvidia,function = "sdmmc3";
244 nvidia,pull = <2>;
245 nvidia,tristate = <0>;
246 nvidia,enable-input = <1>;
247 };
248 sdmmc4_clk_pcc4 {
249 nvidia,pins = "sdmmc4_clk_pcc4";
250 nvidia,function = "sdmmc4";
251 nvidia,pull = <0>;
252 nvidia,tristate = <0>;
253 nvidia,enable-input = <1>;
254 };
255 sdmmc4_cmd_pt7 {
256 nvidia,pins = "sdmmc4_cmd_pt7",
257 "sdmmc4_dat0_paa0",
258 "sdmmc4_dat1_paa1",
259 "sdmmc4_dat2_paa2",
260 "sdmmc4_dat3_paa3",
261 "sdmmc4_dat4_paa4",
262 "sdmmc4_dat5_paa5",
263 "sdmmc4_dat6_paa6",
264 "sdmmc4_dat7_paa7";
265 nvidia,function = "sdmmc4";
266 nvidia,pull = <2>;
267 nvidia,tristate = <0>;
268 nvidia,enable-input = <1>;
269 };
270 clk_32k_out_pa0 {
271 nvidia,pins = "clk_32k_out_pa0";
272 nvidia,function = "blink";
273 nvidia,pull = <0>;
274 nvidia,tristate = <0>;
275 nvidia,enable-input = <0>;
276 };
277 kb_col0_pq0 {
278 nvidia,pins = "kb_col0_pq0",
279 "kb_col1_pq1",
280 "kb_col2_pq2",
281 "kb_row0_pr0",
282 "kb_row1_pr1",
283 "kb_row2_pr2";
284 nvidia,function = "kbc";
285 nvidia,pull = <2>;
286 nvidia,tristate = <0>;
287 nvidia,enable-input = <1>;
288 };
289 dap3_din_pp1 {
290 nvidia,pins = "dap3_din_pp1",
291 "dap3_sclk_pp3";
292 nvidia,function = "displayb";
293 nvidia,pull = <0>;
294 nvidia,tristate = <1>;
295 nvidia,enable-input = <0>;
296 };
297 pv0 {
298 nvidia,pins = "pv0";
299 nvidia,function = "rsvd4";
300 nvidia,pull = <0>;
301 nvidia,tristate = <1>;
302 nvidia,enable-input = <0>;
303 };
304 kb_row7_pr7 {
305 nvidia,pins = "kb_row7_pr7";
306 nvidia,function = "rsvd2";
307 nvidia,pull = <2>;
308 nvidia,tristate = <0>;
309 nvidia,enable-input = <1>;
310 };
311 kb_row10_ps2 {
312 nvidia,pins = "kb_row10_ps2";
313 nvidia,function = "uarta";
314 nvidia,pull = <0>;
315 nvidia,tristate = <1>;
316 nvidia,enable-input = <1>;
317 };
318 kb_row9_ps1 {
319 nvidia,pins = "kb_row9_ps1";
320 nvidia,function = "uarta";
321 nvidia,pull = <0>;
322 nvidia,tristate = <0>;
323 nvidia,enable-input = <0>;
324 };
325 pwr_i2c_scl_pz6 {
326 nvidia,pins = "pwr_i2c_scl_pz6",
327 "pwr_i2c_sda_pz7";
328 nvidia,function = "i2cpwr";
329 nvidia,pull = <0>;
330 nvidia,tristate = <0>;
331 nvidia,enable-input = <1>;
332 nvidia,lock = <0>;
333 nvidia,open-drain = <0>;
334 };
335 sys_clk_req_pz5 {
336 nvidia,pins = "sys_clk_req_pz5";
337 nvidia,function = "sysclk";
338 nvidia,pull = <0>;
339 nvidia,tristate = <0>;
340 nvidia,enable-input = <0>;
341 };
342 core_pwr_req {
343 nvidia,pins = "core_pwr_req";
344 nvidia,function = "pwron";
345 nvidia,pull = <0>;
346 nvidia,tristate = <0>;
347 nvidia,enable-input = <0>;
348 };
349 cpu_pwr_req {
350 nvidia,pins = "cpu_pwr_req";
351 nvidia,function = "cpu";
352 nvidia,pull = <0>;
353 nvidia,tristate = <0>;
354 nvidia,enable-input = <0>;
355 };
356 pwr_int_n {
357 nvidia,pins = "pwr_int_n";
358 nvidia,function = "pmi";
359 nvidia,pull = <0>;
360 nvidia,tristate = <1>;
361 nvidia,enable-input = <1>;
362 };
363 reset_out_n {
364 nvidia,pins = "reset_out_n";
365 nvidia,function = "reset_out_n";
366 nvidia,pull = <0>;
367 nvidia,tristate = <0>;
368 nvidia,enable-input = <0>;
369 };
370 clk3_out_pee0 {
371 nvidia,pins = "clk3_out_pee0";
372 nvidia,function = "extperiph3";
373 nvidia,pull = <0>;
374 nvidia,tristate = <0>;
375 nvidia,enable-input = <0>;
376 };
377 gen1_i2c_scl_pc4 {
378 nvidia,pins = "gen1_i2c_scl_pc4",
379 "gen1_i2c_sda_pc5";
380 nvidia,function = "i2c1";
381 nvidia,pull = <0>;
382 nvidia,tristate = <0>;
383 nvidia,enable-input = <1>;
384 nvidia,lock = <0>;
385 nvidia,open-drain = <0>;
386 };
387 uart2_cts_n_pj5 {
388 nvidia,pins = "uart2_cts_n_pj5";
389 nvidia,function = "uartb";
390 nvidia,pull = <0>;
391 nvidia,tristate = <1>;
392 nvidia,enable-input = <1>;
393 };
394 uart2_rts_n_pj6 {
395 nvidia,pins = "uart2_rts_n_pj6";
396 nvidia,function = "uartb";
397 nvidia,pull = <0>;
398 nvidia,tristate = <0>;
399 nvidia,enable-input = <0>;
400 };
401 uart2_rxd_pc3 {
402 nvidia,pins = "uart2_rxd_pc3";
403 nvidia,function = "irda";
404 nvidia,pull = <0>;
405 nvidia,tristate = <1>;
406 nvidia,enable-input = <1>;
407 };
408 uart2_txd_pc2 {
409 nvidia,pins = "uart2_txd_pc2";
410 nvidia,function = "irda";
411 nvidia,pull = <0>;
412 nvidia,tristate = <0>;
413 nvidia,enable-input = <0>;
414 };
415 uart3_cts_n_pa1 {
416 nvidia,pins = "uart3_cts_n_pa1",
417 "uart3_rxd_pw7";
418 nvidia,function = "uartc";
419 nvidia,pull = <0>;
420 nvidia,tristate = <1>;
421 nvidia,enable-input = <1>;
422 };
423 uart3_rts_n_pc0 {
424 nvidia,pins = "uart3_rts_n_pc0",
425 "uart3_txd_pw6";
426 nvidia,function = "uartc";
427 nvidia,pull = <0>;
428 nvidia,tristate = <0>;
429 nvidia,enable-input = <0>;
430 };
431 owr {
432 nvidia,pins = "owr";
433 nvidia,function = "owr";
434 nvidia,pull = <0>;
435 nvidia,tristate = <0>;
436 nvidia,enable-input = <1>;
437 };
438 hdmi_cec_pee3 {
439 nvidia,pins = "hdmi_cec_pee3";
440 nvidia,function = "cec";
441 nvidia,pull = <0>;
442 nvidia,tristate = <0>;
443 nvidia,enable-input = <1>;
444 nvidia,lock = <0>;
445 nvidia,open-drain = <0>;
446 };
447 ddc_scl_pv4 {
448 nvidia,pins = "ddc_scl_pv4",
449 "ddc_sda_pv5";
450 nvidia,function = "i2c4";
451 nvidia,pull = <0>;
452 nvidia,tristate = <0>;
453 nvidia,enable-input = <1>;
454 nvidia,lock = <0>;
455 nvidia,rcv-sel = <1>;
456 };
457 spdif_in_pk6 {
458 nvidia,pins = "spdif_in_pk6";
459 nvidia,function = "usb";
460 nvidia,pull = <2>;
461 nvidia,tristate = <0>;
462 nvidia,enable-input = <1>;
463 nvidia,lock = <0>;
464 };
465 usb_vbus_en0_pn4 {
466 nvidia,pins = "usb_vbus_en0_pn4";
467 nvidia,function = "usb";
468 nvidia,pull = <2>;
469 nvidia,tristate = <0>;
470 nvidia,enable-input = <1>;
471 nvidia,lock = <0>;
472 nvidia,open-drain = <1>;
473 };
474 gpio_x6_aud_px6 {
475 nvidia,pins = "gpio_x6_aud_px6";
476 nvidia,function = "spi6";
477 nvidia,pull = <2>;
478 nvidia,tristate = <1>;
479 nvidia,enable-input = <1>;
480 };
481 gpio_x4_aud_px4 {
482 nvidia,pins = "gpio_x4_aud_px4",
483 "gpio_x7_aud_px7";
484 nvidia,function = "rsvd1";
485 nvidia,pull = <1>;
486 nvidia,tristate = <0>;
487 nvidia,enable-input = <0>;
488 };
489 gpio_x5_aud_px5 {
490 nvidia,pins = "gpio_x5_aud_px5";
491 nvidia,function = "rsvd1";
492 nvidia,pull = <2>;
493 nvidia,tristate = <0>;
494 nvidia,enable-input = <1>;
495 };
496 gpio_w2_aud_pw2 {
497 nvidia,pins = "gpio_w2_aud_pw2";
498 nvidia,function = "rsvd2";
499 nvidia,pull = <2>;
500 nvidia,tristate = <0>;
501 nvidia,enable-input = <1>;
502 };
503 gpio_w3_aud_pw3 {
504 nvidia,pins = "gpio_w3_aud_pw3";
505 nvidia,function = "spi6";
506 nvidia,pull = <2>;
507 nvidia,tristate = <0>;
508 nvidia,enable-input = <1>;
509 };
510 gpio_x1_aud_px1 {
511 nvidia,pins = "gpio_x1_aud_px1";
512 nvidia,function = "rsvd4";
513 nvidia,pull = <1>;
514 nvidia,tristate = <0>;
515 nvidia,enable-input = <1>;
516 };
517 gpio_x3_aud_px3 {
518 nvidia,pins = "gpio_x3_aud_px3";
519 nvidia,function = "rsvd4";
520 nvidia,pull = <2>;
521 nvidia,tristate = <0>;
522 nvidia,enable-input = <1>;
523 };
524 dap3_fs_pp0 {
525 nvidia,pins = "dap3_fs_pp0";
526 nvidia,function = "i2s2";
527 nvidia,pull = <1>;
528 nvidia,tristate = <0>;
529 nvidia,enable-input = <0>;
530 };
531 dap3_dout_pp2 {
532 nvidia,pins = "dap3_dout_pp2";
533 nvidia,function = "i2s2";
534 nvidia,pull = <1>;
535 nvidia,tristate = <0>;
536 nvidia,enable-input = <0>;
537 };
538 pv1 {
539 nvidia,pins = "pv1";
540 nvidia,function = "rsvd1";
541 nvidia,pull = <0>;
542 nvidia,tristate = <0>;
543 nvidia,enable-input = <1>;
544 };
545 pbb3 {
546 nvidia,pins = "pbb3",
547 "pbb5",
548 "pbb6",
549 "pbb7";
550 nvidia,function = "rsvd4";
551 nvidia,pull = <1>;
552 nvidia,tristate = <0>;
553 nvidia,enable-input = <0>;
554 };
555 pcc1 {
556 nvidia,pins = "pcc1",
557 "pcc2";
558 nvidia,function = "rsvd4";
559 nvidia,pull = <1>;
560 nvidia,tristate = <0>;
561 nvidia,enable-input = <1>;
562 };
563 gmi_ad0_pg0 {
564 nvidia,pins = "gmi_ad0_pg0",
565 "gmi_ad1_pg1";
566 nvidia,function = "gmi";
567 nvidia,pull = <0>;
568 nvidia,tristate = <0>;
569 nvidia,enable-input = <0>;
570 };
571 gmi_ad10_ph2 {
572 nvidia,pins = "gmi_ad10_ph2",
573 "gmi_ad11_ph3",
574 "gmi_ad13_ph5",
575 "gmi_ad8_ph0",
576 "gmi_clk_pk1";
577 nvidia,function = "gmi";
578 nvidia,pull = <1>;
579 nvidia,tristate = <0>;
580 nvidia,enable-input = <0>;
581 };
582 gmi_ad2_pg2 {
583 nvidia,pins = "gmi_ad2_pg2",
584 "gmi_ad3_pg3";
585 nvidia,function = "gmi";
586 nvidia,pull = <0>;
587 nvidia,tristate = <0>;
588 nvidia,enable-input = <1>;
589 };
590 gmi_adv_n_pk0 {
591 nvidia,pins = "gmi_adv_n_pk0",
592 "gmi_cs0_n_pj0",
593 "gmi_cs2_n_pk3",
594 "gmi_cs4_n_pk2",
595 "gmi_cs7_n_pi6",
596 "gmi_dqs_p_pj3",
597 "gmi_iordy_pi5",
598 "gmi_wp_n_pc7";
599 nvidia,function = "gmi";
600 nvidia,pull = <2>;
601 nvidia,tristate = <0>;
602 nvidia,enable-input = <1>;
603 };
604 gmi_cs3_n_pk4 {
605 nvidia,pins = "gmi_cs3_n_pk4";
606 nvidia,function = "gmi";
607 nvidia,pull = <2>;
608 nvidia,tristate = <0>;
609 nvidia,enable-input = <0>;
610 };
611 clk2_req_pcc5 {
612 nvidia,pins = "clk2_req_pcc5";
613 nvidia,function = "rsvd4";
614 nvidia,pull = <0>;
615 nvidia,tristate = <0>;
616 nvidia,enable-input = <0>;
617 };
618 kb_col3_pq3 {
619 nvidia,pins = "kb_col3_pq3",
620 "kb_col6_pq6",
621 "kb_col7_pq7";
622 nvidia,function = "kbc";
623 nvidia,pull = <2>;
624 nvidia,tristate = <0>;
625 nvidia,enable-input = <0>;
626 };
627 kb_col5_pq5 {
628 nvidia,pins = "kb_col5_pq5";
629 nvidia,function = "kbc";
630 nvidia,pull = <2>;
631 nvidia,tristate = <0>;
632 nvidia,enable-input = <1>;
633 };
634 kb_row3_pr3 {
635 nvidia,pins = "kb_row3_pr3",
636 "kb_row4_pr4",
637 "kb_row6_pr6",
638 "kb_row8_ps0";
639 nvidia,function = "kbc";
640 nvidia,pull = <1>;
641 nvidia,tristate = <0>;
642 nvidia,enable-input = <1>;
643 };
644 clk3_req_pee1 {
645 nvidia,pins = "clk3_req_pee1";
646 nvidia,function = "rsvd4";
647 nvidia,pull = <0>;
648 nvidia,tristate = <0>;
649 nvidia,enable-input = <0>;
650 };
651 pu4 {
652 nvidia,pins = "pu4";
653 nvidia,function = "displayb";
654 nvidia,pull = <0>;
655 nvidia,tristate = <0>;
656 nvidia,enable-input = <0>;
657 };
658 pu5 {
659 nvidia,pins = "pu5",
660 "pu6";
661 nvidia,function = "displayb";
662 nvidia,pull = <0>;
663 nvidia,tristate = <0>;
664 nvidia,enable-input = <1>;
665 };
666 hdmi_int_pn7 {
667 nvidia,pins = "hdmi_int_pn7";
668 nvidia,function = "rsvd1";
669 nvidia,pull = <1>;
670 nvidia,tristate = <0>;
671 nvidia,enable-input = <1>;
672 };
673 clk1_req_pee2 {
674 nvidia,pins = "clk1_req_pee2",
675 "usb_vbus_en1_pn5";
676 nvidia,function = "rsvd4";
677 nvidia,pull = <1>;
678 nvidia,tristate = <1>;
679 nvidia,enable-input = <0>;
680 };
681
682 drive_sdio1 {
683 nvidia,pins = "drive_sdio1";
684 nvidia,high-speed-mode = <1>;
685 nvidia,schmitt = <0>;
686 nvidia,low-power-mode = <3>;
687 nvidia,pull-down-strength = <36>;
688 nvidia,pull-up-strength = <20>;
689 nvidia,slew-rate-rising = <2>;
690 nvidia,slew-rate-falling = <2>;
691 };
692 drive_sdio3 {
693 nvidia,pins = "drive_sdio3";
694 nvidia,high-speed-mode = <1>;
695 nvidia,schmitt = <0>;
696 nvidia,low-power-mode = <3>;
697 nvidia,pull-down-strength = <22>;
698 nvidia,pull-up-strength = <36>;
699 nvidia,slew-rate-rising = <0>;
700 nvidia,slew-rate-falling = <0>;
701 };
702 drive_gma {
703 nvidia,pins = "drive_gma";
704 nvidia,high-speed-mode = <1>;
705 nvidia,schmitt = <0>;
706 nvidia,low-power-mode = <3>;
707 nvidia,pull-down-strength = <2>;
708 nvidia,pull-up-strength = <1>;
709 nvidia,slew-rate-rising = <0>;
710 nvidia,slew-rate-falling = <0>;
711 nvidia,drive-type = <1>;
712 };
713 };
714 };
715
13 serial@70006300 { 716 serial@70006300 {
14 status = "okay"; 717 status = "okay";
15 }; 718 };
16 719
720 i2c@7000c000 {
721 status = "okay";
722 clock-frequency = <100000>;
723
724 battery: smart-battery {
725 compatible = "ti,bq20z45", "sbs,sbs-battery";
726 reg = <0xb>;
727 battery-name = "battery";
728 sbs,i2c-retry-count = <2>;
729 sbs,poll-retry-count = <100>;
730 };
731 };
732
733 i2c@7000d000 {
734 status = "okay";
735 clock-frequency = <400000>;
736
737 tps51632 {
738 compatible = "ti,tps51632";
739 reg = <0x43>;
740 regulator-name = "vdd-cpu";
741 regulator-min-microvolt = <500000>;
742 regulator-max-microvolt = <1520000>;
743 regulator-boot-on;
744 regulator-always-on;
745 };
746
747 tps65090 {
748 compatible = "ti,tps65090";
749 reg = <0x48>;
750 interrupt-parent = <&gpio>;
751 interrupts = <72 0x04>; /* gpio PJ0 */
752
753 vsys1-supply = <&vdd_ac_bat_reg>;
754 vsys2-supply = <&vdd_ac_bat_reg>;
755 vsys3-supply = <&vdd_ac_bat_reg>;
756 infet1-supply = <&vdd_ac_bat_reg>;
757 infet2-supply = <&vdd_ac_bat_reg>;
758 infet3-supply = <&tps65090_dcdc2_reg>;
759 infet4-supply = <&tps65090_dcdc2_reg>;
760 infet5-supply = <&tps65090_dcdc2_reg>;
761 infet6-supply = <&tps65090_dcdc2_reg>;
762 infet7-supply = <&tps65090_dcdc2_reg>;
763 vsys-l1-supply = <&vdd_ac_bat_reg>;
764 vsys-l2-supply = <&vdd_ac_bat_reg>;
765
766 regulators {
767 tps65090_dcdc1_reg: dcdc1 {
768 regulator-name = "vdd-sys-5v0";
769 regulator-always-on;
770 regulator-boot-on;
771 };
772
773 tps65090_dcdc2_reg: dcdc2 {
774 regulator-name = "vdd-sys-3v3";
775 regulator-always-on;
776 regulator-boot-on;
777 };
778
779 dcdc3 {
780 regulator-name = "vdd-ao";
781 regulator-always-on;
782 regulator-boot-on;
783 };
784
785 fet1 {
786 regulator-name = "vdd-lcd-bl";
787 };
788
789 fet3 {
790 regulator-name = "vdd-modem-3v3";
791 };
792
793 fet4 {
794 regulator-name = "avdd-lcd";
795 };
796
797 fet5 {
798 regulator-name = "vdd-lvds";
799 };
800
801 fet6 {
802 regulator-name = "vdd-sd-slot";
803 regulator-always-on;
804 regulator-boot-on;
805 };
806
807 fet7 {
808 regulator-name = "vdd-com-3v3";
809 };
810
811 ldo1 {
812 regulator-name = "vdd-sby-5v0";
813 regulator-always-on;
814 regulator-boot-on;
815 };
816
817 ldo2 {
818 regulator-name = "vdd-sby-3v3";
819 regulator-always-on;
820 regulator-boot-on;
821 };
822 };
823 };
824 };
825
17 pmc { 826 pmc {
18 nvidia,invert-interrupt; 827 nvidia,invert-interrupt;
19 }; 828 };
20 829
830 sdhci@78000400 {
831 cd-gpios = <&gpio 170 1>; /* gpio PV2 */
832 bus-width = <4>;
833 status = "okay";
834 };
835
836 sdhci@78000600 {
837 bus-width = <8>;
838 status = "okay";
839 non-removable;
840 };
841
21 clocks { 842 clocks {
22 compatible = "simple-bus"; 843 compatible = "simple-bus";
23 #address-cells = <1>; 844 #address-cells = <1>;
@@ -30,4 +851,74 @@
30 clock-frequency = <32768>; 851 clock-frequency = <32768>;
31 }; 852 };
32 }; 853 };
854
855 regulators {
856 compatible = "simple-bus";
857 #address-cells = <1>;
858 #size-cells = <0>;
859
860 vdd_ac_bat_reg: regulator@0 {
861 compatible = "regulator-fixed";
862 reg = <0>;
863 regulator-name = "vdd_ac_bat";
864 regulator-min-microvolt = <5000000>;
865 regulator-max-microvolt = <5000000>;
866 regulator-always-on;
867 };
868
869 dvdd_ts_reg: regulator@1 {
870 compatible = "regulator-fixed";
871 reg = <1>;
872 regulator-name = "dvdd_ts";
873 regulator-min-microvolt = <1800000>;
874 regulator-max-microvolt = <1800000>;
875 enable-active-high;
876 gpio = <&gpio 61 0>; /* GPIO PH5 */
877 };
878
879 lcd_bl_en_reg: regulator@2 {
880 compatible = "regulator-fixed";
881 reg = <2>;
882 regulator-name = "lcd_bl_en";
883 regulator-min-microvolt = <5000000>;
884 regulator-max-microvolt = <5000000>;
885 enable-active-high;
886 gpio = <&gpio 58 0>; /* GPIO PH2 */
887 };
888
889 usb1_vbus_reg: regulator@3 {
890 compatible = "regulator-fixed";
891 reg = <3>;
892 regulator-name = "usb1_vbus";
893 regulator-min-microvolt = <5000000>;
894 regulator-max-microvolt = <5000000>;
895 enable-active-high;
896 gpio = <&gpio 108 0>; /* GPIO PN4 */
897 gpio-open-drain;
898 vin-supply = <&tps65090_dcdc1_reg>;
899 };
900
901 usb3_vbus_reg: regulator@4 {
902 compatible = "regulator-fixed";
903 reg = <4>;
904 regulator-name = "usb2_vbus";
905 regulator-min-microvolt = <5000000>;
906 regulator-max-microvolt = <5000000>;
907 enable-active-high;
908 gpio = <&gpio 86 0>; /* GPIO PK6 */
909 gpio-open-drain;
910 vin-supply = <&tps65090_dcdc1_reg>;
911 };
912
913 vdd_hdmi_reg: regulator@5 {
914 compatible = "regulator-fixed";
915 reg = <5>;
916 regulator-name = "vdd_hdmi_5v0";
917 regulator-min-microvolt = <5000000>;
918 regulator-max-microvolt = <5000000>;
919 enable-active-high;
920 gpio = <&gpio 81 0>; /* GPIO PK1 */
921 vin-supply = <&tps65090_dcdc1_reg>;
922 };
923 };
33}; 924};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index c1110a9b2a91..629415ffd8dc 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -4,6 +4,13 @@
4 compatible = "nvidia,tegra114"; 4 compatible = "nvidia,tegra114";
5 interrupt-parent = <&gic>; 5 interrupt-parent = <&gic>;
6 6
7 aliases {
8 serial0 = &uarta;
9 serial1 = &uartb;
10 serial2 = &uartc;
11 serial3 = &uartd;
12 };
13
7 gic: interrupt-controller { 14 gic: interrupt-controller {
8 compatible = "arm,cortex-a15-gic"; 15 compatible = "arm,cortex-a15-gic";
9 #interrupt-cells = <3>; 16 #interrupt-cells = <3>;
@@ -33,6 +40,44 @@
33 #clock-cells = <1>; 40 #clock-cells = <1>;
34 }; 41 };
35 42
43 apbdma: dma {
44 compatible = "nvidia,tegra114-apbdma";
45 reg = <0x6000a000 0x1400>;
46 interrupts = <0 104 0x04
47 0 105 0x04
48 0 106 0x04
49 0 107 0x04
50 0 108 0x04
51 0 109 0x04
52 0 110 0x04
53 0 111 0x04
54 0 112 0x04
55 0 113 0x04
56 0 114 0x04
57 0 115 0x04
58 0 116 0x04
59 0 117 0x04
60 0 118 0x04
61 0 119 0x04
62 0 128 0x04
63 0 129 0x04
64 0 130 0x04
65 0 131 0x04
66 0 132 0x04
67 0 133 0x04
68 0 134 0x04
69 0 135 0x04
70 0 136 0x04
71 0 137 0x04
72 0 138 0x04
73 0 139 0x04
74 0 140 0x04
75 0 141 0x04
76 0 142 0x04
77 0 143 0x04>;
78 clocks = <&tegra_car 34>;
79 };
80
36 ahb: ahb { 81 ahb: ahb {
37 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; 82 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
38 reg = <0x6000c004 0x14c>; 83 reg = <0x6000c004 0x14c>;
@@ -61,42 +106,189 @@
61 0x70003000 0x40c>; /* Mux registers */ 106 0x70003000 0x40c>; /* Mux registers */
62 }; 107 };
63 108
64 serial@70006000 { 109 /*
110 * There are two serial driver i.e. 8250 based simple serial
111 * driver and APB DMA based serial driver for higher baudrate
112 * and performace. To enable the 8250 based driver, the compatible
113 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
114 * the APB DMA based serial driver, the comptible is
115 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
116 */
117 uarta: serial@70006000 {
65 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 118 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
66 reg = <0x70006000 0x40>; 119 reg = <0x70006000 0x40>;
67 reg-shift = <2>; 120 reg-shift = <2>;
68 interrupts = <0 36 0x04>; 121 interrupts = <0 36 0x04>;
122 nvidia,dma-request-selector = <&apbdma 8>;
69 status = "disabled"; 123 status = "disabled";
70 clocks = <&tegra_car 6>; 124 clocks = <&tegra_car 6>;
71 }; 125 };
72 126
73 serial@70006040 { 127 uartb: serial@70006040 {
74 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 128 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
75 reg = <0x70006040 0x40>; 129 reg = <0x70006040 0x40>;
76 reg-shift = <2>; 130 reg-shift = <2>;
77 interrupts = <0 37 0x04>; 131 interrupts = <0 37 0x04>;
132 nvidia,dma-request-selector = <&apbdma 9>;
78 status = "disabled"; 133 status = "disabled";
79 clocks = <&tegra_car 192>; 134 clocks = <&tegra_car 192>;
80 }; 135 };
81 136
82 serial@70006200 { 137 uartc: serial@70006200 {
83 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 138 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
84 reg = <0x70006200 0x100>; 139 reg = <0x70006200 0x100>;
85 reg-shift = <2>; 140 reg-shift = <2>;
86 interrupts = <0 46 0x04>; 141 interrupts = <0 46 0x04>;
142 nvidia,dma-request-selector = <&apbdma 10>;
87 status = "disabled"; 143 status = "disabled";
88 clocks = <&tegra_car 55>; 144 clocks = <&tegra_car 55>;
89 }; 145 };
90 146
91 serial@70006300 { 147 uartd: serial@70006300 {
92 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 148 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
93 reg = <0x70006300 0x100>; 149 reg = <0x70006300 0x100>;
94 reg-shift = <2>; 150 reg-shift = <2>;
95 interrupts = <0 90 0x04>; 151 interrupts = <0 90 0x04>;
152 nvidia,dma-request-selector = <&apbdma 19>;
96 status = "disabled"; 153 status = "disabled";
97 clocks = <&tegra_car 65>; 154 clocks = <&tegra_car 65>;
98 }; 155 };
99 156
157 pwm: pwm {
158 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
159 reg = <0x7000a000 0x100>;
160 #pwm-cells = <2>;
161 clocks = <&tegra_car 17>;
162 status = "disabled";
163 };
164
165 i2c@7000c000 {
166 compatible = "nvidia,tegra114-i2c";
167 reg = <0x7000c000 0x100>;
168 interrupts = <0 38 0x04>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171 clocks = <&tegra_car 12>;
172 clock-names = "div-clk";
173 status = "disabled";
174 };
175
176 i2c@7000c400 {
177 compatible = "nvidia,tegra114-i2c";
178 reg = <0x7000c400 0x100>;
179 interrupts = <0 84 0x04>;
180 #address-cells = <1>;
181 #size-cells = <0>;
182 clocks = <&tegra_car 54>;
183 clock-names = "div-clk";
184 status = "disabled";
185 };
186
187 i2c@7000c500 {
188 compatible = "nvidia,tegra114-i2c";
189 reg = <0x7000c500 0x100>;
190 interrupts = <0 92 0x04>;
191 #address-cells = <1>;
192 #size-cells = <0>;
193 clocks = <&tegra_car 67>;
194 clock-names = "div-clk";
195 status = "disabled";
196 };
197
198 i2c@7000c700 {
199 compatible = "nvidia,tegra114-i2c";
200 reg = <0x7000c700 0x100>;
201 interrupts = <0 120 0x04>;
202 #address-cells = <1>;
203 #size-cells = <0>;
204 clocks = <&tegra_car 103>;
205 clock-names = "div-clk";
206 status = "disabled";
207 };
208
209 i2c@7000d000 {
210 compatible = "nvidia,tegra114-i2c";
211 reg = <0x7000d000 0x100>;
212 interrupts = <0 53 0x04>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 clocks = <&tegra_car 47>;
216 clock-names = "div-clk";
217 status = "disabled";
218 };
219
220 spi@7000d400 {
221 compatible = "nvidia,tegra114-spi";
222 reg = <0x7000d400 0x200>;
223 interrupts = <0 59 0x04>;
224 nvidia,dma-request-selector = <&apbdma 15>;
225 #address-cells = <1>;
226 #size-cells = <0>;
227 clocks = <&tegra_car 41>;
228 clock-names = "spi";
229 status = "disabled";
230 };
231
232 spi@7000d600 {
233 compatible = "nvidia,tegra114-spi";
234 reg = <0x7000d600 0x200>;
235 interrupts = <0 82 0x04>;
236 nvidia,dma-request-selector = <&apbdma 16>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 clocks = <&tegra_car 44>;
240 clock-names = "spi";
241 status = "disabled";
242 };
243
244 spi@7000d800 {
245 compatible = "nvidia,tegra114-spi";
246 reg = <0x7000d800 0x200>;
247 interrupts = <0 83 0x04>;
248 nvidia,dma-request-selector = <&apbdma 17>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251 clocks = <&tegra_car 46>;
252 clock-names = "spi";
253 status = "disabled";
254 };
255
256 spi@7000da00 {
257 compatible = "nvidia,tegra114-spi";
258 reg = <0x7000da00 0x200>;
259 interrupts = <0 93 0x04>;
260 nvidia,dma-request-selector = <&apbdma 18>;
261 #address-cells = <1>;
262 #size-cells = <0>;
263 clocks = <&tegra_car 68>;
264 clock-names = "spi";
265 status = "disabled";
266 };
267
268 spi@7000dc00 {
269 compatible = "nvidia,tegra114-spi";
270 reg = <0x7000dc00 0x200>;
271 interrupts = <0 94 0x04>;
272 nvidia,dma-request-selector = <&apbdma 27>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 clocks = <&tegra_car 104>;
276 clock-names = "spi";
277 status = "disabled";
278 };
279
280 spi@7000de00 {
281 compatible = "nvidia,tegra114-spi";
282 reg = <0x7000de00 0x200>;
283 interrupts = <0 79 0x04>;
284 nvidia,dma-request-selector = <&apbdma 28>;
285 #address-cells = <1>;
286 #size-cells = <0>;
287 clocks = <&tegra_car 105>;
288 clock-names = "spi";
289 status = "disabled";
290 };
291
100 rtc { 292 rtc {
101 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 293 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
102 reg = <0x7000e000 0x100>; 294 reg = <0x7000e000 0x100>;
@@ -104,6 +296,14 @@
104 clocks = <&tegra_car 4>; 296 clocks = <&tegra_car 4>;
105 }; 297 };
106 298
299 kbc {
300 compatible = "nvidia,tegra114-kbc";
301 reg = <0x7000e200 0x100>;
302 interrupts = <0 85 0x04>;
303 clocks = <&tegra_car 36>;
304 status = "disabled";
305 };
306
107 pmc { 307 pmc {
108 compatible = "nvidia,tegra114-pmc"; 308 compatible = "nvidia,tegra114-pmc";
109 reg = <0x7000e400 0x400>; 309 reg = <0x7000e400 0x400>;
@@ -122,6 +322,38 @@
122 nvidia,ahb = <&ahb>; 322 nvidia,ahb = <&ahb>;
123 }; 323 };
124 324
325 sdhci@78000000 {
326 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
327 reg = <0x78000000 0x200>;
328 interrupts = <0 14 0x04>;
329 clocks = <&tegra_car 14>;
330 status = "disable";
331 };
332
333 sdhci@78000200 {
334 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
335 reg = <0x78000200 0x200>;
336 interrupts = <0 15 0x04>;
337 clocks = <&tegra_car 9>;
338 status = "disable";
339 };
340
341 sdhci@78000400 {
342 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
343 reg = <0x78000400 0x200>;
344 interrupts = <0 19 0x04>;
345 clocks = <&tegra_car 69>;
346 status = "disable";
347 };
348
349 sdhci@78000600 {
350 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
351 reg = <0x78000600 0x200>;
352 interrupts = <0 31 0x04>;
353 clocks = <&tegra_car 15>;
354 status = "disable";
355 };
356
125 cpus { 357 cpus {
126 #address-cells = <1>; 358 #address-cells = <1>;
127 #size-cells = <0>; 359 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 4e3afdef28a8..a573b94b7c93 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -361,6 +361,15 @@
361 }; 361 };
362 }; 362 };
363 363
364 pmc {
365 nvidia,suspend-mode = <2>;
366 nvidia,cpu-pwr-good-time = <5000>;
367 nvidia,cpu-pwr-off-time = <5000>;
368 nvidia,core-pwr-good-time = <3845 3845>;
369 nvidia,core-pwr-off-time = <3875>;
370 nvidia,sys-clock-req-active-high;
371 };
372
364 memory-controller@7000f400 { 373 memory-controller@7000f400 {
365 emc-table@83250 { 374 emc-table@83250 {
366 reg = <83250>; 375 reg = <83250>;
@@ -473,6 +482,9 @@
473 "Mic", "MIC1"; 482 "Mic", "MIC1";
474 483
475 nvidia,ac97-controller = <&ac97>; 484 nvidia,ac97-controller = <&ac97>;
485
486 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
487 clock-names = "pll_a", "pll_a_out0", "mclk";
476 }; 488 };
477 489
478 regulators { 490 regulators {
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index ae9d5a20834e..e7d5de4e00b9 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -416,6 +416,12 @@
416 416
417 pmc { 417 pmc {
418 nvidia,invert-interrupt; 418 nvidia,invert-interrupt;
419 nvidia,suspend-mode = <2>;
420 nvidia,cpu-pwr-good-time = <5000>;
421 nvidia,cpu-pwr-off-time = <5000>;
422 nvidia,core-pwr-good-time = <3845 3845>;
423 nvidia,core-pwr-off-time = <3875>;
424 nvidia,sys-clock-req-active-high;
419 }; 425 };
420 426
421 usb@c5000000 { 427 usb@c5000000 {
@@ -464,6 +470,17 @@
464 }; 470 };
465 }; 471 };
466 472
473 gpio-keys {
474 compatible = "gpio-keys";
475
476 power {
477 label = "Power";
478 gpios = <&gpio 170 1>; /* gpio PV2, active low */
479 linux,code = <116>; /* KEY_POWER */
480 gpio-key,wakeup;
481 };
482 };
483
467 kbc { 484 kbc {
468 status = "okay"; 485 status = "okay";
469 nvidia,debounce-delay-ms = <2>; 486 nvidia,debounce-delay-ms = <2>;
@@ -669,5 +686,8 @@
669 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 686 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
670 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ 687 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
671 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 688 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
689
690 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
691 clock-names = "pll_a", "pll_a_out0", "mclk";
672 }; 692 };
673}; 693};
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index a2d6d6541f83..ace23437da89 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -6,6 +6,10 @@
6 model = "Avionic Design Medcom-Wide board"; 6 model = "Avionic Design Medcom-Wide board";
7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
8 8
9 pwm {
10 status = "okay";
11 };
12
9 i2c@7000c000 { 13 i2c@7000c000 {
10 wm8903: wm8903@1a { 14 wm8903: wm8903@1a {
11 compatible = "wlf,wm8903"; 15 compatible = "wlf,wm8903";
@@ -54,5 +58,8 @@
54 58
55 nvidia,spkr-en-gpios = <&wm8903 2 0>; 59 nvidia,spkr-en-gpios = <&wm8903 2 0>;
56 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 60 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
61
62 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
63 clock-names = "pll_a", "pll_a_out0", "mclk";
57 }; 64 };
58}; 65};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index fd60940e4063..e3e0c9977df4 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -415,6 +415,12 @@
415 415
416 pmc { 416 pmc {
417 nvidia,invert-interrupt; 417 nvidia,invert-interrupt;
418 nvidia,suspend-mode = <2>;
419 nvidia,cpu-pwr-good-time = <2000>;
420 nvidia,cpu-pwr-off-time = <0>;
421 nvidia,core-pwr-good-time = <3845 3845>;
422 nvidia,core-pwr-off-time = <0>;
423 nvidia,sys-clock-req-active-high;
418 }; 424 };
419 425
420 usb@c5000000 { 426 usb@c5000000 {
@@ -445,6 +451,7 @@
445 sdhci@c8000600 { 451 sdhci@c8000600 {
446 status = "okay"; 452 status = "okay";
447 bus-width = <8>; 453 bus-width = <8>;
454 non-removable;
448 }; 455 };
449 456
450 clocks { 457 clocks {
@@ -514,5 +521,8 @@
514 nvidia,audio-codec = <&alc5632>; 521 nvidia,audio-codec = <&alc5632>;
515 nvidia,i2s-controller = <&tegra_i2s1>; 522 nvidia,i2s-controller = <&tegra_i2s1>;
516 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 523 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
524
525 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
526 clock-names = "pll_a", "pll_a_out0", "mclk";
517 }; 527 };
518}; 528};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 289480026fbf..1a17cc30bb9d 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -52,5 +52,8 @@
52 52
53 nvidia,spkr-en-gpios = <&wm8903 2 0>; 53 nvidia,spkr-en-gpios = <&wm8903 2 0>;
54 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 54 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
55
56 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
57 clock-names = "pll_a", "pll_a_out0", "mclk";
55 }; 58 };
56}; 59};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 4ee700a33ca5..cee4c34010fe 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -517,6 +517,12 @@
517 517
518 pmc { 518 pmc {
519 nvidia,invert-interrupt; 519 nvidia,invert-interrupt;
520 nvidia,suspend-mode = <2>;
521 nvidia,cpu-pwr-good-time = <5000>;
522 nvidia,cpu-pwr-off-time = <5000>;
523 nvidia,core-pwr-good-time = <3845 3845>;
524 nvidia,core-pwr-off-time = <3875>;
525 nvidia,sys-clock-req-active-high;
520 }; 526 };
521 527
522 memory-controller@7000f400 { 528 memory-controller@7000f400 {
@@ -580,6 +586,7 @@
580 status = "okay"; 586 status = "okay";
581 power-gpios = <&gpio 86 0>; /* gpio PK6 */ 587 power-gpios = <&gpio 86 0>; /* gpio PK6 */
582 bus-width = <4>; 588 bus-width = <4>;
589 keep-power-in-suspend;
583 }; 590 };
584 591
585 sdhci@c8000400 { 592 sdhci@c8000400 {
@@ -593,6 +600,7 @@
593 sdhci@c8000600 { 600 sdhci@c8000600 {
594 status = "okay"; 601 status = "okay";
595 bus-width = <8>; 602 bus-width = <8>;
603 non-removable;
596 }; 604 };
597 605
598 clocks { 606 clocks {
@@ -821,5 +829,8 @@
821 829
822 nvidia,spkr-en-gpios = <&wm8903 2 0>; 830 nvidia,spkr-en-gpios = <&wm8903 2 0>;
823 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ 831 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
832
833 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
834 clock-names = "pll_a", "pll_a_out0", "mclk";
824 }; 835 };
825}; 836};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index c19025725918..50b3ec16b93a 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -458,6 +458,12 @@
458 458
459 pmc { 459 pmc {
460 nvidia,invert-interrupt; 460 nvidia,invert-interrupt;
461 nvidia,suspend-mode = <2>;
462 nvidia,cpu-pwr-good-time = <5000>;
463 nvidia,cpu-pwr-off-time = <5000>;
464 nvidia,core-pwr-good-time = <3845 3845>;
465 nvidia,core-pwr-off-time = <3875>;
466 nvidia,sys-clock-req-active-high;
461 }; 467 };
462 468
463 usb@c5008000 { 469 usb@c5008000 {
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 402b21004bef..742f0b38d21d 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -52,5 +52,8 @@
52 52
53 nvidia,spkr-en-gpios = <&wm8903 2 0>; 53 nvidia,spkr-en-gpios = <&wm8903 2 0>;
54 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 54 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
55
56 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
57 clock-names = "pll_a", "pll_a_out0", "mclk";
55 }; 58 };
56}; 59};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index a9f3f06580f5..9cc78a15d739 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -300,6 +300,15 @@
300 }; 300 };
301 }; 301 };
302 302
303 pmc {
304 nvidia,suspend-mode = <2>;
305 nvidia,cpu-pwr-good-time = <5000>;
306 nvidia,cpu-pwr-off-time = <5000>;
307 nvidia,core-pwr-good-time = <3845 3845>;
308 nvidia,core-pwr-off-time = <3875>;
309 nvidia,sys-clock-req-active-high;
310 };
311
303 usb@c5000000 { 312 usb@c5000000 {
304 status = "okay"; 313 status = "okay";
305 nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */ 314 nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
@@ -343,6 +352,17 @@
343 }; 352 };
344 }; 353 };
345 354
355 gpio-keys {
356 compatible = "gpio-keys";
357
358 power {
359 label = "Power";
360 gpios = <&gpio 190 1>; /* gpio PX6, active low */
361 linux,code = <116>; /* KEY_POWER */
362 gpio-key,wakeup;
363 };
364 };
365
346 poweroff { 366 poweroff {
347 compatible = "gpio-poweroff"; 367 compatible = "gpio-poweroff";
348 gpios = <&gpio 191 1>; /* gpio PX7, active low */ 368 gpios = <&gpio 191 1>; /* gpio PX7, active low */
@@ -376,5 +396,8 @@
376 compatible = "nvidia,tegra-audio-trimslice"; 396 compatible = "nvidia,tegra-audio-trimslice";
377 nvidia,i2s-controller = <&tegra_i2s1>; 397 nvidia,i2s-controller = <&tegra_i2s1>;
378 nvidia,audio-codec = <&codec>; 398 nvidia,audio-codec = <&codec>;
399
400 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
401 clock-names = "pll_a", "pll_a_out0", "mclk";
379 }; 402 };
380}; 403};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index f544806e9618..dd38f1f03834 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -493,6 +493,12 @@
493 493
494 pmc { 494 pmc {
495 nvidia,invert-interrupt; 495 nvidia,invert-interrupt;
496 nvidia,suspend-mode = <2>;
497 nvidia,cpu-pwr-good-time = <2000>;
498 nvidia,cpu-pwr-off-time = <100>;
499 nvidia,core-pwr-good-time = <3845 3845>;
500 nvidia,core-pwr-off-time = <458>;
501 nvidia,sys-clock-req-active-high;
496 }; 502 };
497 503
498 usb@c5000000 { 504 usb@c5000000 {
@@ -516,6 +522,7 @@
516 status = "okay"; 522 status = "okay";
517 power-gpios = <&gpio 86 0>; /* gpio PK6 */ 523 power-gpios = <&gpio 86 0>; /* gpio PK6 */
518 bus-width = <4>; 524 bus-width = <4>;
525 keep-power-in-suspend;
519 }; 526 };
520 527
521 sdhci@c8000400 { 528 sdhci@c8000400 {
@@ -529,6 +536,7 @@
529 sdhci@c8000600 { 536 sdhci@c8000600 {
530 status = "okay"; 537 status = "okay";
531 bus-width = <8>; 538 bus-width = <8>;
539 non-removable;
532 }; 540 };
533 541
534 clocks { 542 clocks {
@@ -544,6 +552,17 @@
544 }; 552 };
545 }; 553 };
546 554
555 gpio-keys {
556 compatible = "gpio-keys";
557
558 power {
559 label = "Power";
560 gpios = <&gpio 170 1>; /* gpio PV2, active low */
561 linux,code = <116>; /* KEY_POWER */
562 gpio-key,wakeup;
563 };
564 };
565
547 regulators { 566 regulators {
548 compatible = "simple-bus"; 567 compatible = "simple-bus";
549 #address-cells = <1>; 568 #address-cells = <1>;
@@ -620,5 +639,8 @@
620 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 639 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
621 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */ 640 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
622 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 641 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
642
643 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
644 clock-names = "pll_a", "pll_a_out0", "mclk";
623 }; 645 };
624}; 646};
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 258cf945f515..d2567f83aaff 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -496,6 +496,14 @@
496 496
497 pmc { 497 pmc {
498 nvidia,invert-interrupt; 498 nvidia,invert-interrupt;
499 nvidia,suspend-mode = <2>;
500 nvidia,cpu-pwr-good-time = <2000>;
501 nvidia,cpu-pwr-off-time = <1000>;
502 nvidia,core-pwr-good-time = <0 3845>;
503 nvidia,core-pwr-off-time = <93727>;
504 nvidia,core-power-req-active-high;
505 nvidia,sys-clock-req-active-high;
506 nvidia,combined-power-req;
499 }; 507 };
500 508
501 usb@c5000000 { 509 usb@c5000000 {
@@ -518,6 +526,7 @@
518 sdhci@c8000600 { 526 sdhci@c8000600 {
519 status = "okay"; 527 status = "okay";
520 bus-width = <8>; 528 bus-width = <8>;
529 non-removable;
521 }; 530 };
522 531
523 clocks { 532 clocks {
@@ -539,6 +548,7 @@
539 nvidia,repeat-delay-ms = <160>; 548 nvidia,repeat-delay-ms = <160>;
540 nvidia,kbc-row-pins = <0 1 2>; 549 nvidia,kbc-row-pins = <0 1 2>;
541 nvidia,kbc-col-pins = <16 17>; 550 nvidia,kbc-col-pins = <16 17>;
551 nvidia,wakeup-source;
542 linux,keymap = <0x00000074 /* KEY_POWER */ 552 linux,keymap = <0x00000074 /* KEY_POWER */
543 0x01000066 /* KEY_HOME */ 553 0x01000066 /* KEY_HOME */
544 0x0101009E /* KEY_BACK */ 554 0x0101009E /* KEY_BACK */
@@ -573,5 +583,8 @@
573 583
574 nvidia,i2s-controller = <&tegra_i2s1>; 584 nvidia,i2s-controller = <&tegra_i2s1>;
575 nvidia,audio-codec = <&codec>; 585 nvidia,audio-codec = <&codec>;
586
587 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
588 clock-names = "pll_a", "pll_a_out0", "mclk";
576 }; 589 };
577}; 590};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index fc7febc2b386..56a91106041b 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -209,7 +209,7 @@
209 compatible = "nvidia,tegra20-das"; 209 compatible = "nvidia,tegra20-das";
210 reg = <0x70000c00 0x80>; 210 reg = <0x70000c00 0x80>;
211 }; 211 };
212 212
213 tegra_ac97: ac97 { 213 tegra_ac97: ac97 {
214 compatible = "nvidia,tegra20-ac97"; 214 compatible = "nvidia,tegra20-ac97";
215 reg = <0x70002000 0x200>; 215 reg = <0x70002000 0x200>;
@@ -299,6 +299,7 @@
299 reg = <0x7000a000 0x100>; 299 reg = <0x7000a000 0x100>;
300 #pwm-cells = <2>; 300 #pwm-cells = <2>;
301 clocks = <&tegra_car 17>; 301 clocks = <&tegra_car 17>;
302 status = "disabled";
302 }; 303 };
303 304
304 rtc { 305 rtc {
@@ -442,31 +443,6 @@
442 #size-cells = <0>; 443 #size-cells = <0>;
443 }; 444 };
444 445
445 phy1: usb-phy@c5000400 {
446 compatible = "nvidia,tegra20-usb-phy";
447 reg = <0xc5000400 0x3c00>;
448 phy_type = "utmi";
449 nvidia,has-legacy-mode;
450 clocks = <&tegra_car 22>, <&tegra_car 127>;
451 clock-names = "phy", "pll_u";
452 };
453
454 phy2: usb-phy@c5004400 {
455 compatible = "nvidia,tegra20-usb-phy";
456 reg = <0xc5004400 0x3c00>;
457 phy_type = "ulpi";
458 clocks = <&tegra_car 94>, <&tegra_car 127>;
459 clock-names = "phy", "pll_u";
460 };
461
462 phy3: usb-phy@c5008400 {
463 compatible = "nvidia,tegra20-usb-phy";
464 reg = <0xc5008400 0x3C00>;
465 phy_type = "utmi";
466 clocks = <&tegra_car 22>, <&tegra_car 127>;
467 clock-names = "phy", "pll_u";
468 };
469
470 usb@c5000000 { 446 usb@c5000000 {
471 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 447 compatible = "nvidia,tegra20-ehci", "usb-ehci";
472 reg = <0xc5000000 0x4000>; 448 reg = <0xc5000000 0x4000>;
@@ -479,6 +455,15 @@
479 status = "disabled"; 455 status = "disabled";
480 }; 456 };
481 457
458 phy1: usb-phy@c5000400 {
459 compatible = "nvidia,tegra20-usb-phy";
460 reg = <0xc5000400 0x3c00>;
461 phy_type = "utmi";
462 nvidia,has-legacy-mode;
463 clocks = <&tegra_car 22>, <&tegra_car 127>;
464 clock-names = "phy", "pll_u";
465 };
466
482 usb@c5004000 { 467 usb@c5004000 {
483 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 468 compatible = "nvidia,tegra20-ehci", "usb-ehci";
484 reg = <0xc5004000 0x4000>; 469 reg = <0xc5004000 0x4000>;
@@ -489,6 +474,14 @@
489 status = "disabled"; 474 status = "disabled";
490 }; 475 };
491 476
477 phy2: usb-phy@c5004400 {
478 compatible = "nvidia,tegra20-usb-phy";
479 reg = <0xc5004400 0x3c00>;
480 phy_type = "ulpi";
481 clocks = <&tegra_car 93>, <&tegra_car 127>;
482 clock-names = "phy", "pll_u";
483 };
484
492 usb@c5008000 { 485 usb@c5008000 {
493 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 486 compatible = "nvidia,tegra20-ehci", "usb-ehci";
494 reg = <0xc5008000 0x4000>; 487 reg = <0xc5008000 0x4000>;
@@ -499,6 +492,14 @@
499 status = "disabled"; 492 status = "disabled";
500 }; 493 };
501 494
495 phy3: usb-phy@c5008400 {
496 compatible = "nvidia,tegra20-usb-phy";
497 reg = <0xc5008400 0x3c00>;
498 phy_type = "utmi";
499 clocks = <&tegra_car 22>, <&tegra_car 127>;
500 clock-names = "phy", "pll_u";
501 };
502
502 sdhci@c8000000 { 503 sdhci@c8000000 {
503 compatible = "nvidia,tegra20-sdhci"; 504 compatible = "nvidia,tegra20-sdhci";
504 reg = <0xc8000000 0x200>; 505 reg = <0xc8000000 0x200>;
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 6248b2445b32..b732f7c13a66 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -253,6 +253,13 @@
253 pmc { 253 pmc {
254 status = "okay"; 254 status = "okay";
255 nvidia,invert-interrupt; 255 nvidia,invert-interrupt;
256 nvidia,suspend-mode = <2>;
257 nvidia,cpu-pwr-good-time = <2000>;
258 nvidia,cpu-pwr-off-time = <200>;
259 nvidia,core-pwr-good-time = <3845 3845>;
260 nvidia,core-pwr-off-time = <0>;
261 nvidia,core-power-req-active-high;
262 nvidia,sys-clock-req-active-high;
256 }; 263 };
257 264
258 sdhci@78000000 { 265 sdhci@78000000 {
@@ -266,6 +273,7 @@
266 sdhci@78000600 { 273 sdhci@78000600 {
267 status = "okay"; 274 status = "okay";
268 bus-width = <8>; 275 bus-width = <8>;
276 non-removable;
269 }; 277 };
270 278
271 clocks { 279 clocks {
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index adc88aa50eb6..e392bd2dab9b 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -88,6 +88,7 @@
88 status = "okay"; 88 status = "okay";
89 power-gpios = <&gpio 28 0>; /* gpio PD4 */ 89 power-gpios = <&gpio 28 0>; /* gpio PD4 */
90 bus-width = <4>; 90 bus-width = <4>;
91 keep-power-in-suspend;
91 }; 92 };
92}; 93};
93 94
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index 08163e145d57..d0db6c7e774f 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -100,5 +100,6 @@
100 status = "okay"; 100 status = "okay";
101 power-gpios = <&gpio 27 0>; /* gpio PD3 */ 101 power-gpios = <&gpio 27 0>; /* gpio PD3 */
102 bus-width = <4>; 102 bus-width = <4>;
103 keep-power-in-suspend;
103 }; 104 };
104}; 105};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 65bf2b63174e..01b4c26fad96 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -307,6 +307,13 @@
307 pmc { 307 pmc {
308 status = "okay"; 308 status = "okay";
309 nvidia,invert-interrupt; 309 nvidia,invert-interrupt;
310 nvidia,suspend-mode = <2>;
311 nvidia,cpu-pwr-good-time = <2000>;
312 nvidia,cpu-pwr-off-time = <200>;
313 nvidia,core-pwr-good-time = <3845 3845>;
314 nvidia,core-pwr-off-time = <0>;
315 nvidia,core-power-req-active-high;
316 nvidia,sys-clock-req-active-high;
310 }; 317 };
311 318
312 sdhci@78000000 { 319 sdhci@78000000 {
@@ -320,6 +327,7 @@
320 sdhci@78000600 { 327 sdhci@78000600 {
321 status = "okay"; 328 status = "okay";
322 bus-width = <8>; 329 bus-width = <8>;
330 non-removable;
323 }; 331 };
324 332
325 clocks { 333 clocks {
@@ -509,5 +517,8 @@
509 517
510 nvidia,spkr-en-gpios = <&wm8903 2 0>; 518 nvidia,spkr-en-gpios = <&wm8903 2 0>;
511 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 519 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
520
521 clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
522 clock-names = "pll_a", "pll_a_out0", "mclk";
512 }; 523 };
513}; 524};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 9fe7a92b4c85..15ded605142a 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -286,6 +286,7 @@
286 reg = <0x7000a000 0x100>; 286 reg = <0x7000a000 0x100>;
287 #pwm-cells = <2>; 287 #pwm-cells = <2>;
288 clocks = <&tegra_car 17>; 288 clocks = <&tegra_car 17>;
289 status = "disabled";
289 }; 290 };
290 291
291 rtc { 292 rtc {
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index ed0bc9546837..b3034da00a37 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -23,6 +23,12 @@
23 compatible = "ti,twl4030-wdt"; 23 compatible = "ti,twl4030-wdt";
24 }; 24 };
25 25
26 vcc: regulator-vdd1 {
27 compatible = "ti,twl4030-vdd1";
28 regulator-min-microvolt = <600000>;
29 regulator-max-microvolt = <1450000>;
30 };
31
26 vdac: regulator-vdac { 32 vdac: regulator-vdac {
27 compatible = "ti,twl4030-vdac"; 33 compatible = "ti,twl4030-vdac";
28 regulator-min-microvolt = <1800000>; 34 regulator-min-microvolt = <1800000>;
@@ -67,7 +73,7 @@
67 #interrupt-cells = <1>; 73 #interrupt-cells = <1>;
68 }; 74 };
69 75
70 twl4030-usb { 76 usb2_phy: twl4030-usb {
71 compatible = "ti,twl4030-usb"; 77 compatible = "ti,twl4030-usb";
72 interrupts = <10>, <4>; 78 interrupts = <10>, <4>;
73 usb1v5-supply = <&vusb1v5>; 79 usb1v5-supply = <&vusb1v5>;
@@ -75,4 +81,14 @@
75 usb3v1-supply = <&vusb3v1>; 81 usb3v1-supply = <&vusb3v1>;
76 usb_mode = <1>; 82 usb_mode = <1>;
77 }; 83 };
84
85 twl_pwm: pwm {
86 compatible = "ti,twl4030-pwm";
87 #pwm-cells = <2>;
88 };
89
90 twl_pwmled: pwmled {
91 compatible = "ti,twl4030-pwmled";
92 #pwm-cells = <2>;
93 };
78}; 94};
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 9996cfc5ee80..2e3bd3172b23 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -91,4 +91,16 @@
91 compatible = "ti,twl6030-usb"; 91 compatible = "ti,twl6030-usb";
92 interrupts = <4>, <10>; 92 interrupts = <4>, <10>;
93 }; 93 };
94
95 twl_pwm: pwm {
96 /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */
97 compatible = "ti,twl6030-pwm";
98 #pwm-cells = <2>;
99 };
100
101 twl_pwmled: pwmled {
102 /* provides one PWM (id 0 for Charging indicator LED) */
103 compatible = "ti,twl6030-pwmled";
104 #pwm-cells = <2>;
105 };
94}; 106};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 10:15:10 -0500