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authorStephen Warren <swarren@nvidia.com>2013-02-12 12:26:45 -0500
committerStephen Warren <swarren@nvidia.com>2013-02-13 13:17:02 -0500
commit8364f5d96509e206f02a74bbdc2d4e3742cdefe4 (patch)
tree04506ee7833d303c642ce1a53a4c48e40be29858 /arch/arm/boot/dts/tegra30.dtsi
parent0203d91247090e57063e1ef63a6019e87548dfbc (diff)
ARM: tegra: remove clock-frequency properties from serial nodes
Currently, the serial nodes define both a clock-frequency and a clocks property. We should not provide both, since they might conflict. In practice, this also causes problems since the of_serial driver uses the clock-frequency property in preference to the clocks property, and hence doesn't clk_prepare_enable() the clock, which may then leave it with no known users, and hence the common clock framework will disable it, thus breaking the port, which is usually the console. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi5
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 572a45bab93b..767803e1fd55 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -234,7 +234,6 @@
234 reg = <0x70006000 0x40>; 234 reg = <0x70006000 0x40>;
235 reg-shift = <2>; 235 reg-shift = <2>;
236 interrupts = <0 36 0x04>; 236 interrupts = <0 36 0x04>;
237 clock-frequency = <408000000>;
238 nvidia,dma-request-selector = <&apbdma 8>; 237 nvidia,dma-request-selector = <&apbdma 8>;
239 clocks = <&tegra_car 6>; 238 clocks = <&tegra_car 6>;
240 status = "disabled"; 239 status = "disabled";
@@ -244,7 +243,6 @@
244 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 243 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
245 reg = <0x70006040 0x40>; 244 reg = <0x70006040 0x40>;
246 reg-shift = <2>; 245 reg-shift = <2>;
247 clock-frequency = <408000000>;
248 interrupts = <0 37 0x04>; 246 interrupts = <0 37 0x04>;
249 nvidia,dma-request-selector = <&apbdma 9>; 247 nvidia,dma-request-selector = <&apbdma 9>;
250 clocks = <&tegra_car 160>; 248 clocks = <&tegra_car 160>;
@@ -255,7 +253,6 @@
255 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 253 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
256 reg = <0x70006200 0x100>; 254 reg = <0x70006200 0x100>;
257 reg-shift = <2>; 255 reg-shift = <2>;
258 clock-frequency = <408000000>;
259 interrupts = <0 46 0x04>; 256 interrupts = <0 46 0x04>;
260 nvidia,dma-request-selector = <&apbdma 10>; 257 nvidia,dma-request-selector = <&apbdma 10>;
261 clocks = <&tegra_car 55>; 258 clocks = <&tegra_car 55>;
@@ -266,7 +263,6 @@
266 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 263 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
267 reg = <0x70006300 0x100>; 264 reg = <0x70006300 0x100>;
268 reg-shift = <2>; 265 reg-shift = <2>;
269 clock-frequency = <408000000>;
270 interrupts = <0 90 0x04>; 266 interrupts = <0 90 0x04>;
271 nvidia,dma-request-selector = <&apbdma 19>; 267 nvidia,dma-request-selector = <&apbdma 19>;
272 clocks = <&tegra_car 65>; 268 clocks = <&tegra_car 65>;
@@ -277,7 +273,6 @@
277 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 273 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
278 reg = <0x70006400 0x100>; 274 reg = <0x70006400 0x100>;
279 reg-shift = <2>; 275 reg-shift = <2>;
280 clock-frequency = <408000000>;
281 interrupts = <0 91 0x04>; 276 interrupts = <0 91 0x04>;
282 nvidia,dma-request-selector = <&apbdma 20>; 277 nvidia,dma-request-selector = <&apbdma 20>;
283 clocks = <&tegra_car 66>; 278 clocks = <&tegra_car 66>;