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authorStephen Warren <swarren@nvidia.com>2014-01-07 18:33:31 -0500
committerStephen Warren <swarren@nvidia.com>2014-02-19 12:15:45 -0500
commit1771a2542043109f9382b870db9a35f578c42096 (patch)
tree06df8bb6a68fa33102df932aa1a2eea3856aa71d /arch/arm/boot/dts/tegra20-ventana.dts
parent9615d65631bfed84dcbdf8b1ef3b6410f512e974 (diff)
ARM: tegra: enable LCD panel on Ventana
Ventana uses a CLAA101WA01A LCD panel. Enable the relevant display controller, backlight, and regulators. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-ventana.dts')
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts39
1 files changed, 36 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 571d12e6ac2d..ca8484cccddc 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -17,6 +17,14 @@
17 }; 17 };
18 18
19 host1x@50000000 { 19 host1x@50000000 {
20 dc@54200000 {
21 rgb {
22 status = "okay";
23
24 nvidia,panel = <&panel>;
25 };
26 };
27
20 hdmi@54280000 { 28 hdmi@54280000 {
21 status = "okay"; 29 status = "okay";
22 30
@@ -309,6 +317,10 @@
309 status = "okay"; 317 status = "okay";
310 }; 318 };
311 319
320 pwm: pwm@7000a000 {
321 status = "okay";
322 };
323
312 i2c@7000c000 { 324 i2c@7000c000 {
313 status = "okay"; 325 status = "okay";
314 clock-frequency = <400000>; 326 clock-frequency = <400000>;
@@ -359,7 +371,7 @@
359 #size-cells = <0>; 371 #size-cells = <0>;
360 }; 372 };
361 373
362 i2c@1 { 374 lvds_ddc: i2c@1 {
363 reg = <1>; 375 reg = <1>;
364 #address-cells = <1>; 376 #address-cells = <1>;
365 #size-cells = <0>; 377 #size-cells = <0>;
@@ -557,6 +569,17 @@
557 non-removable; 569 non-removable;
558 }; 570 };
559 571
572 backlight: backlight {
573 compatible = "pwm-backlight";
574
575 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
576 power-supply = <&vdd_bl_reg>;
577 pwms = <&pwm 2 5000000>;
578
579 brightness-levels = <0 4 8 16 32 64 128 255>;
580 default-brightness-level = <6>;
581 };
582
560 clocks { 583 clocks {
561 compatible = "simple-bus"; 584 compatible = "simple-bus";
562 #address-cells = <1>; 585 #address-cells = <1>;
@@ -581,6 +604,16 @@
581 }; 604 };
582 }; 605 };
583 606
607 panel: panel {
608 compatible = "chunghwa,claa101wa01a", "simple-panel";
609
610 power-supply = <&vdd_pnl_reg>;
611 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
612
613 backlight = <&backlight>;
614 ddc-i2c-bus = <&lvds_ddc>;
615 };
616
584 regulators { 617 regulators {
585 compatible = "simple-bus"; 618 compatible = "simple-bus";
586 #address-cells = <1>; 619 #address-cells = <1>;
@@ -614,7 +647,7 @@
614 enable-active-high; 647 enable-active-high;
615 }; 648 };
616 649
617 regulator@3 { 650 vdd_pnl_reg: regulator@3 {
618 compatible = "regulator-fixed"; 651 compatible = "regulator-fixed";
619 reg = <3>; 652 reg = <3>;
620 regulator-name = "vdd_pnl"; 653 regulator-name = "vdd_pnl";
@@ -624,7 +657,7 @@
624 enable-active-high; 657 enable-active-high;
625 }; 658 };
626 659
627 regulator@4 { 660 vdd_bl_reg: regulator@4 {
628 compatible = "regulator-fixed"; 661 compatible = "regulator-fixed";
629 reg = <4>; 662 reg = <4>;
630 regulator-name = "vdd_bl"; 663 regulator-name = "vdd_bl";