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authorDinh Nguyen <dinguyen@altera.com>2014-02-17 21:31:02 -0500
committerDinh Nguyen <dinguyen@altera.com>2014-03-10 00:11:35 -0400
commit9b931361ff0971d2639b1366f8b468c687fa942f (patch)
tree7d38293deaeddd014219ddbb749d23a88f575d24 /arch/arm/boot/dts/socfpga_arria5.dtsi
parentf1ce1a99f289474cf047923981369d5ba140c125 (diff)
dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform specific implementation of the dw_mmc driver. Also add the "syscon" binding to the "altr,sys-mgr" node. The clock driver can use the syscon driver to toggle the register for the SD/MMC clock phase shift settings. Finally, fix an indentation error for the sysmgr node. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria5.dtsi')
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index a85b4043f888..6c87b7070ca7 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -27,6 +27,17 @@
27 }; 27 };
28 }; 28 };
29 29
30 dwmmc0@ff704000 {
31 num-slots = <1>;
32 supports-highspeed;
33 broken-cd;
34
35 slot@0 {
36 reg = <0>;
37 bus-width = <4>;
38 };
39 };
40
30 serial0@ffc02000 { 41 serial0@ffc02000 {
31 clock-frequency = <100000000>; 42 clock-frequency = <100000000>;
32 }; 43 };