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authorUlrich Hecht <ulrich.hecht+renesas@gmail.com>2014-09-24 21:32:12 -0400
committerSimon Horman <horms+renesas@verge.net.au>2014-10-23 21:44:04 -0400
commit005980c0024ecd192c2eac3e3a9dcda1bedddffb (patch)
tree76331d42cae69bb7e04090fee8a091068ca53558 /arch/arm/boot/dts/r7s72100.dtsi
parent6a8663f8bb5e3e2bf0d362744db844f2678d9b8b (diff)
ARM: shmobile: r7s72100: sort dtsi file by address
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r7s72100.dtsi')
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi202
1 files changed, 101 insertions, 101 deletions
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 801a556e264b..277e73c110e5 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -52,16 +52,6 @@
52 clock-output-names = "usb_x1"; 52 clock-output-names = "usb_x1";
53 }; 53 };
54 54
55 /* Special CPG clocks */
56 cpg_clocks: cpg_clocks@fcfe0000 {
57 #clock-cells = <1>;
58 compatible = "renesas,r7s72100-cpg-clocks",
59 "renesas,rz-cpg-clocks";
60 reg = <0xfcfe0000 0x18>;
61 clocks = <&extal_clk>, <&usb_x1_clk>;
62 clock-output-names = "pll", "i", "g";
63 };
64
65 /* Fixed factor clocks */ 55 /* Fixed factor clocks */
66 b_clk: b_clk { 56 b_clk: b_clk {
67 #clock-cells = <0>; 57 #clock-cells = <0>;
@@ -88,6 +78,16 @@
88 clock-output-names = "p0"; 78 clock-output-names = "p0";
89 }; 79 };
90 80
81 /* Special CPG clocks */
82 cpg_clocks: cpg_clocks@fcfe0000 {
83 #clock-cells = <1>;
84 compatible = "renesas,r7s72100-cpg-clocks",
85 "renesas,rz-cpg-clocks";
86 reg = <0xfcfe0000 0x18>;
87 clocks = <&extal_clk>, <&usb_x1_clk>;
88 clock-output-names = "pll", "i", "g";
89 };
90
91 /* MSTP clocks */ 91 /* MSTP clocks */
92 mstp3_clks: mstp3_clks@fcfe0420 { 92 mstp3_clks: mstp3_clks@fcfe0420 {
93 #clock-cells = <1>; 93 #clock-cells = <1>;
@@ -148,97 +148,6 @@
148 }; 148 };
149 }; 149 };
150 150
151 gic: interrupt-controller@e8201000 {
152 compatible = "arm,cortex-a9-gic";
153 #interrupt-cells = <3>;
154 #address-cells = <0>;
155 interrupt-controller;
156 reg = <0xe8201000 0x1000>,
157 <0xe8202000 0x1000>;
158 };
159
160 i2c0: i2c@fcfee000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
164 reg = <0xfcfee000 0x44>;
165 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
166 <0 158 IRQ_TYPE_EDGE_RISING>,
167 <0 159 IRQ_TYPE_EDGE_RISING>,
168 <0 160 IRQ_TYPE_LEVEL_HIGH>,
169 <0 161 IRQ_TYPE_LEVEL_HIGH>,
170 <0 162 IRQ_TYPE_LEVEL_HIGH>,
171 <0 163 IRQ_TYPE_LEVEL_HIGH>,
172 <0 164 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
174 clock-frequency = <100000>;
175 status = "disabled";
176 };
177
178 i2c1: i2c@fcfee400 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
182 reg = <0xfcfee400 0x44>;
183 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
184 <0 166 IRQ_TYPE_EDGE_RISING>,
185 <0 167 IRQ_TYPE_EDGE_RISING>,
186 <0 168 IRQ_TYPE_LEVEL_HIGH>,
187 <0 169 IRQ_TYPE_LEVEL_HIGH>,
188 <0 170 IRQ_TYPE_LEVEL_HIGH>,
189 <0 171 IRQ_TYPE_LEVEL_HIGH>,
190 <0 172 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
192 clock-frequency = <100000>;
193 status = "disabled";
194 };
195
196 i2c2: i2c@fcfee800 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
200 reg = <0xfcfee800 0x44>;
201 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
202 <0 174 IRQ_TYPE_EDGE_RISING>,
203 <0 175 IRQ_TYPE_EDGE_RISING>,
204 <0 176 IRQ_TYPE_LEVEL_HIGH>,
205 <0 177 IRQ_TYPE_LEVEL_HIGH>,
206 <0 178 IRQ_TYPE_LEVEL_HIGH>,
207 <0 179 IRQ_TYPE_LEVEL_HIGH>,
208 <0 180 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
210 clock-frequency = <100000>;
211 status = "disabled";
212 };
213
214 i2c3: i2c@fcfeec00 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
218 reg = <0xfcfeec00 0x44>;
219 interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
220 <0 182 IRQ_TYPE_EDGE_RISING>,
221 <0 183 IRQ_TYPE_EDGE_RISING>,
222 <0 184 IRQ_TYPE_LEVEL_HIGH>,
223 <0 185 IRQ_TYPE_LEVEL_HIGH>,
224 <0 186 IRQ_TYPE_LEVEL_HIGH>,
225 <0 187 IRQ_TYPE_LEVEL_HIGH>,
226 <0 188 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
228 clock-frequency = <100000>;
229 status = "disabled";
230 };
231
232 mtu2: timer@fcff0000 {
233 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
234 reg = <0xfcff0000 0x400>;
235 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-names = "tgi0a";
237 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
238 clock-names = "fck";
239 status = "disabled";
240 };
241
242 scif0: serial@e8007000 { 151 scif0: serial@e8007000 {
243 compatible = "renesas,scif-r7s72100", "renesas,scif"; 152 compatible = "renesas,scif-r7s72100", "renesas,scif";
244 reg = <0xe8007000 64>; 153 reg = <0xe8007000 64>;
@@ -404,4 +313,95 @@
404 #size-cells = <0>; 313 #size-cells = <0>;
405 status = "disabled"; 314 status = "disabled";
406 }; 315 };
316
317 gic: interrupt-controller@e8201000 {
318 compatible = "arm,cortex-a9-gic";
319 #interrupt-cells = <3>;
320 #address-cells = <0>;
321 interrupt-controller;
322 reg = <0xe8201000 0x1000>,
323 <0xe8202000 0x1000>;
324 };
325
326 i2c0: i2c@fcfee000 {
327 #address-cells = <1>;
328 #size-cells = <0>;
329 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
330 reg = <0xfcfee000 0x44>;
331 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
332 <0 158 IRQ_TYPE_EDGE_RISING>,
333 <0 159 IRQ_TYPE_EDGE_RISING>,
334 <0 160 IRQ_TYPE_LEVEL_HIGH>,
335 <0 161 IRQ_TYPE_LEVEL_HIGH>,
336 <0 162 IRQ_TYPE_LEVEL_HIGH>,
337 <0 163 IRQ_TYPE_LEVEL_HIGH>,
338 <0 164 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
340 clock-frequency = <100000>;
341 status = "disabled";
342 };
343
344 i2c1: i2c@fcfee400 {
345 #address-cells = <1>;
346 #size-cells = <0>;
347 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
348 reg = <0xfcfee400 0x44>;
349 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
350 <0 166 IRQ_TYPE_EDGE_RISING>,
351 <0 167 IRQ_TYPE_EDGE_RISING>,
352 <0 168 IRQ_TYPE_LEVEL_HIGH>,
353 <0 169 IRQ_TYPE_LEVEL_HIGH>,
354 <0 170 IRQ_TYPE_LEVEL_HIGH>,
355 <0 171 IRQ_TYPE_LEVEL_HIGH>,
356 <0 172 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
358 clock-frequency = <100000>;
359 status = "disabled";
360 };
361
362 i2c2: i2c@fcfee800 {
363 #address-cells = <1>;
364 #size-cells = <0>;
365 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
366 reg = <0xfcfee800 0x44>;
367 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
368 <0 174 IRQ_TYPE_EDGE_RISING>,
369 <0 175 IRQ_TYPE_EDGE_RISING>,
370 <0 176 IRQ_TYPE_LEVEL_HIGH>,
371 <0 177 IRQ_TYPE_LEVEL_HIGH>,
372 <0 178 IRQ_TYPE_LEVEL_HIGH>,
373 <0 179 IRQ_TYPE_LEVEL_HIGH>,
374 <0 180 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
376 clock-frequency = <100000>;
377 status = "disabled";
378 };
379
380 i2c3: i2c@fcfeec00 {
381 #address-cells = <1>;
382 #size-cells = <0>;
383 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
384 reg = <0xfcfeec00 0x44>;
385 interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
386 <0 182 IRQ_TYPE_EDGE_RISING>,
387 <0 183 IRQ_TYPE_EDGE_RISING>,
388 <0 184 IRQ_TYPE_LEVEL_HIGH>,
389 <0 185 IRQ_TYPE_LEVEL_HIGH>,
390 <0 186 IRQ_TYPE_LEVEL_HIGH>,
391 <0 187 IRQ_TYPE_LEVEL_HIGH>,
392 <0 188 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
394 clock-frequency = <100000>;
395 status = "disabled";
396 };
397
398 mtu2: timer@fcff0000 {
399 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
400 reg = <0xfcff0000 0x400>;
401 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "tgi0a";
403 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
404 clock-names = "fck";
405 status = "disabled";
406 };
407}; 407};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 22:23:27 -0500