aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
diff options
context:
space:
mode:
authorKumar Gala <galak@codeaurora.org>2014-05-28 13:01:29 -0400
committerKumar Gala <galak@codeaurora.org>2014-05-28 14:31:45 -0400
commitba08220aa81e757491a3665c28df7eaa954128dc (patch)
tree8cd84ae11f6d77c1aec1c66d2a0dab7a89185eaf /arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
parent08f9234ad6b0b8bc51046346eabf5b92e631e62a (diff)
ARM: dts: qcom: Update msm8974/apq8074 device trees
* Move SoC peripherals into an SoC container node * Move serial enabling into board file (qcom-apq8074-dragonboard.dts) * Move spi pinctrl into board file * Cleanup cpu node to match binding spec, enable-method and compatible should be per cpu, not part of the container * Drop interrupts property from l2-cache node as its not part of the binding spec * Move timer node out of SoC container Signed-off-by: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-apq8074-dragonboard.dts')
-rw-r--r--arch/arm/boot/dts/qcom-apq8074-dragonboard.dts28
1 files changed, 27 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 92320c4a7668..b4dfb01fe6fb 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -4,7 +4,11 @@
4 model = "Qualcomm APQ8074 Dragonboard"; 4 model = "Qualcomm APQ8074 Dragonboard";
5 compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; 5 compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
6 6
7 soc: soc { 7 soc {
8 serial@f991e000 {
9 status = "ok";
10 };
11
8 sdhci@f9824900 { 12 sdhci@f9824900 {
9 bus-width = <8>; 13 bus-width = <8>;
10 non-removable; 14 non-removable;
@@ -15,5 +19,27 @@
15 cd-gpios = <&msmgpio 62 0x1>; 19 cd-gpios = <&msmgpio 62 0x1>;
16 bus-width = <4>; 20 bus-width = <4>;
17 }; 21 };
22
23
24 pinctrl@fd510000 {
25 spi8_default: spi8_default {
26 mosi {
27 pins = "gpio45";
28 function = "blsp_spi8";
29 };
30 miso {
31 pins = "gpio46";
32 function = "blsp_spi8";
33 };
34 cs {
35 pins = "gpio47";
36 function = "blsp_spi8";
37 };
38 clk {
39 pins = "gpio48";
40 function = "blsp_spi8";
41 };
42 };
43 };
18 }; 44 };
19}; 45};