diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2012-08-12 08:02:10 -0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2012-09-11 04:26:50 -0400 |
| commit | 5be03a7bdb0f7411465eb90b3b670e99e1aefbe5 (patch) | |
| tree | a61ec2b91207a4416d8b19d62e2b44106ca696dd /arch/arm/boot/dts/imx53.dtsi | |
| parent | d9d253a498a60043b5f63ff7b4060ef6553f24d9 (diff) | |
ARM: dts: imx53-qsb: add pinctrl settings
Add pinctrl settings for existing devices in imx53-qsb.dts.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx53.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx53.dtsi | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 776ce410d057..01fa49abab6d 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -216,6 +216,96 @@ | |||
| 216 | status = "disabled"; | 216 | status = "disabled"; |
| 217 | }; | 217 | }; |
| 218 | 218 | ||
| 219 | iomuxc@53fa8000 { | ||
| 220 | compatible = "fsl,imx53-iomuxc"; | ||
| 221 | reg = <0x53fa8000 0x4000>; | ||
| 222 | |||
| 223 | audmux { | ||
| 224 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 225 | fsl,pins = < | ||
| 226 | 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ | ||
| 227 | 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ | ||
| 228 | 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ | ||
| 229 | 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ | ||
| 230 | >; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | |||
| 234 | fec { | ||
| 235 | pinctrl_fec_1: fecgrp-1 { | ||
| 236 | fsl,pins = < | ||
| 237 | 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ | ||
| 238 | 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ | ||
| 239 | 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ | ||
| 240 | 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ | ||
| 241 | 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ | ||
| 242 | 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ | ||
| 243 | 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ | ||
| 244 | 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ | ||
| 245 | 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ | ||
| 246 | 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ | ||
| 247 | >; | ||
| 248 | }; | ||
| 249 | }; | ||
| 250 | |||
| 251 | esdhc1 { | ||
| 252 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 253 | fsl,pins = < | ||
| 254 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ | ||
| 255 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ | ||
| 256 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ | ||
| 257 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ | ||
| 258 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ | ||
| 259 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ | ||
| 260 | >; | ||
| 261 | }; | ||
| 262 | }; | ||
| 263 | |||
| 264 | esdhc3 { | ||
| 265 | pinctrl_esdhc3_1: esdhc3grp-1 { | ||
| 266 | fsl,pins = < | ||
| 267 | 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ | ||
| 268 | 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ | ||
| 269 | 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ | ||
| 270 | 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ | ||
| 271 | 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ | ||
| 272 | 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ | ||
| 273 | 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ | ||
| 274 | 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ | ||
| 275 | 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ | ||
| 276 | 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ | ||
| 277 | >; | ||
| 278 | }; | ||
| 279 | }; | ||
| 280 | |||
| 281 | i2c1 { | ||
| 282 | pinctrl_i2c1_1: i2c1grp-1 { | ||
| 283 | fsl,pins = < | ||
| 284 | 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ | ||
| 285 | 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ | ||
| 286 | >; | ||
| 287 | }; | ||
| 288 | }; | ||
| 289 | |||
| 290 | i2c2 { | ||
| 291 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 292 | fsl,pins = < | ||
| 293 | 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ | ||
| 294 | 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ | ||
| 295 | >; | ||
| 296 | }; | ||
| 297 | }; | ||
| 298 | |||
| 299 | uart1 { | ||
| 300 | pinctrl_uart1_1: uart1grp-1 { | ||
| 301 | fsl,pins = < | ||
| 302 | 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ | ||
| 303 | 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ | ||
| 304 | >; | ||
| 305 | }; | ||
| 306 | }; | ||
| 307 | }; | ||
| 308 | |||
| 219 | uart1: serial@53fbc000 { | 309 | uart1: serial@53fbc000 { |
| 220 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; | 310 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 221 | reg = <0x53fbc000 0x4000>; | 311 | reg = <0x53fbc000 0x4000>; |