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authorRob Herring <rob.herring@calxeda.com>2012-10-25 12:59:09 -0400
committerRob Herring <rob.herring@calxeda.com>2012-10-31 14:46:17 -0400
commit7d6ab9b8620bbca6718b36242113f4f069840641 (patch)
tree9d26ff4c09ae674d0079ea652907fd51845f86e7 /arch/arm/boot/dts/highbank.dts
parent185bdffb4b2997a2d4ee2e88d52a6539bde59eea (diff)
ARM: dts: Add Calxeda ECX-2000 support
Separate out common dts pieces from highbank dts and add support for Calxeda ECX-2000 (Midway) SOC. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/highbank.dts')
-rw-r--r--arch/arm/boot/dts/highbank.dts219
1 files changed, 3 insertions, 216 deletions
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index e39a79a61e0c..a9ae5d32e80d 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -69,16 +69,8 @@
69 reg = <0x00000000 0xff900000>; 69 reg = <0x00000000 0xff900000>;
70 }; 70 };
71 71
72 chosen {
73 bootargs = "console=ttyAMA0";
74 };
75
76 soc { 72 soc {
77 #address-cells = <1>; 73 ranges = <0x00000000 0x00000000 0xffffffff>;
78 #size-cells = <1>;
79 compatible = "simple-bus";
80 interrupt-parent = <&intc>;
81 ranges;
82 74
83 timer@fff10600 { 75 timer@fff10600 {
84 compatible = "arm,cortex-a9-twd-timer"; 76 compatible = "arm,cortex-a9-twd-timer";
@@ -117,178 +109,6 @@
117 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; 109 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
118 }; 110 };
119 111
120 sata@ffe08000 {
121 compatible = "calxeda,hb-ahci";
122 reg = <0xffe08000 0x10000>;
123 interrupts = <0 83 4>;
124 calxeda,port-phys = <&combophy5 0 &combophy0 0
125 &combophy0 1 &combophy0 2
126 &combophy0 3>;
127 dma-coherent;
128 };
129
130 sdhci@ffe0e000 {
131 compatible = "calxeda,hb-sdhci";
132 reg = <0xffe0e000 0x1000>;
133 interrupts = <0 90 4>;
134 clocks = <&eclk>;
135 status = "disabled";
136 };
137
138 memory-controller@fff00000 {
139 compatible = "calxeda,hb-ddr-ctrl";
140 reg = <0xfff00000 0x1000>;
141 interrupts = <0 91 4>;
142 };
143
144 ipc@fff20000 {
145 compatible = "arm,pl320", "arm,primecell";
146 reg = <0xfff20000 0x1000>;
147 interrupts = <0 7 4>;
148 clocks = <&pclk>;
149 clock-names = "apb_pclk";
150 };
151
152 gpioe: gpio@fff30000 {
153 #gpio-cells = <2>;
154 compatible = "arm,pl061", "arm,primecell";
155 gpio-controller;
156 reg = <0xfff30000 0x1000>;
157 interrupts = <0 14 4>;
158 clocks = <&pclk>;
159 clock-names = "apb_pclk";
160 status = "disabled";
161 };
162
163 gpiof: gpio@fff31000 {
164 #gpio-cells = <2>;
165 compatible = "arm,pl061", "arm,primecell";
166 gpio-controller;
167 reg = <0xfff31000 0x1000>;
168 interrupts = <0 15 4>;
169 clocks = <&pclk>;
170 clock-names = "apb_pclk";
171 status = "disabled";
172 };
173
174 gpiog: gpio@fff32000 {
175 #gpio-cells = <2>;
176 compatible = "arm,pl061", "arm,primecell";
177 gpio-controller;
178 reg = <0xfff32000 0x1000>;
179 interrupts = <0 16 4>;
180 clocks = <&pclk>;
181 clock-names = "apb_pclk";
182 status = "disabled";
183 };
184
185 gpioh: gpio@fff33000 {
186 #gpio-cells = <2>;
187 compatible = "arm,pl061", "arm,primecell";
188 gpio-controller;
189 reg = <0xfff33000 0x1000>;
190 interrupts = <0 17 4>;
191 clocks = <&pclk>;
192 clock-names = "apb_pclk";
193 status = "disabled";
194 };
195
196 timer {
197 compatible = "arm,sp804", "arm,primecell";
198 reg = <0xfff34000 0x1000>;
199 interrupts = <0 18 4>;
200 clocks = <&pclk>;
201 clock-names = "apb_pclk";
202 };
203
204 rtc@fff35000 {
205 compatible = "arm,pl031", "arm,primecell";
206 reg = <0xfff35000 0x1000>;
207 interrupts = <0 19 4>;
208 clocks = <&pclk>;
209 clock-names = "apb_pclk";
210 };
211
212 serial@fff36000 {
213 compatible = "arm,pl011", "arm,primecell";
214 reg = <0xfff36000 0x1000>;
215 interrupts = <0 20 4>;
216 clocks = <&pclk>;
217 clock-names = "apb_pclk";
218 };
219
220 smic@fff3a000 {
221 compatible = "ipmi-smic";
222 device_type = "ipmi";
223 reg = <0xfff3a000 0x1000>;
224 interrupts = <0 24 4>;
225 reg-size = <4>;
226 reg-spacing = <4>;
227 };
228
229 sregs@fff3c000 {
230 compatible = "calxeda,hb-sregs";
231 reg = <0xfff3c000 0x1000>;
232
233 clocks {
234 #address-cells = <1>;
235 #size-cells = <0>;
236
237 osc: oscillator {
238 #clock-cells = <0>;
239 compatible = "fixed-clock";
240 clock-frequency = <33333000>;
241 };
242
243 ddrpll: ddrpll {
244 #clock-cells = <0>;
245 compatible = "calxeda,hb-pll-clock";
246 clocks = <&osc>;
247 reg = <0x108>;
248 };
249
250 a9pll: a9pll {
251 #clock-cells = <0>;
252 compatible = "calxeda,hb-pll-clock";
253 clocks = <&osc>;
254 reg = <0x100>;
255 };
256
257 a9periphclk: a9periphclk {
258 #clock-cells = <0>;
259 compatible = "calxeda,hb-a9periph-clock";
260 clocks = <&a9pll>;
261 reg = <0x104>;
262 };
263
264 a9bclk: a9bclk {
265 #clock-cells = <0>;
266 compatible = "calxeda,hb-a9bus-clock";
267 clocks = <&a9pll>;
268 reg = <0x104>;
269 };
270
271 emmcpll: emmcpll {
272 #clock-cells = <0>;
273 compatible = "calxeda,hb-pll-clock";
274 clocks = <&osc>;
275 reg = <0x10C>;
276 };
277
278 eclk: eclk {
279 #clock-cells = <0>;
280 compatible = "calxeda,hb-emmc-clock";
281 clocks = <&emmcpll>;
282 reg = <0x114>;
283 };
284
285 pclk: pclk {
286 #clock-cells = <0>;
287 compatible = "fixed-clock";
288 clock-frequency = <150000000>;
289 };
290 };
291 };
292 112
293 sregs@fff3c200 { 113 sregs@fff3c200 {
294 compatible = "calxeda,hb-sregs-l2-ecc"; 114 compatible = "calxeda,hb-sregs-l2-ecc";
@@ -296,40 +116,7 @@
296 interrupts = <0 71 4 0 72 4>; 116 interrupts = <0 71 4 0 72 4>;
297 }; 117 };
298 118
299 dma@fff3d000 {
300 compatible = "arm,pl330", "arm,primecell";
301 reg = <0xfff3d000 0x1000>;
302 interrupts = <0 92 4>;
303 clocks = <&pclk>;
304 clock-names = "apb_pclk";
305 };
306
307 ethernet@fff50000 {
308 compatible = "calxeda,hb-xgmac";
309 reg = <0xfff50000 0x1000>;
310 interrupts = <0 77 4 0 78 4 0 79 4>;
311 dma-coherent;
312 };
313
314 ethernet@fff51000 {
315 compatible = "calxeda,hb-xgmac";
316 reg = <0xfff51000 0x1000>;
317 interrupts = <0 80 4 0 81 4 0 82 4>;
318 dma-coherent;
319 };
320
321 combophy0: combo-phy@fff58000 {
322 compatible = "calxeda,hb-combophy";
323 #phy-cells = <1>;
324 reg = <0xfff58000 0x1000>;
325 phydev = <5>;
326 };
327
328 combophy5: combo-phy@fff5d000 {
329 compatible = "calxeda,hb-combophy";
330 #phy-cells = <1>;
331 reg = <0xfff5d000 0x1000>;
332 phydev = <31>;
333 };
334 }; 119 };
335}; 120};
121
122/include/ "ecx-common.dtsi"
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