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authorKrzysztof Kozlowski <krzk@kernel.org>2016-05-08 12:41:57 -0400
committerKrzysztof Kozlowski <k.kozlowski@samsung.com>2016-05-31 06:42:40 -0400
commitc9cf996d854b8f96d450083d3e0aace457a5a46b (patch)
treee939c2fcd63e941ccdae7a7a3a1ebb28fbfb2489 /arch/arm/boot/dts/exynos5420.dtsi
parent3f2f95ff6aa3490ae57364424b59b80cbff6be29 (diff)
ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI
The Exynos5410/542x/5800 are very similar designs. Create a new DTSI with common nodes to remove DTS duplication. Although currently only MCT and SysRAM are shared but in future more nodes will be added to the common file. The patch should not have functional impact. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi54
1 files changed, 6 insertions, 48 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index fa8bda836cef..2d9f43b8cc15 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -13,9 +13,8 @@
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 */ 14 */
15 15
16#include "exynos54xx.dtsi"
16#include <dt-bindings/clock/exynos5420.h> 17#include <dt-bindings/clock/exynos5420.h>
17#include "exynos5.dtsi"
18
19#include <dt-bindings/clock/exynos-audss-clk.h> 18#include <dt-bindings/clock/exynos-audss-clk.h>
20 19
21/ { 20/ {
@@ -181,24 +180,6 @@
181 }; 180 };
182 }; 181 };
183 182
184 sysram@02020000 {
185 compatible = "mmio-sram";
186 reg = <0x02020000 0x54000>;
187 #address-cells = <1>;
188 #size-cells = <1>;
189 ranges = <0 0x02020000 0x54000>;
190
191 smp-sysram@0 {
192 compatible = "samsung,exynos4210-sysram";
193 reg = <0x0 0x1000>;
194 };
195
196 smp-sysram@53000 {
197 compatible = "samsung,exynos4210-sysram-ns";
198 reg = <0x53000 0x1000>;
199 };
200 };
201
202 clock: clock-controller@10010000 { 183 clock: clock-controller@10010000 {
203 compatible = "samsung,exynos5420-clock"; 184 compatible = "samsung,exynos5420-clock";
204 reg = <0x10010000 0x30000>; 185 reg = <0x10010000 0x30000>;
@@ -261,34 +242,6 @@
261 status = "disabled"; 242 status = "disabled";
262 }; 243 };
263 244
264 mct: mct@101C0000 {
265 compatible = "samsung,exynos4210-mct";
266 reg = <0x101C0000 0xB00>;
267 interrupt-parent = <&mct_map>;
268 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
269 <8>, <9>, <10>, <11>;
270 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
271 clock-names = "fin_pll", "mct";
272
273 mct_map: mct-map {
274 #interrupt-cells = <1>;
275 #address-cells = <0>;
276 #size-cells = <0>;
277 interrupt-map = <0 &combiner 23 3>,
278 <1 &combiner 23 4>,
279 <2 &combiner 25 2>,
280 <3 &combiner 25 3>,
281 <4 &gic 0 120 0>,
282 <5 &gic 0 121 0>,
283 <6 &gic 0 122 0>,
284 <7 &gic 0 123 0>,
285 <8 &gic 0 128 0>,
286 <9 &gic 0 129 0>,
287 <10 &gic 0 130 0>,
288 <11 &gic 0 131 0>;
289 };
290 };
291
292 nocp_mem0_0: nocp@10CA1000 { 245 nocp_mem0_0: nocp@10CA1000 {
293 compatible = "samsung,exynos5420-nocp"; 246 compatible = "samsung,exynos5420-nocp";
294 reg = <0x10CA1000 0x200>; 247 reg = <0x10CA1000 0x200>;
@@ -1570,6 +1523,11 @@
1570 pinctrl-0 = <&i2c3_bus>; 1523 pinctrl-0 = <&i2c3_bus>;
1571}; 1524};
1572 1525
1526&mct {
1527 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1528 clock-names = "fin_pll", "mct";
1529};
1530
1573&pwm { 1531&pwm {
1574 clocks = <&clock CLK_PWM>; 1532 clocks = <&clock CLK_PWM>;
1575 clock-names = "timers"; 1533 clock-names = "timers";