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authorJavier Martinez Canillas <javier@osg.samsung.com>2015-11-12 23:53:59 -0500
committerTony Lindgren <tony@atomide.com>2015-11-30 11:43:26 -0500
commitc78be3d82e0f1590be75e6900e8194066ae78638 (patch)
tree6ff299f603b5bc746d4b03b28dd815911ac7e7d6 /arch/arm/boot/dts/dra7-evm.dts
parentf70dfa6648f138ee58d176003057b83b153c406d (diff)
ARM: dts: dra7-evm: Use DRA7XX_CORE_IOPAD pinmux macro
Use the pinmux IOPAD macro to define the register absolute physical address instead of the offset from the padconf base address. This makes the DTS easier to read since matches the addresses listed in the Technical Reference Manual. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7-evm.dts')
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts254
1 files changed, 127 insertions, 127 deletions
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 864f60020124..53b3a4b97086 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -154,100 +154,100 @@
154 154
155 vtt_pin: pinmux_vtt_pin { 155 vtt_pin: pinmux_vtt_pin {
156 pinctrl-single,pins = < 156 pinctrl-single,pins = <
157 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ 157 DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
158 >; 158 >;
159 }; 159 };
160 160
161 i2c1_pins: pinmux_i2c1_pins { 161 i2c1_pins: pinmux_i2c1_pins {
162 pinctrl-single,pins = < 162 pinctrl-single,pins = <
163 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ 163 DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
164 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ 164 DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
165 >; 165 >;
166 }; 166 };
167 167
168 i2c2_pins: pinmux_i2c2_pins { 168 i2c2_pins: pinmux_i2c2_pins {
169 pinctrl-single,pins = < 169 pinctrl-single,pins = <
170 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ 170 DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
171 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ 171 DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
172 >; 172 >;
173 }; 173 };
174 174
175 i2c3_pins: pinmux_i2c3_pins { 175 i2c3_pins: pinmux_i2c3_pins {
176 pinctrl-single,pins = < 176 pinctrl-single,pins = <
177 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ 177 DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
178 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ 178 DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
179 >; 179 >;
180 }; 180 };
181 181
182 mcspi1_pins: pinmux_mcspi1_pins { 182 mcspi1_pins: pinmux_mcspi1_pins {
183 pinctrl-single,pins = < 183 pinctrl-single,pins = <
184 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */ 184 DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
185 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */ 185 DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
186 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */ 186 DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
187 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ 187 DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
188 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ 188 DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
189 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ 189 DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
190 >; 190 >;
191 }; 191 };
192 192
193 mcspi2_pins: pinmux_mcspi2_pins { 193 mcspi2_pins: pinmux_mcspi2_pins {
194 pinctrl-single,pins = < 194 pinctrl-single,pins = <
195 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */ 195 DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
196 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ 196 DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
197 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ 197 DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
198 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ 198 DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
199 >; 199 >;
200 }; 200 };
201 201
202 uart1_pins: pinmux_uart1_pins { 202 uart1_pins: pinmux_uart1_pins {
203 pinctrl-single,pins = < 203 pinctrl-single,pins = <
204 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ 204 DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
205 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ 205 DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
206 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ 206 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
207 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ 207 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
208 >; 208 >;
209 }; 209 };
210 210
211 uart2_pins: pinmux_uart2_pins { 211 uart2_pins: pinmux_uart2_pins {
212 pinctrl-single,pins = < 212 pinctrl-single,pins = <
213 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */ 213 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
214 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */ 214 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
215 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ 215 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
216 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ 216 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
217 >; 217 >;
218 }; 218 };
219 219
220 uart3_pins: pinmux_uart3_pins { 220 uart3_pins: pinmux_uart3_pins {
221 pinctrl-single,pins = < 221 pinctrl-single,pins = <
222 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ 222 DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
223 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ 223 DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
224 >; 224 >;
225 }; 225 };
226 226
227 qspi1_pins: pinmux_qspi1_pins { 227 qspi1_pins: pinmux_qspi1_pins {
228 pinctrl-single,pins = < 228 pinctrl-single,pins = <
229 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ 229 DRA7XX_CORE_IOPAD(0x344c, PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
230 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ 230 DRA7XX_CORE_IOPAD(0x3450, PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
231 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ 231 DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
232 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ 232 DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
233 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ 233 DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
234 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ 234 DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
235 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ 235 DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
236 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ 236 DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
237 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ 237 DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
238 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ 238 DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
239 >; 239 >;
240 }; 240 };
241 241
242 usb1_pins: pinmux_usb1_pins { 242 usb1_pins: pinmux_usb1_pins {
243 pinctrl-single,pins = < 243 pinctrl-single,pins = <
244 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ 244 DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
245 >; 245 >;
246 }; 246 };
247 247
248 usb2_pins: pinmux_usb2_pins { 248 usb2_pins: pinmux_usb2_pins {
249 pinctrl-single,pins = < 249 pinctrl-single,pins = <
250 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ 250 DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
251 >; 251 >;
252 }; 252 };
253 253
@@ -257,60 +257,60 @@
257 * SW5.9 (GPMC_WPN) = LOW 257 * SW5.9 (GPMC_WPN) = LOW
258 * SW5.1 (NAND_BOOTn) = HIGH */ 258 * SW5.1 (NAND_BOOTn) = HIGH */
259 pinctrl-single,pins = < 259 pinctrl-single,pins = <
260 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ 260 DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
261 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ 261 DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
262 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ 262 DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
263 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ 263 DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
264 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ 264 DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
265 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ 265 DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
266 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ 266 DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
267 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ 267 DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
268 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ 268 DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
269 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ 269 DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
270 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ 270 DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
271 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ 271 DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
272 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ 272 DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
273 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ 273 DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
274 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ 274 DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
275 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ 275 DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
276 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ 276 DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
277 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ 277 DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
278 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ 278 DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
279 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ 279 DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
280 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ 280 DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
281 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ 281 DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
282 >; 282 >;
283 }; 283 };
284 284
285 cpsw_default: cpsw_default { 285 cpsw_default: cpsw_default {
286 pinctrl-single,pins = < 286 pinctrl-single,pins = <
287 /* Slave 1 */ 287 /* Slave 1 */
288 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ 288 DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
289 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ 289 DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
290 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ 290 DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
291 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ 291 DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
292 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ 292 DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
293 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ 293 DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
294 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ 294 DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
295 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ 295 DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
296 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ 296 DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
297 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ 297 DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
298 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ 298 DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
299 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ 299 DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
300 300
301 /* Slave 2 */ 301 /* Slave 2 */
302 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ 302 DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
303 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ 303 DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
304 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ 304 DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
305 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ 305 DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
306 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ 306 DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
307 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ 307 DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
308 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ 308 DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
309 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ 309 DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
310 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ 310 DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
311 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ 311 DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
312 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ 312 DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
313 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ 313 DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
314 >; 314 >;
315 315
316 }; 316 };
@@ -318,85 +318,85 @@
318 cpsw_sleep: cpsw_sleep { 318 cpsw_sleep: cpsw_sleep {
319 pinctrl-single,pins = < 319 pinctrl-single,pins = <
320 /* Slave 1 */ 320 /* Slave 1 */
321 0x250 (MUX_MODE15) 321 DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
322 0x254 (MUX_MODE15) 322 DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
323 0x258 (MUX_MODE15) 323 DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
324 0x25c (MUX_MODE15) 324 DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
325 0x260 (MUX_MODE15) 325 DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
326 0x264 (MUX_MODE15) 326 DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
327 0x268 (MUX_MODE15) 327 DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
328 0x26c (MUX_MODE15) 328 DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
329 0x270 (MUX_MODE15) 329 DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
330 0x274 (MUX_MODE15) 330 DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
331 0x278 (MUX_MODE15) 331 DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
332 0x27c (MUX_MODE15) 332 DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
333 333
334 /* Slave 2 */ 334 /* Slave 2 */
335 0x198 (MUX_MODE15) 335 DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
336 0x19c (MUX_MODE15) 336 DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
337 0x1a0 (MUX_MODE15) 337 DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
338 0x1a4 (MUX_MODE15) 338 DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
339 0x1a8 (MUX_MODE15) 339 DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
340 0x1ac (MUX_MODE15) 340 DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
341 0x1b0 (MUX_MODE15) 341 DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
342 0x1b4 (MUX_MODE15) 342 DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
343 0x1b8 (MUX_MODE15) 343 DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
344 0x1bc (MUX_MODE15) 344 DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
345 0x1c0 (MUX_MODE15) 345 DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
346 0x1c4 (MUX_MODE15) 346 DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
347 >; 347 >;
348 }; 348 };
349 349
350 davinci_mdio_default: davinci_mdio_default { 350 davinci_mdio_default: davinci_mdio_default {
351 pinctrl-single,pins = < 351 pinctrl-single,pins = <
352 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ 352 DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
353 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 353 DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
354 >; 354 >;
355 }; 355 };
356 356
357 davinci_mdio_sleep: davinci_mdio_sleep { 357 davinci_mdio_sleep: davinci_mdio_sleep {
358 pinctrl-single,pins = < 358 pinctrl-single,pins = <
359 0x23c (MUX_MODE15) 359 DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
360 0x240 (MUX_MODE15) 360 DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
361 >; 361 >;
362 }; 362 };
363 363
364 dcan1_pins_default: dcan1_pins_default { 364 dcan1_pins_default: dcan1_pins_default {
365 pinctrl-single,pins = < 365 pinctrl-single,pins = <
366 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 366 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
367 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 367 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
368 >; 368 >;
369 }; 369 };
370 370
371 dcan1_pins_sleep: dcan1_pins_sleep { 371 dcan1_pins_sleep: dcan1_pins_sleep {
372 pinctrl-single,pins = < 372 pinctrl-single,pins = <
373 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 373 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
374 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ 374 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
375 >; 375 >;
376 }; 376 };
377 377
378 atl_pins: pinmux_atl_pins { 378 atl_pins: pinmux_atl_pins {
379 pinctrl-single,pins = < 379 pinctrl-single,pins = <
380 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ 380 DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
381 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ 381 DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
382 >; 382 >;
383 }; 383 };
384 384
385 mcasp3_pins: pinmux_mcasp3_pins { 385 mcasp3_pins: pinmux_mcasp3_pins {
386 pinctrl-single,pins = < 386 pinctrl-single,pins = <
387 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ 387 DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
388 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ 388 DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
389 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ 389 DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
390 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ 390 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
391 >; 391 >;
392 }; 392 };
393 393
394 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { 394 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
395 pinctrl-single,pins = < 395 pinctrl-single,pins = <
396 0x324 (MUX_MODE15) 396 DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
397 0x328 (MUX_MODE15) 397 DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
398 0x32c (MUX_MODE15) 398 DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
399 0x330 (MUX_MODE15) 399 DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
400 >; 400 >;
401 }; 401 };
402}; 402};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 15:11:26 -0500