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authorVineet Gupta <vgupta@synopsys.com>2015-03-05 08:43:56 -0500
committerVineet Gupta <vgupta@synopsys.com>2015-06-19 08:39:40 -0400
commit5793e273a134331d05ed904e5be3b31ccfca54c1 (patch)
treed615c70600502c888108e6c99fa365c53c68bd9d /arch/arc/kernel
parent6ffb9c8c5f59a50779109e8b0a2e1bdd4b9be5c5 (diff)
ARC: intc: split into ARCompact ISA specific, common bits
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/kernel')
-rw-r--r--arch/arc/kernel/Makefile2
-rw-r--r--arch/arc/kernel/intc-compact.c226
-rw-r--r--arch/arc/kernel/irq.c210
-rw-r--r--arch/arc/kernel/process.c3
4 files changed, 228 insertions, 213 deletions
diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile
index 024a63e90b72..cc929c0e2133 100644
--- a/arch/arc/kernel/Makefile
+++ b/arch/arc/kernel/Makefile
@@ -10,7 +10,7 @@ CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"'
10 10
11obj-y := arcksyms.o setup.o irq.o time.o reset.o ptrace.o process.o devtree.o 11obj-y := arcksyms.o setup.o irq.o time.o reset.o ptrace.o process.o devtree.o
12obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o clk.o 12obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o clk.o
13obj-y += entry-compact.o 13obj-y += entry-compact.o intc-compact.o
14 14
15obj-$(CONFIG_MODULES) += arcksyms.o module.o 15obj-$(CONFIG_MODULES) += arcksyms.o module.o
16obj-$(CONFIG_SMP) += smp.o 16obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/arc/kernel/intc-compact.c b/arch/arc/kernel/intc-compact.c
new file mode 100644
index 000000000000..fcdddb631766
--- /dev/null
+++ b/arch/arc/kernel/intc-compact.c
@@ -0,0 +1,226 @@
1/*
2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/irqdomain.h>
14#include <linux/irqchip.h>
15#include "../../drivers/irqchip/irqchip.h"
16#include <asm/irq.h>
17
18/*
19 * Early Hardware specific Interrupt setup
20 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
21 * -Called very early (start_kernel -> setup_arch -> setup_processor)
22 *
23 * what it does ?
24 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
25 */
26void arc_init_IRQ(void)
27{
28 int level_mask = 0;
29
30 /* setup any high priority Interrupts (Level2 in ARCompact jargon) */
31 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3;
32 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;
33 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6;
34
35 /*
36 * Write to register, even if no LV2 IRQs configured to reset it
37 * in case bootloader had mucked with it
38 */
39 write_aux_reg(AUX_IRQ_LEV, level_mask);
40
41 if (level_mask)
42 pr_info("Level-2 interrupts bitset %x\n", level_mask);
43}
44
45/*
46 * ARC700 core includes a simple on-chip intc supporting
47 * -per IRQ enable/disable
48 * -2 levels of interrupts (high/low)
49 * -all interrupts being level triggered
50 *
51 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
52 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
53 * below, per IRQ.
54 */
55
56static void arc_irq_mask(struct irq_data *data)
57{
58 unsigned int ienb;
59
60 ienb = read_aux_reg(AUX_IENABLE);
61 ienb &= ~(1 << data->irq);
62 write_aux_reg(AUX_IENABLE, ienb);
63}
64
65static void arc_irq_unmask(struct irq_data *data)
66{
67 unsigned int ienb;
68
69 ienb = read_aux_reg(AUX_IENABLE);
70 ienb |= (1 << data->irq);
71 write_aux_reg(AUX_IENABLE, ienb);
72}
73
74static struct irq_chip onchip_intc = {
75 .name = "ARC In-core Intc",
76 .irq_mask = arc_irq_mask,
77 .irq_unmask = arc_irq_unmask,
78};
79
80static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
81 irq_hw_number_t hw)
82{
83 /*
84 * XXX: the IPI IRQ needs to be handled like TIMER too. However ARC core
85 * code doesn't own it (like TIMER0). ISS IDU / ezchip define it
86 * in platform header which can't be included here as it goes
87 * against multi-platform image philisophy
88 */
89 if (irq == TIMER0_IRQ)
90 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
91 else
92 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
93
94 return 0;
95}
96
97static const struct irq_domain_ops arc_intc_domain_ops = {
98 .xlate = irq_domain_xlate_onecell,
99 .map = arc_intc_domain_map,
100};
101
102static struct irq_domain *root_domain;
103
104static int __init
105init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
106{
107 if (parent)
108 panic("DeviceTree incore intc not a root irq controller\n");
109
110 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
111 &arc_intc_domain_ops, NULL);
112
113 if (!root_domain)
114 panic("root irq domain not avail\n");
115
116 /* with this we don't need to export root_domain */
117 irq_set_default_host(root_domain);
118
119 return 0;
120}
121
122IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
123
124/*
125 * arch_local_irq_enable - Enable interrupts.
126 *
127 * 1. Explicitly called to re-enable interrupts
128 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
129 * which maybe in hard ISR itself
130 *
131 * Semantics of this function change depending on where it is called from:
132 *
133 * -If called from hard-ISR, it must not invert interrupt priorities
134 * e.g. suppose TIMER is high priority (Level 2) IRQ
135 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
136 * Here local_irq_enable( ) shd not re-enable lower priority interrupts
137 * -If called from soft-ISR, it must re-enable all interrupts
138 * soft ISR are low prioity jobs which can be very slow, thus all IRQs
139 * must be enabled while they run.
140 * Now hardware context wise we may still be in L2 ISR (not done rtie)
141 * still we must re-enable both L1 and L2 IRQs
142 * Another twist is prev scenario with flow being
143 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
144 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
145 * over-written (this is deficiency in ARC700 Interrupt mechanism)
146 */
147
148#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */
149
150void arch_local_irq_enable(void)
151{
152
153 unsigned long flags = arch_local_save_flags();
154
155 /* Allow both L1 and L2 at the onset */
156 flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
157
158 /* Called from hard ISR (between irq_enter and irq_exit) */
159 if (in_irq()) {
160
161 /* If in L2 ISR, don't re-enable any further IRQs as this can
162 * cause IRQ priorities to get upside down. e.g. it could allow
163 * L1 be taken while in L2 hard ISR which is wrong not only in
164 * theory, it can also cause the dreaded L1-L2-L1 scenario
165 */
166 if (flags & STATUS_A2_MASK)
167 flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK);
168
169 /* Even if in L1 ISR, allowe Higher prio L2 IRQs */
170 else if (flags & STATUS_A1_MASK)
171 flags &= ~(STATUS_E1_MASK);
172 }
173
174 /* called from soft IRQ, ideally we want to re-enable all levels */
175
176 else if (in_softirq()) {
177
178 /* However if this is case of L1 interrupted by L2,
179 * re-enabling both may cause whaco L1-L2-L1 scenario
180 * because ARC700 allows level 1 to interrupt an active L2 ISR
181 * Thus we disable both
182 * However some code, executing in soft ISR wants some IRQs
183 * to be enabled so we re-enable L2 only
184 *
185 * How do we determine L1 intr by L2
186 * -A2 is set (means in L2 ISR)
187 * -E1 is set in this ISR's pt_regs->status32 which is
188 * saved copy of status32_l2 when l2 ISR happened
189 */
190 struct pt_regs *pt = get_irq_regs();
191
192 if ((flags & STATUS_A2_MASK) && pt &&
193 (pt->status32 & STATUS_A1_MASK)) {
194 /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */
195 flags &= ~(STATUS_E1_MASK);
196 }
197 }
198
199 arch_local_irq_restore(flags);
200}
201
202#else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */
203
204/*
205 * Simpler version for only 1 level of interrupt
206 * Here we only Worry about Level 1 Bits
207 */
208void arch_local_irq_enable(void)
209{
210 unsigned long flags;
211
212 /*
213 * ARC IDE Drivers tries to re-enable interrupts from hard-isr
214 * context which is simply wrong
215 */
216 if (in_irq()) {
217 WARN_ONCE(1, "IRQ enabled from hard-isr");
218 return;
219 }
220
221 flags = arch_local_save_flags();
222 flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
223 arch_local_irq_restore(flags);
224}
225#endif
226EXPORT_SYMBOL(arch_local_irq_enable);
diff --git a/arch/arc/kernel/irq.c b/arch/arc/kernel/irq.c
index 620ec2fe32a9..2989a7bcf8a8 100644
--- a/arch/arc/kernel/irq.c
+++ b/arch/arc/kernel/irq.c
@@ -8,116 +8,10 @@
8 */ 8 */
9 9
10#include <linux/interrupt.h> 10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/irqdomain.h>
14#include <linux/irqchip.h> 11#include <linux/irqchip.h>
15#include "../../drivers/irqchip/irqchip.h"
16#include <asm/sections.h>
17#include <asm/irq.h>
18#include <asm/mach_desc.h> 12#include <asm/mach_desc.h>
19 13
20/* 14/*
21 * Early Hardware specific Interrupt setup
22 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
23 * -Called very early (start_kernel -> setup_arch -> setup_processor)
24 *
25 * what it does ?
26 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
27 */
28void arc_init_IRQ(void)
29{
30 int level_mask = 0;
31
32 /* setup any high priority Interrupts (Level2 in ARCompact jargon) */
33 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3;
34 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;
35 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6;
36
37 /*
38 * Write to register, even if no LV2 IRQs configured to reset it
39 * in case bootloader had mucked with it
40 */
41 write_aux_reg(AUX_IRQ_LEV, level_mask);
42
43 if (level_mask)
44 pr_info("Level-2 interrupts bitset %x\n", level_mask);
45}
46
47/*
48 * ARC700 core includes a simple on-chip intc supporting
49 * -per IRQ enable/disable
50 * -2 levels of interrupts (high/low)
51 * -all interrupts being level triggered
52 *
53 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
54 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
55 * below, per IRQ.
56 */
57
58static void arc_irq_mask(struct irq_data *data)
59{
60 unsigned int ienb;
61
62 ienb = read_aux_reg(AUX_IENABLE);
63 ienb &= ~(1 << data->irq);
64 write_aux_reg(AUX_IENABLE, ienb);
65}
66
67static void arc_irq_unmask(struct irq_data *data)
68{
69 unsigned int ienb;
70
71 ienb = read_aux_reg(AUX_IENABLE);
72 ienb |= (1 << data->irq);
73 write_aux_reg(AUX_IENABLE, ienb);
74}
75
76static struct irq_chip onchip_intc = {
77 .name = "ARC In-core Intc",
78 .irq_mask = arc_irq_mask,
79 .irq_unmask = arc_irq_unmask,
80};
81
82static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
83 irq_hw_number_t hw)
84{
85 if (irq == TIMER0_IRQ)
86 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
87 else
88 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
89
90 return 0;
91}
92
93static const struct irq_domain_ops arc_intc_domain_ops = {
94 .xlate = irq_domain_xlate_onecell,
95 .map = arc_intc_domain_map,
96};
97
98static struct irq_domain *root_domain;
99
100static int __init
101init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
102{
103 if (parent)
104 panic("DeviceTree incore intc not a root irq controller\n");
105
106 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
107 &arc_intc_domain_ops, NULL);
108
109 if (!root_domain)
110 panic("root irq domain not avail\n");
111
112 /* with this we don't need to export root_domain */
113 irq_set_default_host(root_domain);
114
115 return 0;
116}
117
118IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
119
120/*
121 * Late Interrupt system init called from start_kernel for Boot CPU only 15 * Late Interrupt system init called from start_kernel for Boot CPU only
122 * 16 *
123 * Since slab must already be initialized, platforms can start doing any 17 * Since slab must already be initialized, platforms can start doing any
@@ -178,107 +72,3 @@ void arc_request_percpu_irq(int irq, int cpu,
178 72
179 enable_percpu_irq(irq, 0); 73 enable_percpu_irq(irq, 0);
180} 74}
181
182/*
183 * arch_local_irq_enable - Enable interrupts.
184 *
185 * 1. Explicitly called to re-enable interrupts
186 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
187 * which maybe in hard ISR itself
188 *
189 * Semantics of this function change depending on where it is called from:
190 *
191 * -If called from hard-ISR, it must not invert interrupt priorities
192 * e.g. suppose TIMER is high priority (Level 2) IRQ
193 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
194 * Here local_irq_enable( ) shd not re-enable lower priority interrupts
195 * -If called from soft-ISR, it must re-enable all interrupts
196 * soft ISR are low prioity jobs which can be very slow, thus all IRQs
197 * must be enabled while they run.
198 * Now hardware context wise we may still be in L2 ISR (not done rtie)
199 * still we must re-enable both L1 and L2 IRQs
200 * Another twist is prev scenario with flow being
201 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
202 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
203 * over-written (this is deficiency in ARC700 Interrupt mechanism)
204 */
205
206#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */
207
208void arch_local_irq_enable(void)
209{
210
211 unsigned long flags;
212 flags = arch_local_save_flags();
213
214 /* Allow both L1 and L2 at the onset */
215 flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
216
217 /* Called from hard ISR (between irq_enter and irq_exit) */
218 if (in_irq()) {
219
220 /* If in L2 ISR, don't re-enable any further IRQs as this can
221 * cause IRQ priorities to get upside down. e.g. it could allow
222 * L1 be taken while in L2 hard ISR which is wrong not only in
223 * theory, it can also cause the dreaded L1-L2-L1 scenario
224 */
225 if (flags & STATUS_A2_MASK)
226 flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK);
227
228 /* Even if in L1 ISR, allowe Higher prio L2 IRQs */
229 else if (flags & STATUS_A1_MASK)
230 flags &= ~(STATUS_E1_MASK);
231 }
232
233 /* called from soft IRQ, ideally we want to re-enable all levels */
234
235 else if (in_softirq()) {
236
237 /* However if this is case of L1 interrupted by L2,
238 * re-enabling both may cause whaco L1-L2-L1 scenario
239 * because ARC700 allows level 1 to interrupt an active L2 ISR
240 * Thus we disable both
241 * However some code, executing in soft ISR wants some IRQs
242 * to be enabled so we re-enable L2 only
243 *
244 * How do we determine L1 intr by L2
245 * -A2 is set (means in L2 ISR)
246 * -E1 is set in this ISR's pt_regs->status32 which is
247 * saved copy of status32_l2 when l2 ISR happened
248 */
249 struct pt_regs *pt = get_irq_regs();
250 if ((flags & STATUS_A2_MASK) && pt &&
251 (pt->status32 & STATUS_A1_MASK)) {
252 /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */
253 flags &= ~(STATUS_E1_MASK);
254 }
255 }
256
257 arch_local_irq_restore(flags);
258}
259
260#else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */
261
262/*
263 * Simpler version for only 1 level of interrupt
264 * Here we only Worry about Level 1 Bits
265 */
266void arch_local_irq_enable(void)
267{
268 unsigned long flags;
269
270 /*
271 * ARC IDE Drivers tries to re-enable interrupts from hard-isr
272 * context which is simply wrong
273 */
274 if (in_irq()) {
275 WARN_ONCE(1, "IRQ enabled from hard-isr");
276 return;
277 }
278
279 flags = arch_local_save_flags();
280 flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
281 arch_local_irq_restore(flags);
282}
283#endif
284EXPORT_SYMBOL(arch_local_irq_enable);
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index e095c557afdd..b5426babd3c8 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -166,8 +166,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long usp)
166 * [L] ZOL loop inhibited to begin with - cleared by a LP insn 166 * [L] ZOL loop inhibited to begin with - cleared by a LP insn
167 * Interrupts enabled 167 * Interrupts enabled
168 */ 168 */
169 regs->status32 = STATUS_U_MASK | STATUS_L_MASK | 169 regs->status32 = STATUS_U_MASK | STATUS_L_MASK | STATUS_IE_MASK;
170 STATUS_E1_MASK | STATUS_E2_MASK;
171 170
172 /* bogus seed values for debugging */ 171 /* bogus seed values for debugging */
173 regs->lp_start = 0x10; 172 regs->lp_start = 0x10;
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