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author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-11-25 13:21:54 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-11-25 13:21:54 -0500 |
commit | ca122fe376fc43f7565e3e56e6777d06a433a4cc (patch) | |
tree | d123dd4be2b62d6c404b676ed259f7cb0c762657 /arch/arc/kernel/setup.c | |
parent | 5e2fda4776bb94ee47314e71cefaa8a104f8f4ab (diff) | |
parent | 82385732b1c9d6a22942b5fe6e48a99891cb806f (diff) |
Merge tag 'arc-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta:
- more changes for HS48 cores: supporting MMUv5, detecting new
micro-arch gizmos
- axs10x platform wiring up reset driver merged in this cycle
- ARC perf driver optimizations
* tag 'arc-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: perf: avoid vmalloc backed mmap
ARCv2: perf: optimize given that num counters <= 32
ARCv2: perf: tweak overflow interrupt
ARC: [plat-axs10x] DTS: Add reset controller node to manage ethernet reset
ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer
ARCv2: Accomodate HS48 MMUv5 by relaxing MMU ver checking
ARC: [plat-axs10x] auto-select AXS101 or AXS103 given the ISA config
Diffstat (limited to 'arch/arc/kernel/setup.c')
-rw-r--r-- | arch/arc/kernel/setup.c | 43 |
1 files changed, 39 insertions, 4 deletions
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index fb83844daeea..7ef7d9a8ff89 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c | |||
@@ -199,8 +199,10 @@ static void read_arc_build_cfg_regs(void) | |||
199 | unsigned int exec_ctrl; | 199 | unsigned int exec_ctrl; |
200 | 200 | ||
201 | READ_BCR(AUX_EXEC_CTRL, exec_ctrl); | 201 | READ_BCR(AUX_EXEC_CTRL, exec_ctrl); |
202 | cpu->extn.dual_iss_exist = 1; | 202 | cpu->extn.dual_enb = exec_ctrl & 1; |
203 | cpu->extn.dual_iss_enb = exec_ctrl & 1; | 203 | |
204 | /* dual issue always present for this core */ | ||
205 | cpu->extn.dual = 1; | ||
204 | } | 206 | } |
205 | } | 207 | } |
206 | 208 | ||
@@ -253,7 +255,7 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) | |||
253 | cpu_id, cpu->name, cpu->details, | 255 | cpu_id, cpu->name, cpu->details, |
254 | is_isa_arcompact() ? "ARCompact" : "ARCv2", | 256 | is_isa_arcompact() ? "ARCompact" : "ARCv2", |
255 | IS_AVAIL1(cpu->isa.be, "[Big-Endian]"), | 257 | IS_AVAIL1(cpu->isa.be, "[Big-Endian]"), |
256 | IS_AVAIL3(cpu->extn.dual_iss_exist, cpu->extn.dual_iss_enb, " Dual-Issue")); | 258 | IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue ")); |
257 | 259 | ||
258 | n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ", | 260 | n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ", |
259 | IS_AVAIL1(cpu->extn.timer0, "Timer0 "), | 261 | IS_AVAIL1(cpu->extn.timer0, "Timer0 "), |
@@ -293,11 +295,26 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) | |||
293 | 295 | ||
294 | if (cpu->bpu.ver) | 296 | if (cpu->bpu.ver) |
295 | n += scnprintf(buf + n, len - n, | 297 | n += scnprintf(buf + n, len - n, |
296 | "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n", | 298 | "BPU\t\t: %s%s match, cache:%d, Predict Table:%d", |
297 | IS_AVAIL1(cpu->bpu.full, "full"), | 299 | IS_AVAIL1(cpu->bpu.full, "full"), |
298 | IS_AVAIL1(!cpu->bpu.full, "partial"), | 300 | IS_AVAIL1(!cpu->bpu.full, "partial"), |
299 | cpu->bpu.num_cache, cpu->bpu.num_pred); | 301 | cpu->bpu.num_cache, cpu->bpu.num_pred); |
300 | 302 | ||
303 | if (is_isa_arcv2()) { | ||
304 | struct bcr_lpb lpb; | ||
305 | |||
306 | READ_BCR(ARC_REG_LPB_BUILD, lpb); | ||
307 | if (lpb.ver) { | ||
308 | unsigned int ctl; | ||
309 | ctl = read_aux_reg(ARC_REG_LPB_CTRL); | ||
310 | |||
311 | n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s", | ||
312 | lpb.entries, | ||
313 | IS_DISABLED_RUN(!ctl)); | ||
314 | } | ||
315 | } | ||
316 | |||
317 | n += scnprintf(buf + n, len - n, "\n"); | ||
301 | return buf; | 318 | return buf; |
302 | } | 319 | } |
303 | 320 | ||
@@ -326,6 +343,24 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) | |||
326 | cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), | 343 | cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), |
327 | cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); | 344 | cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); |
328 | 345 | ||
346 | if (is_isa_arcv2()) { | ||
347 | |||
348 | /* Error Protection: ECC/Parity */ | ||
349 | struct bcr_erp erp; | ||
350 | READ_BCR(ARC_REG_ERP_BUILD, erp); | ||
351 | |||
352 | if (erp.ver) { | ||
353 | struct ctl_erp ctl; | ||
354 | READ_BCR(ARC_REG_ERP_CTRL, ctl); | ||
355 | |||
356 | /* inverted bits: 0 means enabled */ | ||
357 | n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n", | ||
358 | IS_AVAIL3(erp.ic, !ctl.dpi, "IC "), | ||
359 | IS_AVAIL3(erp.dc, !ctl.dpd, "DC "), | ||
360 | IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU ")); | ||
361 | } | ||
362 | } | ||
363 | |||
329 | n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n", | 364 | n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n", |
330 | EF_ARC_OSABI_CURRENT >> 8, | 365 | EF_ARC_OSABI_CURRENT >> 8, |
331 | EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ? | 366 | EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ? |