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authorLinus Torvalds <torvalds@linux-foundation.org>2016-05-19 12:46:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-05-19 12:46:18 -0400
commit0efacbbaee1e94e9942da0912f5b46ffd45a74bd (patch)
treea17933437de955f4ce5e74760610bab75f2ae385 /arch/arc/kernel/mcip.c
parentf4f27d0028aabce57e44c16c2fdefccd6310d2f3 (diff)
parent776d7f1694a7d678291354a05f0243965708306a (diff)
Merge tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta: "We have a relatively big changeset for ARC for 4.7. The highlight is support for EZChip (now Mellanox) NPS-400 network processor, a 400-Gb throughput C-programmable packet processor based on ARC700 cores from Synopsys. See http://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf Also present are irqchip and clocksource drivers for NPS as agreed with respective maintainers to go via ARC tree due to an soc header dependency. I have the needed ACKs from Jason, Marc, Daniel. You might run into a trivial merge conflict in drivers/irqchip/* This EZChip platform support required some deep changes in ARC architecture code and also opportunity to cleanup past sins (legacy irq domains, missing irq domain lookup, hard coded timer irqs...) Summary: - Support for EZChip (now Mellanox) NPS-400 Network processor based on ARC700 - NPS interrupt controller and clocksource drivers - ARC timers probed off DT - ARC iqrchips switching to linear domain (upgrade from legacy domains)" * tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (37 commits) arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core arc: axs10x: Add DT bindings for I2S PLL Clock ARC: pae: STRICT_MM_TYPECHECKS was broken ARC: Add eznps platform to Kconfig and Makefile ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE ARC: [plat-eznps] Use dedicated cpu_relax() ARC: [plat-eznps] Use dedicated identity auxiliary register. ARC: [plat-eznps] Use dedicated SMP barriers ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg ARC: [plat-eznps] Use dedicated user stack top ARC: [plat-eznps] Add eznps platform ARC: [plat-eznps] Add eznps board defconfig and dts ARC: Mark secondary cpu online only after all HW setup is done ARC: rwlock: disable interrupts in !LLSC variant ARC: Make vmalloc size configurable ARC: clean out UAPI byteorder.h clean off Kconfig symbol irqchip: add nps Internal and external irqchips clocksource: Add NPS400 timers driver soc: Support for EZchip SoC Documentation: Add EZchip vendor to binding list ...
Diffstat (limited to 'arch/arc/kernel/mcip.c')
-rw-r--r--arch/arc/kernel/mcip.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
index c41c364b926c..72f9179b1a24 100644
--- a/arch/arc/kernel/mcip.c
+++ b/arch/arc/kernel/mcip.c
@@ -15,9 +15,6 @@
15#include <asm/mcip.h> 15#include <asm/mcip.h>
16#include <asm/setup.h> 16#include <asm/setup.h>
17 17
18#define IPI_IRQ 19
19#define SOFTIRQ_IRQ 21
20
21static char smp_cpuinfo_buf[128]; 18static char smp_cpuinfo_buf[128];
22static int idu_detected; 19static int idu_detected;
23 20
@@ -116,15 +113,13 @@ static void mcip_probe_n_setup(void)
116 IS_AVAIL1(mp.dbg, "DEBUG "), 113 IS_AVAIL1(mp.dbg, "DEBUG "),
117 IS_AVAIL1(mp.gfrc, "GFRC")); 114 IS_AVAIL1(mp.gfrc, "GFRC"));
118 115
116 cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
119 idu_detected = mp.idu; 117 idu_detected = mp.idu;
120 118
121 if (mp.dbg) { 119 if (mp.dbg) {
122 __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); 120 __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
123 __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); 121 __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
124 } 122 }
125
126 if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc)
127 panic("kernel trying to use non-existent GFRC\n");
128} 123}
129 124
130struct plat_smp_ops plat_smp_ops = { 125struct plat_smp_ops plat_smp_ops = {