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authorLinus Torvalds <torvalds@linux-foundation.org>2016-05-19 12:46:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-05-19 12:46:18 -0400
commit0efacbbaee1e94e9942da0912f5b46ffd45a74bd (patch)
treea17933437de955f4ce5e74760610bab75f2ae385 /arch/arc/kernel/intc-compact.c
parentf4f27d0028aabce57e44c16c2fdefccd6310d2f3 (diff)
parent776d7f1694a7d678291354a05f0243965708306a (diff)
Merge tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta: "We have a relatively big changeset for ARC for 4.7. The highlight is support for EZChip (now Mellanox) NPS-400 network processor, a 400-Gb throughput C-programmable packet processor based on ARC700 cores from Synopsys. See http://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf Also present are irqchip and clocksource drivers for NPS as agreed with respective maintainers to go via ARC tree due to an soc header dependency. I have the needed ACKs from Jason, Marc, Daniel. You might run into a trivial merge conflict in drivers/irqchip/* This EZChip platform support required some deep changes in ARC architecture code and also opportunity to cleanup past sins (legacy irq domains, missing irq domain lookup, hard coded timer irqs...) Summary: - Support for EZChip (now Mellanox) NPS-400 Network processor based on ARC700 - NPS interrupt controller and clocksource drivers - ARC timers probed off DT - ARC iqrchips switching to linear domain (upgrade from legacy domains)" * tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (37 commits) arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core arc: axs10x: Add DT bindings for I2S PLL Clock ARC: pae: STRICT_MM_TYPECHECKS was broken ARC: Add eznps platform to Kconfig and Makefile ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE ARC: [plat-eznps] Use dedicated cpu_relax() ARC: [plat-eznps] Use dedicated identity auxiliary register. ARC: [plat-eznps] Use dedicated SMP barriers ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg ARC: [plat-eznps] Use dedicated user stack top ARC: [plat-eznps] Add eznps platform ARC: [plat-eznps] Add eznps board defconfig and dts ARC: Mark secondary cpu online only after all HW setup is done ARC: rwlock: disable interrupts in !LLSC variant ARC: Make vmalloc size configurable ARC: clean out UAPI byteorder.h clean off Kconfig symbol irqchip: add nps Internal and external irqchips clocksource: Add NPS400 timers driver soc: Support for EZchip SoC Documentation: Add EZchip vendor to binding list ...
Diffstat (limited to 'arch/arc/kernel/intc-compact.c')
-rw-r--r--arch/arc/kernel/intc-compact.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/arc/kernel/intc-compact.c b/arch/arc/kernel/intc-compact.c
index 224d1c3aa9c4..c5cceca36118 100644
--- a/arch/arc/kernel/intc-compact.c
+++ b/arch/arc/kernel/intc-compact.c
@@ -14,6 +14,8 @@
14#include <linux/irqchip.h> 14#include <linux/irqchip.h>
15#include <asm/irq.h> 15#include <asm/irq.h>
16 16
17#define TIMER0_IRQ 3 /* Fixed by ISA */
18
17/* 19/*
18 * Early Hardware specific Interrupt setup 20 * Early Hardware specific Interrupt setup
19 * -Platform independent, needed for each CPU (not foldable into init_IRQ) 21 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
@@ -79,8 +81,9 @@ static struct irq_chip onchip_intc = {
79static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq, 81static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
80 irq_hw_number_t hw) 82 irq_hw_number_t hw)
81{ 83{
82 switch (irq) { 84 switch (hw) {
83 case TIMER0_IRQ: 85 case TIMER0_IRQ:
86 irq_set_percpu_devid(irq);
84 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq); 87 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
85 break; 88 break;
86 default: 89 default:
@@ -94,21 +97,23 @@ static const struct irq_domain_ops arc_intc_domain_ops = {
94 .map = arc_intc_domain_map, 97 .map = arc_intc_domain_map,
95}; 98};
96 99
97static struct irq_domain *root_domain;
98
99static int __init 100static int __init
100init_onchip_IRQ(struct device_node *intc, struct device_node *parent) 101init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
101{ 102{
103 struct irq_domain *root_domain;
104
102 if (parent) 105 if (parent)
103 panic("DeviceTree incore intc not a root irq controller\n"); 106 panic("DeviceTree incore intc not a root irq controller\n");
104 107
105 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0, 108 root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS,
106 &arc_intc_domain_ops, NULL); 109 &arc_intc_domain_ops, NULL);
107
108 if (!root_domain) 110 if (!root_domain)
109 panic("root irq domain not avail\n"); 111 panic("root irq domain not avail\n");
110 112
111 /* with this we don't need to export root_domain */ 113 /*
114 * Needed for primary domain lookup to succeed
115 * This is a primary irqchip, and can never have a parent
116 */
112 irq_set_default_host(root_domain); 117 irq_set_default_host(root_domain);
113 118
114 return 0; 119 return 0;